[llvm] [IR][REVEC] Define llvm.vector.repeat intrinsic (PR #208212)

[Paul Walker via llvm-commits]

=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
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In-Reply-To: <llvm.org/llvm/llvm-project/pull/208212 at github.com>


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@@ -525,3 +525,20 @@ TEST_F(SelectionDAGNodeConstructionTest, ExpandPartialReduceSUMLA) {
   EXPECT_EQ(NumSignExtends, 1u);
   EXPECT_EQ(NumZeroExtends, 1u);
 }
+
+TEST_F(SelectionDAGNodeConstructionTest, VectorRepeat) {
+  SDLoc DL;
+  SDValue V1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                   Register::index2VirtReg(1), MVT::v1i32);
+  SDValue NXV1 = DAG->getNode(ISD::VECTOR_REPEAT, DL, MVT::nxv1i32, V1);
+
+  ASSERT_EQ(NXV1.getOpcode(), ISD::SPLAT_VECTOR);
+  ASSERT_EQ(NXV1.getOperand(0).getOpcode(), ISD::EXTRACT_VECTOR_ELT);
+  EXPECT_EQ(NXV1.getOperand(0).getOperand(0), V1);
+  EXPECT_TRUE(isNullConstant(NXV1.getOperand(0).getOperand(1)));
+
+  SDValue V2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL,
+                                   Register::index2VirtReg(2), MVT::v2i32);
+  SDValue NXV2 = DAG->getNode(ISD::VECTOR_REPEAT, DL, MVT::nxv2i32, V2);
+  EXPECT_EQ(NXV2.getOpcode(), ISD::VECTOR_REPEAT);
----------------
paulwalker-arm wrote:

It was just the V2 test. I agree verifying the nxv1 canonicalisation has value. There's nothing I cannot live with so if you see value then I'm happy to keep it.

https://github.com/llvm/llvm-project/pull/208212