[llvm] [IR][REVEC] Define llvm.vector.repeat intrinsic (PR #208212)

[Paul Walker via llvm-commits]

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@@ -0,0 +1,6 @@
+; RUN: opt -passes=verify -disable-output < %s
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paulwalker-arm wrote:

I'm not sure what this is testing?  Verifier tests normally use llvm-as to ensure the expected error messages are generated.

https://github.com/llvm/llvm-project/pull/208212