[llvm] [IR][REVEC] Define llvm.vector.repeat intrinsic (PR #208212)

Paul Walker via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 23 06:09:05 PDT 2026


=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>,
=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/208212 at github.com>


================
@@ -17807,6 +17792,28 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerVECTOR_REPEAT(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  assert(isUnpackedType(VT, DAG) && "Expected an unpacked vector type!");
+
+  // Broadcast into a packed container before extracting the low lanes, which
+  // places the result elements at the spacing required by the unpacked type.
+  EVT PackedVT = getPackedSVEVectorVT(VT.getVectorElementType());
+  SDValue Src = Op.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  unsigned NumConcat =
+      PackedVT.getVectorMinNumElements() / SrcVT.getVectorMinNumElements();
+  SmallVector<SDValue, 8> Ops(NumConcat, Src);
+  EVT PackedSrcVT = SrcVT.changeVectorElementCount(
+      *DAG.getContext(),
+      ElementCount::getFixed(PackedVT.getVectorMinNumElements()));
+  SDValue PackedSrc = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedSrcVT, Ops);
+  SDValue Broadcast = DAG.getNode(ISD::VECTOR_REPEAT, DL, PackedVT, PackedSrc);
----------------
paulwalker-arm wrote:

Yes, DAGCombine undoing the lowering is my concern.  That said, no such combine exists so I'm happy to defer the change until it does.

https://github.com/llvm/llvm-project/pull/208212


More information about the llvm-commits mailing list