[llvm] [RISCV] Reject XTHeadMemIdx load-update with rd == rs1 (PR #225271)

[Sam Elliott via llvm-commits]

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@@ -62,6 +62,14 @@ def immfour : RISCVOp {
 
 def tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
 
+def th_memidx_rs1 : RegisterOperand<GPR> {
+  let DecoderMethod = "decodeTHMemIdxRs1Operand";
+}
+
+def th_mempair_rs1 : RegisterOperand<GPR> {
+  let DecoderMethod = "decodeTHMemPairRs1Operand";
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lenary wrote:

My understanding is that if you have `hasCompleteDecoder = false` then after failing to decode that operand, you're in one of two states:
- You have a fallback for the same field, so you're in an OPC_Scope, and can try the next alternative for the same field before failing.
- There is no fallback for the same field, so you're not in an OPC_Scope, and `decodeInstruction` will return that it failed to disassemble.



https://github.com/llvm/llvm-project/pull/225271