[llvm] [AMDGPU][SIMemoryLegalizer] Ensure LDS -> DMA hazards respect fences (PR #220288)

[Sameer Sahasrabuddhe via llvm-commits]

ssahasra wrote:

So what's the plan for this PR, post #224065? Note that the memory model that we are drafting for async DMA operations will always cause the DMA to wait for previous LDS operations. Do people on this PR have reason to believe that such a model will leave performance on the table? There is room to invent metadata on the prior LDS operations which allow the subsequent DMA operation to not wait for them. But would that be over-design?

https://github.com/llvm/llvm-project/pull/220288