[llvm] [AArch64MIPeepholeOpt] Coalesce sibling base-address materializations (PR #223682)

[via llvm-commits]

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@@ -0,0 +1,101 @@
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-mi-peephole-opt \
+# RUN:   -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=SHARED
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-mi-peephole-opt \
+# RUN:   -aarch64-base-address-cse=0 -o - %s | FileCheck %s --check-prefix=NOBASECSE
+
+--- |
+  define void @share_sub_i32(ptr %p) { ret void }
+  define void @share_sub_i32_3sibling(ptr %p) { ret void }
+  define void @share_add_i64(ptr %p) { ret void }
+...
+---
+name: share_sub_i32
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    %0:gpr64common = COPY $x0
+    %1:gpr64common = SUBXri %0, 400, 0
+    %2:gpr64common = SUBXri %0, 396, 0
+    %3:gpr32 = LDRWui killed %1, 0
+    %4:gpr32 = LDRWui killed %2, 0
+    $w0 = COPY %3
+    $w1 = COPY %4
+    RET_ReallyLR
+
+# SHARED-LABEL: name: share_sub_i32
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whokeke wrote:

Done — regenerated all CHECK lines with update_mir_test_checks.py. 

https://github.com/llvm/llvm-project/pull/223682