[llvm] [AArch64MIPeepholeOpt] Coalesce sibling base-address materializations (PR #223682)

[via llvm-commits]

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@@ -0,0 +1,101 @@
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-mi-peephole-opt \
+# RUN:   -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=SHARED
+# RUN: llc -mtriple=aarch64 -run-pass=aarch64-mi-peephole-opt \
+# RUN:   -aarch64-base-address-cse=0 -o - %s | FileCheck %s --check-prefix=NOBASECSE
+
+--- |
+  define void @share_sub_i32(ptr %p) { ret void }
+  define void @share_sub_i32_3sibling(ptr %p) { ret void }
+  define void @share_add_i64(ptr %p) { ret void }
+...
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whokeke wrote:

Done — removed the --- | define void @... { ret void } ... ... block. That stub only exists so MIR bodies can reference IR values via :: (load ... from %ir.foo)-style memory-operand comments; since none of the three MIR functions in this file use that syntax, the stub wasn't serving any purpose. Confirmed the test still passes without it.

https://github.com/llvm/llvm-project/pull/223682