[llvm] [LV] Reduce register pressure of RISC-V outer loop reduction. (PR #208621)

[Florian Hahn via llvm-commits]

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@@ -653,3 +653,46 @@ void VPlanTransforms::convertEVLExitCond(VPlan &Plan) {
   LatchBr->setOperand(
       0, Builder.createICmp(CmpInst::ICMP_EQ, AVLNext, Plan.getZero(AVLTy)));
 }
+
+static void wrapPredicateMerge(VPWidenIntrinsicRecipe *VPMerge) {
+  assert(VPMerge->getVectorIntrinsicID() == Intrinsic::vp_merge);
+  VPSingleDefRecipe *InLoopOp =
+      dyn_cast<VPSingleDefRecipe>(VPMerge->getOperand(1));
+  // TODO: Support cmp-select reductions.
+  if (!InLoopOp || !isa<VPWidenRecipe, VPWidenIntrinsicRecipe>(InLoopOp) ||
+      match(InLoopOp, m_Select(m_VPValue(), m_VPValue(), m_VPValue())))
+    return;
+
+  // Only convert the in-loop operations with tail-folding predication to
+  // expression recipe.
+  if (!all_of(VPMerge->users(), [](VPUser *U) {
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fhahn wrote:

does this match the logic in `RISCVVectorPeephole.cpp`? After a quick glance, it looks like it requires some opreands of the merge to be single-uses?

https://github.com/llvm/llvm-project/pull/208621