[llvm] [LV] Reduce register pressure of RISC-V outer loop reduction. (PR #208621)

[Florian Hahn via llvm-commits]

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@@ -653,3 +653,46 @@ void VPlanTransforms::convertEVLExitCond(VPlan &Plan) {
   LatchBr->setOperand(
       0, Builder.createICmp(CmpInst::ICMP_EQ, AVLNext, Plan.getZero(AVLTy)));
 }
+
+static void wrapPredicateMerge(VPWidenIntrinsicRecipe *VPMerge) {
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fhahn wrote:

would be good to document. also, if this is RISCV specific (and not a generic fold for vp_merge), this should be TTI driven.

https://github.com/llvm/llvm-project/pull/208621