[llvm] [AArch64] Match scalar_to_vector of frozen extended loads (PR #224213)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Cyrus Ding (dingcyrus)

<details>
<summary>Changes</summary>

DAGCombiner sinks freeze below SCALAR_TO_VECTOR (freeze(stv(x)) folds to stv(freeze(x)) when only element zero is demanded, and visitFREEZE pushes freeze through single-use poison-propagating ops). A freeze of a load can never be folded away, because the loaded value may be poison in memory, so scalar_to_vector(freeze(extload)) is a common shape reaching ISel.

The ExtLoad8_16AllModes / ExtLoad8_16_32AllModes scalar_to_vector patterns only match plain zextload/extload scalars, so the frozen shape fell back to a GPR load plus fmov instead of the direct ldr b/h/s SIMD-register forms.

Add PatFrags that additionally match a freeze of the extended load and use them in the scalar_to_vector pattern instantiations. Matching through the freeze is safe: the LDRB/LDRH/LDRS forms write a fully defined value into the destination register, which is exactly what freeze promises, and the load stays visible so the memory operand is attached to the selected instruction.

Fixes #<!-- -->224181

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Full diff: https://github.com/llvm/llvm-project/pull/224213.diff


2 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+35-9) 
- (added) llvm/test/CodeGen/AArch64/scalar-to-vector-frozen-load.ll (+104) 


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</details>


https://github.com/llvm/llvm-project/pull/224213