[llvm] [AArch64] Add custom v2i32->v2i16 store lowering. (PR #223659)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 15 04:30:24 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
This extends the existing v4i16->v4i8 lowering to handle v2i32->v2i16 stores too, which in general helps keep the number of instructions down.
---
Patch is 26.43 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223659.diff
21 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+13-11)
- (modified) llvm/test/CodeGen/AArch64/add.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/andorxor.ll (+11-14)
- (modified) llvm/test/CodeGen/AArch64/arm64-rev.ll (+5-3)
- (modified) llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/bitcast.ll (+3-8)
- (modified) llvm/test/CodeGen/AArch64/ctlz.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/ctpop.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/cttz.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/ldst-opt.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/mul.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/neon-rshrn.ll (+3-6)
- (modified) llvm/test/CodeGen/AArch64/neon-truncstore.ll (+7-11)
- (modified) llvm/test/CodeGen/AArch64/sadd_sat_vec.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/shufflevector.ll (+5-9)
- (modified) llvm/test/CodeGen/AArch64/ssub_sat_vec.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/store.ll (+13-7)
- (modified) llvm/test/CodeGen/AArch64/sub.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/uadd_sat_vec.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/usub_sat_vec.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll (+42-41)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e01cb8f77732f..118a80c3f32e8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1507,6 +1507,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
+ setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
setOperationAction(ISD::BITCAST, MVT::i2, Custom);
setOperationAction(ISD::BITCAST, MVT::i4, Custom);
@@ -7778,7 +7779,8 @@ static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
EVT VT, EVT MemVT,
SelectionDAG &DAG) {
assert(VT.isVector() && "VT should be a vector type");
- assert(MemVT == MVT::v4i8 && VT == MVT::v4i16);
+ assert((MemVT == MVT::v4i8 && VT == MVT::v4i16) ||
+ (MemVT == MVT::v2i16 && VT == MVT::v2i32));
SDValue Value = ST->getValue();
@@ -7789,20 +7791,19 @@ static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
// xtn v0.8b, v0.8h
// str s0, [x0]
- SDValue Poison = DAG.getPOISON(MVT::i16);
- SDValue PoisonVec =
- DAG.getBuildVector(MVT::v4i16, DL, {Poison, Poison, Poison, Poison});
-
+ SDValue PoisonVec = DAG.getPOISON(VT);
+ EVT DblVT = VT.getDoubleNumVectorElementsVT(*DAG.getContext());
+ EVT DblMemVT = MemVT.getDoubleNumVectorElementsVT(*DAG.getContext());
SDValue TruncExt =
- DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, Value, PoisonVec);
- SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt);
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, DblVT, Value, PoisonVec);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, DblMemVT, TruncExt);
Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc);
SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
Trunc, DAG.getConstant(0, DL, MVT::i64));
- return DAG.getStore(ST->getChain(), DL, ExtractTrunc,
- ST->getBasePtr(), ST->getMemOperand());
+ return DAG.getStore(ST->getChain(), DL, ExtractTrunc, ST->getBasePtr(),
+ ST->getMemOperand());
}
static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
@@ -8067,8 +8068,9 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
return scalarizeVectorStore(StoreNode, DAG);
}
- if (StoreNode->isTruncatingStore() && VT == MVT::v4i16 &&
- MemVT == MVT::v4i8) {
+ if (StoreNode->isTruncatingStore() &&
+ ((VT == MVT::v4i16 && MemVT == MVT::v4i8) ||
+ (VT == MVT::v2i32 && MemVT == MVT::v2i16))) {
return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);
}
} else if (MemVT == MVT::i128 && StoreNode->isVolatile()) {
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index f71c58f16bf36..40c3e6560edcb 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -198,9 +198,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index 6e1f7710b4cd8..adf560cc97362 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -608,11 +608,10 @@ define void @and_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: and_v2i16:
@@ -641,12 +640,11 @@ define void @or_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_v2i16:
@@ -675,12 +673,11 @@ define void @xor_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: xor_v2i16:
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index 5980e3214d0da..42afc0831d914 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -464,9 +464,11 @@ define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp
; CHECK-SD-LABEL: test_vrev64:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr q0, [x0]
-; CHECK-SD-NEXT: mov h1, v0[5]
-; CHECK-SD-NEXT: st1.h { v0 }[6], [x1]
-; CHECK-SD-NEXT: str h1, [x1, #2]
+; CHECK-SD-NEXT: mov h1, v0[6]
+; CHECK-SD-NEXT: umov.h w8, v0[5]
+; CHECK-SD-NEXT: mov.s v1[1], w8
+; CHECK-SD-NEXT: xtn.4h v0, v1
+; CHECK-SD-NEXT: str s0, [x1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vrev64:
diff --git a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
index 1486b3a8b9cff..ddbd6fc839441 100644
--- a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
@@ -8,7 +8,7 @@
; CHECK: str x30, [sp, #-16]!
; CHECK: adrp x8, q
; CHECK: ldr x8, [x8, :lo12:q]
-; CHECK: stp xzr, xzr, [x8]
+; CHECK: str q0, [x8]
; CHECK: bl f
@q = external dso_local unnamed_addr global ptr, align 8
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index f293934572b16..efac5578b8df6 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -86,10 +86,8 @@ define i32 @bitcast_v2i16_i32(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
@@ -372,10 +370,7 @@ define <4 x i8> @bitcast_v2i16_v4i8(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr s0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: add sp, sp, #16
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index 968fd6d7c9813..0b8e18482f1ea 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -133,9 +133,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-SD-NEXT: clz v1.2s, v1.2s
; CHECK-SD-NEXT: sub v0.2s, v1.2s, v0.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index 00d3542988272..345449b3149a7 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -131,9 +131,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: cnt v0.8b, v0.8b
; CHECK-SD-NEXT: uaddlp v0.4h, v0.8b
; CHECK-SD-NEXT: uaddlp v0.2s, v0.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index a7cb028537088..8f46f389cb68e 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -191,9 +191,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: rev32 v0.8b, v0.8b
; CHECK-SD-NEXT: rbit v0.8b, v0.8b
; CHECK-SD-NEXT: clz v0.2s, v0.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.ll b/llvm/test/CodeGen/AArch64/ldst-opt.ll
index e002f3fba9d5b..6bb9bcc32be7c 100644
--- a/llvm/test/CodeGen/AArch64/ldst-opt.ll
+++ b/llvm/test/CodeGen/AArch64/ldst-opt.ll
@@ -2260,9 +2260,8 @@ define void @trunc_splat_zero(ptr %ptr) {
define void @trunc_splat(ptr %ptr) {
; CHECK-LABEL: trunc_splat:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #42 // =0x2a
-; CHECK-NEXT: movk w8, #42, lsl #16
-; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: movi v0.8h, #42
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
store <2 x i16> <i16 42, i16 42>, ptr %ptr, align 4
ret void
diff --git a/llvm/test/CodeGen/AArch64/mul.ll b/llvm/test/CodeGen/AArch64/mul.ll
index dfd6f9801e54b..c89d1c290fa16 100644
--- a/llvm/test/CodeGen/AArch64/mul.ll
+++ b/llvm/test/CodeGen/AArch64/mul.ll
@@ -211,9 +211,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: umull v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/neon-rshrn.ll b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
index 4cc8df59c95db..599709f0741f1 100644
--- a/llvm/test/CodeGen/AArch64/neon-rshrn.ll
+++ b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
@@ -865,12 +865,9 @@ entry:
define void @rshrn_v2i32_4(<2 x i32> %a, ptr %p) {
; CHECK-LABEL: rshrn_v2i32_4:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.2s, #8
-; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #4
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: rshrn v0.4h, v0.4s, #4
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
entry:
%b = add <2 x i32> %a, <i32 8, i32 8>
diff --git a/llvm/test/CodeGen/AArch64/neon-truncstore.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
index 9666cd705cbf6..9ae9c1987e4bd 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncstore.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -41,10 +41,8 @@ define void @v8i64_v8i32(<8 x i64> %a, ptr %result) {
define void @v2i32_v2i16(<2 x i32> %a, ptr %result) {
; CHECK-LABEL: v2i32_v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%b = trunc <2 x i32> %a to <2 x i16>
store <2 x i16> %b, ptr %result
@@ -213,9 +211,9 @@ define void @v32i16_v32i8(<32 x i16> %a, ptr %result) {
define void @extract_v2i16_v8i16(<8 x i16> %a, ptr %p) {
; CHECK-LABEL: extract_v2i16_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%c = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
store <2 x i16> %c, ptr %p
@@ -235,10 +233,8 @@ define void @extract_v4i16_v8i16(<8 x i16> %a, ptr %p) {
define void @extract_v2i16_v4i16(<4 x i16> %a, ptr %p) {
; CHECK-LABEL: extract_v2i16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%c = shufflevector <4 x i16> %a, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
store <2 x i16> %c, ptr %p
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 8d3a9ee8beba4..2021d7ed468a7 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -203,9 +203,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: sqadd v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/shufflevector.ll b/llvm/test/CodeGen/AArch64/shufflevector.ll
index 9fd5e65086782..59e406f64b14b 100644
--- a/llvm/test/CodeGen/AArch64/shufflevector.ll
+++ b/llvm/test/CodeGen/AArch64/shufflevector.ll
@@ -287,10 +287,8 @@ define i32 @shufflevector_v2i16(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: ext v0.8b, v0.8b, v1.8b, #4
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
@@ -491,11 +489,9 @@ define i32 @shufflevector_v2i16_zeroes(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: dup v1.2s, v0.s[0]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: mov s1, v1.s[1]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: dup v0.2s, v0.s[0]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index f4359edcc1bbd..1f92884f02f71 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -203,9 +203,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/store.ll b/llvm/test/CodeGen/AArch64/store.ll
index 72f1cb5a0b22f..96c3847af9b9e 100644
--- a/llvm/test/CodeGen/AArch64/store.ll
+++ b/llvm/test/CodeGen/AArch64/store.ll
@@ -169,13 +169,19 @@ define void @store_v32i8(<32 x i8> %a, ptr %ptr){
}
define void @store_v2i16(<2 x i16> %a, ptr %ptr){
-; CHECK-LABEL: store_v2i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: store_v2i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: store_v2i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: str h0, [x0]
+; CHECK-GI-NEXT: str h1, [x0, #2]
+; CHECK-GI-NEXT: ret
store <2 x i16> %a, ptr %ptr
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sub.ll b/llvm/test/CodeGen/AArch64/sub.ll
index 4516cf821af20..70f7e43b73584 100644
--- a/llvm/test/CodeGen/AArch64/sub.ll
+++ b/llvm/test/CodeGen/AArch64/sub.ll
@@ -198,9 +198,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: usubl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index 3f9f420d8f2bb..6768c733af47f 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -192,9 +192,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: umin v0.2s, v0.2s, v2.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index c8f59a95addb3..04a67ecf534c6 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -192,9 +192,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-SD-NEXT: uqsub v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll b/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
index 538dbf94608c7..20b0959ab84a3 100644
--- a/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
+++ b/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
@@ -15,9 +15,9 @@ define <16 x i8> @load_v3i8(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: umov w8, v0.h[0]
@@ -51,10 +51,10 @...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223659
More information about the llvm-commits
mailing list