[llvm] [GlobalISel] [AArch64] Skip redundant shift amount masking during isel (PR #223136)

[Craig Topper via llvm-commits]

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@@ -257,6 +257,43 @@ void applyAArch64MulConstCombine(
   MI.eraseFromParent();
 }
 
+/// Skip redundant AND on shift amounts. AArch64 shift instructions only
+/// use the low 5 bits (i32) or 6 bits (i64) of the shift amount, so an
+/// AND that masks to exactly a byte or halfword is redundant.
+bool matchShiftAmountMask(MachineInstr &MI, MachineRegisterInfo &MRI,
+                          Register &NewShiftReg) {
+  assert(MI.getOpcode() == TargetOpcode::G_SHL ||
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topperc wrote:

This optimization cannot be done on generic nodes. The semantics of the generic nodes are that all bits of the shift amount are used regardless of what the target instructions do.

https://github.com/llvm/llvm-project/pull/223136