[llvm] [AMDGPU][GlobalISel] Narrow 64-bit shifts when KnownBits proves the amount is >= 32 (PR #215500)

[Arseniy Obolenskiy via llvm-commits]

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@@ -1458,6 +1458,35 @@ define i64 @v_shl_i64_31(i64 %value) {
   ret i64 %result
 }
 
+define i64 @v_shl_i64_or32(i64 %value, i32 %amount) {
+; GCN-LABEL: v_shl_i64_or32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_and_b32_e32 v1, 31, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, v1, v0
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_shl_i64_or32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_and_b32_e32 v1, 31, v2
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, v1, v0
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_shl_i64_or32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_and_b32_e32 v1, 31, v2
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v1, v1, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+  %amount.or = or i32 %amount, 32
+  %amount.ext = zext i32 %amount.or to i64
+  %result = shl i64 %value, %amount.ext
+  ret i64 %result
+}
+
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aobolensk wrote:

Added SALU tests and they regress as you said, leaving the combine here for now.

https://github.com/llvm/llvm-project/pull/215500