[llvm] [AMDGPU][GlobalISel] Narrow 64-bit shifts when KnownBits proves the amount is >= 32 (PR #215500)

[Matt Arsenault via llvm-commits]

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@@ -572,3 +573,57 @@ bool AMDGPUCombinerHelper::matchConstantIs32BitMask(Register Reg) const {
   // Check if low 32 bits or high 32 bits are all ones.
   return MaskLen >= 32 && ((MaskIdx == 0) || (MaskIdx == 64 - MaskLen));
 }
+
+// 64-bit shift is quarter rate on some subtargets, so splitting into a move
+// plus 32-bit shift is a win. Constant amounts are handled by the generic
+// matchCombineShiftToUnmerge combine already.
+bool AMDGPUCombinerHelper::matchShiftKnownGeHalfWidth(
+    MachineInstr &MI, BuildFnTy &MatchInfo) const {
+  unsigned Opc = MI.getOpcode();
+  assert(Opc == TargetOpcode::G_SHL || Opc == TargetOpcode::G_LSHR ||
+         Opc == TargetOpcode::G_ASHR);
+
+  Register Dst = MI.getOperand(0).getReg();
+  if (MRI.getType(Dst) != LLT::scalar(64))
+    return false;
+
+  Register ShiftAmt = MI.getOperand(2).getReg();
+  if (getIConstantVRegValWithLookThrough(ShiftAmt, MRI))
+    return false;
+
+  if (VT->getKnownBits(ShiftAmt).getMinValue().getZExtValue() < 32)
+    return false;
+
+  Register Src = MI.getOperand(1).getReg();
+  MatchInfo = [=, &MI](MachineIRBuilder &B) {
+    const LLT S32 = LLT::integer(32);
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arsenm wrote:

S32 doesn't match the type 

https://github.com/llvm/llvm-project/pull/215500