[llvm] [WIP][AMDGPU] Support the RF inline asm constraint (PR #195123)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,510 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+
+; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s
+
+define void @flat_load_RF(ptr %in) {
+; VI-LABEL: flat_load_RF:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    flat_load_dword v1, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr, ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_RF_as1(ptr %in) {
+; VI-LABEL: flat_load_RF_as1:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    flat_load_dword v1, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(1), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(1) elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_RF_as2(ptr %in) {
+; VI-LABEL: flat_load_RF_as2:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v0
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(2), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(2) elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_RF_as3(ptr %in) {
+; VI-LABEL: flat_load_RF_as3:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v0
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(3), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(3) elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_RF_as4(ptr %in) {
+; VI-LABEL: flat_load_RF_as4:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    flat_load_dword v1, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(4), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(4) elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_RF_as5(ptr %in) {
+; VI-LABEL: flat_load_RF_as5:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v0
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(5), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(5) elementtype(i32) %addr)
+  ret void
+}
+
+
+define void @flat_load_m_constraint(ptr %in) {
+; VI-LABEL: flat_load_m_constraint:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    flat_load_dword v1, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr, ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*m"(ptr elementtype(i32) %addr)
+  ret void
+}
+
+define void @flat_load_m_constraint_as1(ptr %in) {
+; VI-LABEL: flat_load_m_constraint_as1:
+; VI:       ; %bb.0: ; %entry
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v0
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    flat_load_dword v1, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    ;;#ASMSTART
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    ;;#ASMEND
+; VI-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %addr = load ptr addrspace(1), ptr %in
+  %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*m"(ptr addrspace(1) elementtype(i32) %addr)
+  ret void
+}
+
----------------
arsenm wrote:

Missing a test where the source value is inreg / SGPR 

https://github.com/llvm/llvm-project/pull/195123