[llvm] [WIP][AMDGPU] Support the RF inline asm constraint (PR #195123)

[Matt Arsenault via llvm-commits]

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@@ -4809,6 +4809,39 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
   } while (IsModified);
 }
 
+bool AMDGPUDAGToDAGISel::SelectInlineAsmMemoryOperand(
+    const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
+    std::vector<SDValue> &OutOps) {
+  switch (ConstraintID) {
+  case InlineAsm::ConstraintCode::m:
+    OutOps.push_back(Op);
+    return false;
+  case InlineAsm::ConstraintCode::RF: {
+    // flat_load/flat_store require the address in a VGPR. If the operand is
+    // non-divergent it will be SGPR-allocated, so copy it to the right VGPR
+    // class before handing it to the inline asm.
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arsenm wrote:

This is still not a divergence property. This should be unconditionally forced to VGPR without a comment 

https://github.com/llvm/llvm-project/pull/195123