[llvm] [RegAlloc][X86] Rematerialization of instructions with physical register (PR #198853)

[Matt Arsenault via llvm-commits]

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@@ -146,17 +146,43 @@ bool VirtRegAuxInfo::isRematerializable(const LiveInterval &LI,
   return true;
 }
 
-bool VirtRegAuxInfo::allUsesAvailableAt(const MachineInstr *MI,
+bool VirtRegAuxInfo::allUsesAvailableAt(const MachineInstr *OrigMI,
                                         SlotIndex UseIdx,
                                         const LiveIntervals &LIS,
                                         const MachineRegisterInfo &MRI,
                                         const TargetInstrInfo &TII) {
-  SlotIndex OrigIdx = LIS.getInstructionIndex(*MI).getRegSlot(true);
+  SlotIndex OrigIdx = LIS.getInstructionIndex(*OrigMI).getRegSlot(true);
+  auto MBB = LIS.getMBBFromIndex(UseIdx);
+  MachineInstr *UseMI = LIS.getInstructionFromIndex(UseIdx);
+  MachineBasicBlock::iterator UseIt = UseMI;
+  if (!UseMI) {
+    if (MBB->empty() ||
+        UseIdx < LIS.getInstructionIndex(*MBB->begin()).getBaseIndex())
+      UseIt = MBB->begin();
+    else {
+      UseIt = MBB->end();
+    }
+  }
   UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
-  for (const MachineOperand &MO : MI->operands()) {
-    if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
+
+  for (const MachineOperand &MO : OrigMI->operands()) {
+    if (!MO.isReg() || !MO.getReg())
       continue;
 
+    if (!MO.readsReg()) {
+      if (MO.getReg().isVirtual())
+        continue;
+      // A physical register is defined here, and we allow rematerialization of
+      // an instruction with physical register definition, it must be dead at
+      // this position.
+      const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
+      if (MBB->computeRegisterLiveness(TRI, MO.getReg(), UseIt) ==
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arsenm wrote:

You shouldn't be using computeRegisterLiveness in RA code, you have the full LiveIntervals available 

https://github.com/llvm/llvm-project/pull/198853