[llvm] [Xtensa] Implement esp32s3 target. (PR #220393)
Andrei Safronov via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 12 18:02:17 PDT 2026
https://github.com/andreisfr updated https://github.com/llvm/llvm-project/pull/220393
>From 774f2abc27a2d44425daf60d3f202bec40285d90 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Wed, 2 Sep 2026 00:14:03 +0300
Subject: [PATCH 1/2] [Xtensa] Implement esp32s3 target.
- Add esp32s3 CPU support
- Implement esp32s3 DSP operations with test
- Improve asm register parsing
---
.../llvm/TargetParser/XtensaTargetParser.def | 7 +
.../llvm/TargetParser/XtensaTargetParser.h | 3 +-
.../Xtensa/AsmParser/XtensaAsmParser.cpp | 101 +-
.../Disassembler/XtensaDisassembler.cpp | 200 +-
.../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 129 +
.../Xtensa/MCTargetDesc/XtensaInstPrinter.h | 18 +
.../MCTargetDesc/XtensaMCCodeEmitter.cpp | 184 +-
.../MCTargetDesc/XtensaMCTargetDesc.cpp | 57 +
llvm/lib/Target/Xtensa/Xtensa.td | 1 +
llvm/lib/Target/Xtensa/XtensaFeatures.td | 5 +
llvm/lib/Target/Xtensa/XtensaInstrFormats.td | 13 +
llvm/lib/Target/Xtensa/XtensaInstrInfo.td | 36 +
llvm/lib/Target/Xtensa/XtensaOperands.td | 83 +
llvm/lib/Target/Xtensa/XtensaProcessors.td | 6 +
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 9 +
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td | 46 +-
.../lib/Target/Xtensa/XtensaS3DSPInstrInfo.td | 5753 +++++++++++++++++
llvm/lib/Target/Xtensa/XtensaSubtarget.h | 1 +
llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s | 1030 +++
19 files changed, 7671 insertions(+), 11 deletions(-)
create mode 100644 llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
create mode 100755 llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s
diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.def b/llvm/include/llvm/TargetParser/XtensaTargetParser.def
index 65a2fbacd1028..eaf71c4aa64b3 100644
--- a/llvm/include/llvm/TargetParser/XtensaTargetParser.def
+++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.def
@@ -51,6 +51,7 @@ XTENSA_FEATURE(XF_PRID, "prid")
XTENSA_FEATURE(XF_REGPROTECT, "regprotect")
XTENSA_FEATURE(XF_MISCSR, "miscsr")
XTENSA_FEATURE(XF_ESP32S2OPS, "esp32s2ops")
+XTENSA_FEATURE(XF_ESP32S3OPS, "esp32s3ops")
#undef XTENSA_FEATURE
@@ -75,6 +76,12 @@ XTENSA_CPU(ESP32S2, {"esp32s2"},
XF_THREADPTR | XF_DIV32 | XF_DATACACHE | XF_DEBUG | XF_EXCEPTION | XF_HIGHPRIINTERRUPTS |
XF_HIGHPRIINTERRUPTSLEVEL7 | XF_COPROCESSOR | XF_INTERRUPT | XF_RVECTOR | XF_TIMERS3 | XF_PRID |
XF_REGPROTECT | XF_MISCSR | XF_MINMAX | XF_CLAMPS | XF_ESP32S2OPS))
+XTENSA_CPU(ESP32S3, {"esp32s3"},
+ (XF_DENSITY | XF_FP | XF_LOOP | XF_MAC16 | XF_WINDOWED | XF_BOOLEAN | XF_SEXT |
+ XF_NSA | XF_MUL16 | XF_MUL32 | XF_MUL32HIGH | XF_S32C1I | XF_THREADPTR | XF_DIV32 |
+ XF_DATACACHE | XF_DEBUG | XF_EXCEPTION | XF_HIGHPRIINTERRUPTS | XF_HIGHPRIINTERRUPTSLEVEL7 |
+ XF_COPROCESSOR | XF_INTERRUPT | XF_RVECTOR | XF_TIMERS3 | XF_PRID | XF_REGPROTECT | XF_MISCSR |
+ XF_MINMAX | XF_CLAMPS | XF_ESP32S3OPS))
#undef XTENSA_CPU
diff --git a/llvm/include/llvm/TargetParser/XtensaTargetParser.h b/llvm/include/llvm/TargetParser/XtensaTargetParser.h
index 58ae6f4c63af9..be63dc0a74eaa 100644
--- a/llvm/include/llvm/TargetParser/XtensaTargetParser.h
+++ b/llvm/include/llvm/TargetParser/XtensaTargetParser.h
@@ -65,7 +65,8 @@ enum XtensaFeatureKind : uint64_t {
XF_PRID = 1ULL << 34,
XF_REGPROTECT = 1ULL << 35,
XF_MISCSR = 1ULL << 36,
- XF_ESP32S2OPS = 1ULL << 37
+ XF_ESP32S2OPS = 1ULL << 37,
+ XF_ESP32S3OPS = 1ULL << 38
};
LLVM_ABI CPUKind parseCPUKind(StringRef CPU);
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index 1a624fda48a8a..8bc9e39ed3072 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -65,6 +65,7 @@ class XtensaAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "XtensaGenAsmMatcher.inc"
+ MCRegister getRegisterByName(StringRef RegName);
ParseStatus parseImmediate(OperandVector &Operands);
ParseStatus
parseRegister(OperandVector &Operands, bool AllowParens = false,
@@ -284,8 +285,48 @@ struct XtensaOperand : public MCParsedAsmOperand {
bool isimm7_22() const { return isImm(7, 22); }
+ bool isSelect_2() const { return isImm(0, 1); }
+
+ bool isSelect_4() const { return isImm(0, 3); }
+
+ bool isSelect_8() const { return isImm(0, 7); }
+
+ bool isSelect_16() const { return isImm(0, 16); }
+
bool isSelect_256() const { return isImm(0, 255); }
+ bool isOffset_16_16() const {
+ return isImm(-128, 112) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
+ }
+
+ bool isOffset_256_8() const {
+ return isImm(-1024, 1016) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0x7) == 0);
+ }
+
+ bool isOffset_256_16() const {
+ return isImm(-2048, 2032) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
+ }
+
+ bool isOffset_256_4() const {
+ return isImm(-512, 508) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
+ }
+
+ bool isOffset_128_2() const {
+ return isImm(0, 254) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0x1) == 0);
+ }
+
+ bool isOffset_128_1() const { return isImm(0, 127); }
+
+ bool isOffset_64_16() const {
+ return isImm(-512, 496) &&
+ ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -548,9 +589,48 @@ bool XtensaAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_Invalidimm7_22:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [7, 22]");
+ case Match_InvalidSelect_2:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 1]");
+ case Match_InvalidSelect_4:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 3]");
+ case Match_InvalidSelect_8:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 7]");
+ case Match_InvalidSelect_16:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 15]");
case Match_InvalidSelect_256:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [0, 255]");
+ case Match_InvalidOffset_16_16:
+ return Error(
+ RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-128, 112], first 4 bits should be zero");
+ case Match_InvalidOffset_256_8:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-1024, 1016], first 3 bits "
+ "should be zero");
+ case Match_InvalidOffset_256_16:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-2048, 2032], first 4 bits "
+ "should be zero");
+ case Match_InvalidOffset_256_4:
+ return Error(
+ RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-512, 508], first 2 bits should be zero");
+ case Match_InvalidOffset_128_2:
+ return Error(
+ RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 254], first bit should be zero");
+ case Match_InvalidOffset_128_1:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 127]");
+ case Match_InvalidOffset_64_16:
+ return Error(
+ RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-512, 496], first 4 bits should be zero");
}
report_fatal_error("Unknown match type detected!");
@@ -577,6 +657,18 @@ ParseStatus XtensaAsmParser::parsePCRelTarget(OperandVector &Operands) {
return ParseStatus::Success;
}
+MCRegister XtensaAsmParser::getRegisterByName(StringRef RegName) {
+ MCRegister RegNo = MatchRegisterName(RegName);
+ if (RegNo == 0)
+ RegNo = MatchRegisterAltName(RegName);
+
+ if (RegNo == Xtensa::GPIO_OUT_S2 &&
+ getSTI().getFeatureBits()[Xtensa::FeatureESP32S3Ops])
+ RegNo = Xtensa::GPIO_OUT_S3;
+
+ return RegNo;
+}
+
bool XtensaAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
SMLoc &EndLoc) {
const AsmToken &Tok = getParser().getTok();
@@ -635,9 +727,7 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands,
break;
case AsmToken::Identifier:
RegName = getLexer().getTok().getIdentifier();
- RegNo = MatchRegisterName(RegName);
- if (RegNo == 0)
- RegNo = MatchRegisterAltName(RegName);
+ RegNo = getRegisterByName(RegName);
break;
}
@@ -746,10 +836,7 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info,
Operands.push_back(XtensaOperand::createToken(Name.take_front(3), NameLoc));
StringRef RegName = Name.drop_front(4);
- unsigned RegNo = MatchRegisterName(RegName);
-
- if (RegNo == 0)
- RegNo = MatchRegisterAltName(RegName);
+ MCRegister RegNo = getRegisterByName(RegName);
if (!Xtensa::checkRegister(RegNo, getSTI().getFeatureBits(), RAType))
return Error(NameLoc, "invalid register name");
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 807a2d6d35fdc..4bc34fff4f00b 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -42,6 +42,10 @@ class XtensaDisassembler : public MCDisassembler {
bool hasDensity() const { return STI.hasFeature(Xtensa::FeatureDensity); }
+ bool hasESP32S3Ops() const {
+ return STI.getFeatureBits()[Xtensa::FeatureESP32S3Ops];
+ }
+
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const override;
@@ -108,6 +112,21 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}
+static const unsigned QRDecoderTable[] = {Xtensa::Q0, Xtensa::Q1, Xtensa::Q2,
+ Xtensa::Q3, Xtensa::Q4, Xtensa::Q5,
+ Xtensa::Q6, Xtensa::Q7};
+
+static DecodeStatus DecodeQRRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= std::size(QRDecoderTable))
+ return MCDisassembler::Fail;
+
+ unsigned Reg = QRDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
@@ -415,6 +434,38 @@ static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeSelect_2Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeSelect_4Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeSelect_8Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeSelect_16Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm,
int64_t Address,
const void *Decoder) {
@@ -423,6 +474,80 @@ static DecodeStatus decodeSelect_256Operand(MCInst &Inst, uint64_t Imm,
return MCDisassembler::Success;
}
+static DecodeStatus decodeOffset_16_16Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isInt<8>(Imm) && "Invalid immediate");
+ if ((Imm & 0xf) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 4));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_256_8Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isInt<16>(Imm) && "Invalid immediate");
+ if ((Imm & 0x7) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 3));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isInt<16>(Imm) && "Invalid immediate");
+ if ((Imm & 0xf) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 4));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isInt<16>(Imm) && "Invalid immediate");
+ if ((Imm & 0x2) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 2));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_128_2Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ if ((Imm & 0x1) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 1));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_128_1Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeOffset_64_16Operand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isInt<16>(Imm) && "Invalid immediate");
+ if ((Imm & 0xf) != 0)
+ Inst.addOperand(MCOperand::createImm(Imm << 4));
+ else
+ Inst.addOperand(MCOperand::createImm(Imm));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) {
assert(isUInt<12>(Imm) && "Invalid immediate");
@@ -478,7 +603,7 @@ static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
/// Read three bytes from the ArrayRef and return 24 bit data
static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint64_t &Insn,
- bool IsLittleEndian) {
+ bool IsLittleEndian, bool CheckTIE = false) {
// We want to read exactly 3 Bytes of data.
if (Bytes.size() < 3) {
Size = 0;
@@ -488,12 +613,58 @@ static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
if (!IsLittleEndian) {
report_fatal_error("Big-endian mode currently is not supported!");
} else {
+ if (CheckTIE && (Bytes[0] & 0x8) != 0)
+ return MCDisassembler::Fail;
Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
}
return MCDisassembler::Success;
}
+/// Read three bytes from the ArrayRef and return 32 bit data
+static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
+ uint64_t &Size, uint64_t &Insn,
+ bool IsLittleEndian) {
+ // We want to read exactly 4 Bytes of data.
+ if (Bytes.size() < 4) {
+ Size = 0;
+ return MCDisassembler::Fail;
+ }
+
+ if (!IsLittleEndian) {
+ report_fatal_error("Big-endian mode currently is not supported!");
+ } else {
+ if ((Bytes[0] & 0x8) == 0)
+ return MCDisassembler::Fail;
+ Insn = (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
+ }
+
+ return MCDisassembler::Success;
+}
+
+/// Read InstSize bytes from the ArrayRef and return 24 bit data
+static DecodeStatus readInstructionN(ArrayRef<uint8_t> Bytes, uint64_t Address,
+ unsigned InstSize,
+ uint64_t &Size, uint64_t &Insn,
+ bool IsLittleEndian) {
+ // We want to read exactly 3 Bytes of data.
+ if (Bytes.size() < InstSize) {
+ Size = 0;
+ return MCDisassembler::Fail;
+ }
+
+ if (!IsLittleEndian) {
+ report_fatal_error("Big-endian mode currently is not supported!");
+ } else {
+ Insn = 0;
+ for (unsigned i = 0; i < InstSize; i++)
+ Insn |= (Bytes[i] << 8*i);
+ }
+
+ Size = InstSize;
+ return MCDisassembler::Success;
+}
+
#include "XtensaGenDisassemblerTables.inc"
DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
@@ -526,5 +697,32 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Size = 3;
return Result;
}
+
+ if (hasESP32S3Ops()) {
+ // Parse ESP32S3 24-bit instructions
+ Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian, true);
+ if (Result != MCDisassembler::Fail) {
+ LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (24-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableESP32S324, MI, Insn, Address, this,
+ STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 3;
+ return Result;
+ }
+ }
+
+ // Parse ESP32S3 32-bit instructions
+ Result = readInstruction32(Bytes, Address, Size, Insn, IsLittleEndian);
+ if (Result == MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+ LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (32-bit opcodes):\n");
+ Result = decodeInstruction(DecoderTableESP32S332, MI, Insn,
+ Address, this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ }
+
return Result;
}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
index 42971c79cf8bf..4ccfb614e068f 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -440,6 +440,50 @@ void XtensaInstPrinter::printImm7_22_AsmOperand(const MCInst *MI, int OpNum,
printOperand(MI, OpNum, O);
}
+void XtensaInstPrinter::printSelect_2_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 1) &&
+ "Invalid argument, value must be in range [0,1]");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printSelect_4_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 3) &&
+ "Invalid argument, value must be in range [0,3]");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printSelect_8_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 7) &&
+ "Invalid argument, value must be in range [0,7]");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printSelect_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 15) &&
+ "Invalid argument, value must be in range [0,15]");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum,
raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
@@ -450,3 +494,88 @@ void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum,
} else
printOperand(MI, OpNum, O);
}
+
+void XtensaInstPrinter::printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -128 && Value <= 112 && (Value & 0xf) == 0) &&
+ "Invalid argument, value must be in range [-128,112], first 4 bits "
+ "should be zero");
+ O << Value;
+ } else{
+ printOperand(MI, OpNum, O);
+ }
+}
+
+void XtensaInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -1024 && Value <= 1016 && (Value & 0x7) == 0) &&
+ "Invalid argument, value must be in range [-1024,1016], first 3 "
+ "bits should be zero");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -2048 && Value <= 2032 && (Value & 0xf) == 0) &&
+ "Invalid argument, value must be in range [-2048,2032], first 4 "
+ "bits should be zero");
+ O << Value;
+ } else{
+ printOperand(MI, OpNum, O);
+ }
+}
+
+void XtensaInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -512 && Value <= 508 && (Value & 0x3) == 0) &&
+ "Invalid argument, value must be in range [-512,508], first 2 bits "
+ "should be zero");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 254 && (Value & 0x1) == 0) &&
+ "Invalid argument, value must be in range [0,254], first bit should "
+ "be zero");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= 0 && Value <= 127) &&
+ "Invalid argument, value must be in range [0,127]");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
+
+void XtensaInstPrinter::printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O) {
+ if (MI->getOperand(OpNum).isImm()) {
+ int64_t Value = MI->getOperand(OpNum).getImm();
+ assert((Value >= -512 && Value <= 496 && (Value & 0xf) == 0) &&
+ "Invalid argument, value must be in range [-512,496], first 4 bits "
+ "should be zero");
+ O << Value;
+ } else
+ printOperand(MI, OpNum, O);
+}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
index 657996dd607e6..66c5fbd7cf06a 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
@@ -77,7 +77,25 @@ class XtensaInstPrinter : public MCInstPrinter {
void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printImm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printSelect_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
void printSelect_256_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+ void printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
+ void printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum,
+ raw_ostream &O);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
index 349a747d3d51f..e2cd186bffc06 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
@@ -143,9 +143,53 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint8_t getSelect_4OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint8_t getSelect_8OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint8_t getSelect_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
uint8_t getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+
+ int8_t getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ int16_t getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint8_t getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ uint8_t getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
+
+ int16_t getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
};
} // namespace
@@ -611,6 +655,54 @@ XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
return res;
}
+uint8_t
+XtensaMCCodeEmitter::getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 1)) && "Unexpected operand value!");
+
+ return Res;
+}
+
+uint8_t
+XtensaMCCodeEmitter::getSelect_4OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 3)) && "Unexpected operand value!");
+
+ return Res;
+}
+
+uint8_t
+XtensaMCCodeEmitter::getSelect_8OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 7)) && "Unexpected operand value!");
+
+ return Res;
+}
+
+uint8_t
+XtensaMCCodeEmitter::getSelect_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 15)) && "Unexpected operand value!");
+
+ return Res;
+}
+
uint8_t
XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
@@ -618,8 +710,98 @@ XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
uint8_t Res = static_cast<uint8_t>(MO.getImm());
- assert(isUInt<8>(Res) && "Unexpected operand value!");
+ assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!");
return Res;
}
#include "XtensaGenMCCodeEmitter.inc"
+
+int8_t
+XtensaMCCodeEmitter::getOffset_16_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int8_t Res = static_cast<int8_t>(MO.getImm());
+
+ assert(((Res >= -128) && (Res <= 112) && ((Res & 0xf) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 16;
+}
+
+int16_t
+XtensaMCCodeEmitter::getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int16_t Res = static_cast<int16_t>(MO.getImm());
+
+ assert(((Res >= -1024) && (Res <= 1016) && ((Res & 0x7) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 8;
+}
+
+int16_t
+XtensaMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int16_t Res = static_cast<int16_t>(MO.getImm());
+
+ assert(((Res >= -2048) && (Res <= 2032) && ((Res & 0xf) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 16;
+}
+
+int16_t
+XtensaMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int16_t Res = static_cast<int16_t>(MO.getImm());
+
+ assert(((Res >= -512) && (Res <= 508) && ((Res & 0x3) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 4;
+}
+
+uint8_t
+XtensaMCCodeEmitter::getOffset_128_2OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 254) && ((Res & 0x1) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 2;
+}
+
+uint8_t
+XtensaMCCodeEmitter::getOffset_128_1OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+ assert(((Res >= 0) && (Res <= 127)) && "Unexpected operand value!");
+
+ return Res;
+}
+
+int16_t
+XtensaMCCodeEmitter::getOffset_64_16OpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ const MCOperand &MO = MI.getOperand(OpNo);
+ int16_t Res = static_cast<int16_t>(MO.getImm());
+
+ assert(((Res >= -512) && (Res <= 496) && ((Res & 0xf) == 0)) &&
+ "Unexpected operand value!");
+
+ return Res / 16;
+}
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
index 397b56fb57b5a..11e98df39133f 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
@@ -206,6 +206,25 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
return FeatureBits[Xtensa::FeatureWindowed];
case Xtensa::GPIO_OUT_S2:
return FeatureBits[Xtensa::FeatureESP32S2Ops];
+ case Xtensa::ACCX_0:
+ case Xtensa::ACCX_1:
+ case Xtensa::QACC_H_0:
+ case Xtensa::QACC_H_1:
+ case Xtensa::QACC_H_2:
+ case Xtensa::QACC_H_3:
+ case Xtensa::QACC_H_4:
+ case Xtensa::QACC_L_0:
+ case Xtensa::QACC_L_1:
+ case Xtensa::QACC_L_2:
+ case Xtensa::QACC_L_3:
+ case Xtensa::QACC_L_4:
+ case Xtensa::GPIO_OUT_S3:
+ case Xtensa::FFT_BIT_WIDTH:
+ case Xtensa::UA_STATE_0:
+ case Xtensa::UA_STATE_1:
+ case Xtensa::UA_STATE_2:
+ case Xtensa::UA_STATE_3:
+ return FeatureBits[Xtensa::FeatureESP32S3Ops];
case Xtensa::NoRegister:
return false;
}
@@ -231,6 +250,44 @@ MCRegister Xtensa::getUserRegister(unsigned Code, const MCRegisterInfo &MRI) {
UserReg = Xtensa::THREADPTR;
} else if (MRI.getEncodingValue(Xtensa::GPIO_OUT_S2) == Code) {
UserReg = Xtensa::GPIO_OUT_S2;
+ } else if (MRI.getEncodingValue(Xtensa::GPIO_OUT_S3) == Code) {
+ UserReg = Xtensa::GPIO_OUT_S3;
+ } else if (MRI.getEncodingValue(Xtensa::ACCX_0) == Code) {
+ UserReg = Xtensa::ACCX_0;
+ } else if (MRI.getEncodingValue(Xtensa::ACCX_1) == Code) {
+ UserReg = Xtensa::ACCX_1;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_H_0) == Code) {
+ UserReg = Xtensa::QACC_H_0;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_H_1) == Code) {
+ UserReg = Xtensa::QACC_H_1;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_H_2) == Code) {
+ UserReg = Xtensa::QACC_H_2;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_H_3) == Code) {
+ UserReg = Xtensa::QACC_H_3;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_H_4) == Code) {
+ UserReg = Xtensa::QACC_H_4;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_L_0) == Code) {
+ UserReg = Xtensa::QACC_L_0;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_L_1) == Code) {
+ UserReg = Xtensa::QACC_L_1;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_L_2) == Code) {
+ UserReg = Xtensa::QACC_L_2;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_L_3) == Code) {
+ UserReg = Xtensa::QACC_L_3;
+ } else if (MRI.getEncodingValue(Xtensa::QACC_L_4) == Code) {
+ UserReg = Xtensa::QACC_L_4;
+ } else if (MRI.getEncodingValue(Xtensa::FFT_BIT_WIDTH) == Code) {
+ UserReg = Xtensa::FFT_BIT_WIDTH;
+ } else if (MRI.getEncodingValue(Xtensa::SAR_BYTE) == Code) {
+ UserReg = Xtensa::SAR_BYTE;
+ } else if (MRI.getEncodingValue(Xtensa::UA_STATE_0) == Code) {
+ UserReg = Xtensa::UA_STATE_0;
+ } else if (MRI.getEncodingValue(Xtensa::UA_STATE_1) == Code) {
+ UserReg = Xtensa::UA_STATE_1;
+ } else if (MRI.getEncodingValue(Xtensa::UA_STATE_2) == Code) {
+ UserReg = Xtensa::UA_STATE_2;
+ } else if (MRI.getEncodingValue(Xtensa::UA_STATE_3) == Code) {
+ UserReg = Xtensa::UA_STATE_3;
}
return UserReg;
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index eecf42f46f88b..2fd5f4a197b8b 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -54,6 +54,7 @@ def XtensaInstrInfo : InstrInfo;
def XtensaAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = 1;
+ let AllowDuplicateRegisterNames = 1;
}
def XtensaInstPrinter : AsmWriter {
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
index 5b0732bf78ad3..b95b1a9909bcb 100644
--- a/llvm/lib/Target/Xtensa/XtensaFeatures.td
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -168,3 +168,8 @@ def FeatureESP32S2Ops : SubtargetFeature<"esp32s2ops", "HasESP32S2Ops", "true",
"Support Xtensa esp32-s2 ISA extension">;
def HasESP32S2Ops : Predicate<"Subtarget->hasESP32S2Ops()">,
AssemblerPredicate<(all_of FeatureESP32S2Ops)>;
+
+def FeatureESP32S3Ops : SubtargetFeature<"esp32s3ops", "HasESP32S3Ops", "true",
+ "Support Xtensa esp32-s3 ISA extension">;
+def HasESP32S3Ops : Predicate<"Subtarget->hasESP32S3Ops()">,
+ AssemblerPredicate<(all_of FeatureESP32S3Ops)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
index bd082c1def88d..e4608cd34ed32 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
@@ -208,6 +208,19 @@ class RI6_Inst<bits<4> op0, bits<1> i, bits<1> z, dag outs, dag ins,
let Inst{3-0} = op0;
}
+class EE_Inst24<dag outs, dag ins, string asmstr, list<dag> pattern,
+ InstrItinClass itin = NoItinerary>
+ : XtensaInst24<outs, ins, asmstr, pattern, itin> {
+ let DecoderNamespace = "ESP32S3";
+}
+
+class EE_Inst32<dag outs, dag ins, string asmstr, list<dag> pattern,
+ InstrItinClass itin = NoItinerary>
+ : XtensaInst<4, outs, ins, asmstr, pattern, itin> {
+ field bits<32> Inst;
+ let DecoderNamespace = "ESP32S3";
+}
+
// Pseudo instructions
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: XtensaInst<2, outs, ins, asmstr, pattern> {
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index b55a6ea8c932c..bd0034ed00f07 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1594,6 +1594,42 @@ let Predicates = [HasESP32S2Ops] in {
}
}
+//===----------------------------------------------------------------------===//
+// Xtensa ESP32S3 Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasESP32S3Ops] in {
+ def EE_WR_MASK_GPIO_OUT : RRR_Inst<0x04, 0x02, 0x07, (outs), (ins AR:$t, AR:$s),
+ "ee.wr_mask_gpio_out\t$t, $s", []> {
+ let r = 0x4;
+ }
+
+ def EE_SET_BIT_GPIO_OUT : RRR_Inst<0x04, 0x05, 0x07, (outs), (ins select_256:$imm),
+ "ee.set_bit_gpio_out\t$imm", []> {
+ bits<8> imm;
+
+ let r = 0x4;
+ let s = imm{7-4};
+ let t = imm{3-0};
+ }
+
+ def EE_CLR_BIT_GPIO_OUT : RRR_Inst<0x04, 0x06, 0x07, (outs), (ins select_256:$imm),
+ "ee.clr_bit_gpio_out\t$imm", []> {
+ bits<8> imm;
+
+ let r = 0x4;
+ let s = imm{7-4};
+ let t = imm{3-0};
+ }
+
+ def EE_GET_GPIO_IN : RRR_Inst<0x04, 0x05, 0x06, (outs AR:$t), (ins),
+ "ee.get_gpio_in\t$t", []> {
+ let r = 0x0;
+ let s = 0x8;
+ }
+}
+include "XtensaS3DSPInstrInfo.td"
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td
index 76629f107d4b5..4356bb3d72564 100644
--- a/llvm/lib/Target/Xtensa/XtensaOperands.td
+++ b/llvm/lib/Target/Xtensa/XtensaOperands.td
@@ -182,6 +182,89 @@ def select_256: Immediate<i32, [{ return Imm >= 0 && Imm <= 255; }], "Select_256
let DecoderMethod = "decodeSelect_256Operand";
}
+// select_2 predicate - Immediate in the range [0,1]
+def Select_2_AsmOperand: ImmAsmOperand<"Select_2">;
+def select_2: Immediate<i32, [{ return Imm >= 0 && Imm <= 1; }], "Select_2_AsmOperand"> {
+ let EncoderMethod = "getSelect_2OpValue";
+ let DecoderMethod = "decodeSelect_2Operand";
+}
+
+// select_4 predicate - Immediate in the range [0,3]
+def Select_4_AsmOperand: ImmAsmOperand<"Select_4">;
+def select_4: Immediate<i32, [{ return Imm >= 0 && Imm <= 3; }], "Select_4_AsmOperand"> {
+ let EncoderMethod = "getSelect_4OpValue";
+ let DecoderMethod = "decodeSelect_4Operand";
+}
+
+// select_8 predicate - Immediate in the range [0,7]
+def Select_8_AsmOperand: ImmAsmOperand<"Select_8">;
+def select_8: Immediate<i32, [{ return Imm >= 0 && Imm <= 7; }], "Select_8_AsmOperand"> {
+ let EncoderMethod = "getSelect_8OpValue";
+ let DecoderMethod = "decodeSelect_8Operand";
+}
+
+// select_16 predicate - Immediate in the range [0,15]
+def Select_16_AsmOperand: ImmAsmOperand<"Select_16">;
+def select_16: Immediate<i32, [{ return Imm >= 0 && Imm <= 15; }], "Select_16_AsmOperand"> {
+ let EncoderMethod = "getSelect_16OpValue";
+ let DecoderMethod = "decodeSelect_16Operand";
+}
+/// --------------------------- ///
+// offset_16_16 predicate - 4-bit signed immediate in the range [-128,112] with an interval
+// of 16.
+def Offset_16_16_AsmOperand: ImmAsmOperand<"Offset_16_16">;
+def offset_16_16: Immediate<i32, [{ return (Imm >= -128 && Imm <= 112) && (Imm & 0xf == 0); }], "Offset_16_16_AsmOperand"> {
+ let EncoderMethod = "getOffset_16_16OpValue";
+ let DecoderMethod = "decodeOffset_16_16Operand";
+}
+
+// offset_256_8 predicate - 4-bit signed immediate in the range [-1024,1016] with an interval
+// of 8.
+def Offset_256_8_AsmOperand: ImmAsmOperand<"Offset_256_8">;
+def offset_256_8: Immediate<i32, [{ return (Imm >= -1024 && Imm <= 1016) && (Imm & 0x7 == 0); }], "Offset_256_8_AsmOperand"> {
+ let EncoderMethod = "getOffset_256_8OpValue";
+ let DecoderMethod = "decodeOffset_256_8Operand";
+}
+
+// offset_256_16 predicate - 8-bit signed immediate in the range [-2048,2032] with an interval
+// of 16.
+def Offset_256_16_AsmOperand: ImmAsmOperand<"Offset_256_16">;
+def offset_256_16: Immediate<i32, [{ return (Imm >= -2048 && Imm <= 2032) && (Imm & 0xf == 0); }], "Offset_256_16_AsmOperand"> {
+ let EncoderMethod = "getOffset_256_16OpValue";
+ let DecoderMethod = "decodeOffset_256_16Operand";
+}
+
+// offset_256_4 predicate - 4-bit signed immediate in the range [-512,508] with an interval
+// of 4.
+def Offset_256_4_AsmOperand: ImmAsmOperand<"Offset_256_4">;
+def offset_256_4: Immediate<i32, [{ return (Imm >= -512 && Imm <= 508) && (Imm & 0x3 == 0); }], "Offset_256_4_AsmOperand"> {
+ let EncoderMethod = "getOffset_256_4OpValue";
+ let DecoderMethod = "decodeOffset_256_4Operand";
+}
+
+// offset_128_2 predicate - 4-bit signed immediate in the range [0,254] with an interval
+// of 2.
+def Offset_128_2_AsmOperand: ImmAsmOperand<"Offset_128_2">;
+def offset_128_2: Immediate<i32, [{ return (Imm >= 0 && Imm <= 254) && (Imm & 0x1 == 0); }], "Offset_128_2_AsmOperand"> {
+ let EncoderMethod = "getOffset_128_2OpValue";
+ let DecoderMethod = "decodeOffset_128_2Operand";
+}
+
+// offset_128_1 predicate - 4-bit signed immediate in the range [0,127]
+def Offset_128_1_AsmOperand: ImmAsmOperand<"Offset_128_1">;
+def offset_128_1: Immediate<i32, [{ return Imm >= 0 && Imm <= 127; }], "Offset_128_1_AsmOperand"> {
+ let EncoderMethod = "getOffset_128_1OpValue";
+ let DecoderMethod = "decodeOffset_128_1Operand";
+}
+
+// offset_64_16 predicate - 4-bit signed immediate in the range [-512,496] with an interval
+// of 16.
+def Offset_64_16_AsmOperand: ImmAsmOperand<"Offset_64_16">;
+def offset_64_16: Immediate<i32, [{ return (Imm >= -512 && Imm <= 496) && (Imm & 0xf == 0); }], "Offset_64_16_AsmOperand"> {
+ let EncoderMethod = "getOffset_64_16OpValue";
+ let DecoderMethod = "decodeOffset_64_16Operand";
+}
+
//===----------------------------------------------------------------------===//
// Memory address operands
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaProcessors.td b/llvm/lib/Target/Xtensa/XtensaProcessors.td
index b977de596762c..7a2a1869817d6 100644
--- a/llvm/lib/Target/Xtensa/XtensaProcessors.td
+++ b/llvm/lib/Target/Xtensa/XtensaProcessors.td
@@ -30,3 +30,9 @@ def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA,
FeatureDiv32, FeatureDataCache, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel7,
FeatureCoprocessor, FeatureInterrupt, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, FeatureRegionProtection,
FeatureMiscSR, FeatureMINMAX, FeatureCLAMPS, FeatureESP32S2Ops]>;
+
+def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT,
+ FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
+ FeatureDataCache, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureHighPriInterruptsLevel7, FeatureCoprocessor,
+ FeatureInterrupt, FeatureRelocatableVector, FeatureTimers3, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
+ FeatureMINMAX, FeatureCLAMPS, FeatureESP32S3Ops]>;
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
index ed76431bf5495..619f231803c3e 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -59,6 +59,15 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
// Reserve stack pointer.
Reserved.set(Xtensa::SP);
+ //Reserve QR regs
+ Reserved.set(Xtensa::Q0);
+ Reserved.set(Xtensa::Q1);
+ Reserved.set(Xtensa::Q2);
+ Reserved.set(Xtensa::Q3);
+ Reserved.set(Xtensa::Q4);
+ Reserved.set(Xtensa::Q5);
+ Reserved.set(Xtensa::Q6);
+ Reserved.set(Xtensa::Q7);
return Reserved;
}
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
index 6c4f35e832f3f..d5427554d17f0 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
@@ -65,6 +65,23 @@ def AR : RegisterClass<"Xtensa", [i32], 32, (add
A8, A9, A10, A11, A12, A13, A14, A15,
A7, A6, A5, A4, A3, A2, A0, SP)>;
+// 128-bit general-purpose registers
+class QRReg<bits<16> num, string n, list<string>alt = []> : XtensaReg<n>{
+ let HWEncoding{15-0} = num;
+ let AltNames = alt;
+}
+
+def Q0 : QRReg<0, "q0">;
+def Q1 : QRReg<1, "q1">;
+def Q2 : QRReg<2, "q2">;
+def Q3 : QRReg<3, "q3">;
+def Q4 : QRReg<4, "q4">;
+def Q5 : QRReg<5, "q5">;
+def Q6 : QRReg<6, "q6">;
+def Q7 : QRReg<7, "q7">;
+
+def QR : RegisterClass<"Xtensa", [v16i8, v4i32], 128, (sequence "Q%u", 0, 7)>;
+
//===----------------------------------------------------------------------===//
// Special-purpose registers
//===----------------------------------------------------------------------===//
@@ -243,6 +260,32 @@ class URReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> {
// ESP32S2 registers
def GPIO_OUT_S2 : URReg<0, "gpio_out", ["GPIO_OUT"]>;
+// ESP32S3 registers
+def ACCX_0 : URReg<0, "accx_0", ["ACCX_0"]>;
+def ACCX_1 : URReg<1, "accx_1", ["ACCX_1"]>;
+def QACC_H_0 : URReg<2, "qacc_h_0", ["QACC_H_0"]>;
+def QACC_H_1 : URReg<3, "qacc_h_1", ["QACC_H_1"]>;
+def QACC_H_2 : URReg<4, "qacc_h_2", ["QACC_H_2"]>;
+def QACC_H_3 : URReg<5, "qacc_h_3", ["QACC_H_3"]>;
+def QACC_H_4 : URReg<6, "qacc_h_4", ["QACC_H_4"]>;
+def QACC_L_0 : URReg<7, "qacc_l_0", ["QACC_L_0"]>;
+def QACC_L_1 : URReg<8, "qacc_l_1", ["QACC_L_1"]>;
+def QACC_L_2 : URReg<9, "qacc_l_2", ["QACC_L_2"]>;
+def QACC_L_3 : URReg<10, "qacc_l_3", ["QACC_L_3"]>;
+def QACC_L_4 : URReg<11, "qacc_l_4", ["QACC_L_4"]>;
+def GPIO_OUT_S3 : URReg<12, "gpio_out", ["GPIO_OUT"]>;
+def SAR_BYTE : URReg<13, "sar_byte", ["SAR_BYTE"]>;
+def FFT_BIT_WIDTH : URReg<14, "fft_bit_width", ["FFT_BIT_WIDTH"]>;
+def UA_STATE_0 : URReg<15, "ua_state_0", ["UA_STATE_0"]>;
+def UA_STATE_1 : URReg<16, "ua_state_1", ["UA_STATE_1"]>;
+def UA_STATE_2 : URReg<17, "ua_state_2", ["UA_STATE_2"]>;
+def UA_STATE_3 : URReg<18, "ua_state_3", ["UA_STATE_3"]>;
+
+def ESP32S3R : RegisterClass<"Xtensa", [i32], 32, (add
+ ACCX_0, ACCX_1, QACC_H_0, QACC_H_1, QACC_H_2, QACC_H_3, QACC_H_4,
+ QACC_L_0, QACC_L_1, QACC_L_2, QACC_L_3, QACC_L_4, GPIO_OUT_S3, SAR_BYTE,
+ FFT_BIT_WIDTH, UA_STATE_0, UA_STATE_1, UA_STATE_2, UA_STATE_3)>;
+
// Thread Pointer register
def THREADPTR : URReg<231, "threadptr", ["THREADPTR"]>;
@@ -255,7 +298,8 @@ def F64R_HI : URReg<235, "f64r_hi", ["F64R_HI"]>;
def F64S : URReg<236, "f64s", ["F64S"]>;
def UR : RegisterClass<"Xtensa", [i32], 32, (add
- GPIO_OUT_S2, THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S)>;
+ GPIO_OUT_S2, THREADPTR, FCR, FSR, F64R_LO, F64R_HI, F64S,
+ ESP32S3R)>;
//===----------------------------------------------------------------------===//
// Floating-Point registers
diff --git a/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
new file mode 100644
index 0000000000000..a42b67684efa5
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
@@ -0,0 +1,5753 @@
+//===- XtensaS3DSPInstrInfo.td - Xtensa Target Description -*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Xtensa S3 DSP instructions in TableGen format.
+//
+// These definitions are generated
+// This file is generated
+// AI_S6_V2.h
+//
+//===----------------------------------------------------------------------===//
+
+// This file is generated
+
+
+def EE_ANDQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.andq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-12} = 0x3;
+ let Inst{11-10} = qy{2-1};
+ let Inst{9-8} = 0x0;
+ let Inst{7-6} = qx{2-1};
+ let Inst{5} = qy{0};
+ let Inst{4} = qx{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_BITREV: EE_Inst24<(outs QR:$qa, AR:$axr), (ins AR:$ax),
+ "ee.bitrev\t $qa, $ax", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<4> ax;
+
+
+ let Constraints = "$axr = $ax";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-8} = 0x7b;
+ let Inst{7-4} = ax{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_CMUL_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, select_4:$sel4),
+ "ee.cmul.s16\t $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<2> sel4;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-6} = 0x0;
+ let Inst{5-4} = sel4{1-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_CMUL_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy, select_4:$sel4),
+ "ee.cmul.s16.ld.incp\t $qu, $as, $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<2> sel4;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{9-8} = sel4{1-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_CMUL_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy, select_4:$sel4),
+ "ee.cmul.s16.st.incp\t $qv, $as, $qz, $qx, $qy, $sel4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<2> sel4;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 0;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{9-8} = sel4{1-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_AMS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2),
+ "ee.fft.ams.s16.ld.incp\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qz1;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qm;
+ bits<1> sel2;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25} = sel2{0};
+ let Inst{24} = qz1{2};
+ let Inst{23} = qz{0};
+ let Inst{22-20} = qy{2-0};
+ let Inst{19} = qz1{1};
+ let Inst{18-16} = qm{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qz{2-1};
+ let Inst{11} = qz1{0};
+ let Inst{10-8} = qu{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_AMS_S16_LD_INCP_UAUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2),
+ "ee.fft.ams.s16.ld.incp.uaup\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qz1;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qm;
+ bits<1> sel2;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = sel2{0};
+ let Inst{24} = qz1{2};
+ let Inst{23} = qz{0};
+ let Inst{22-20} = qy{2-0};
+ let Inst{19} = qz1{1};
+ let Inst{18-16} = qm{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qz{2-1};
+ let Inst{11} = qz1{0};
+ let Inst{10-8} = qu{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_AMS_S16_LD_R32_DECP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz, QR:$qz1), (ins AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2),
+ "ee.fft.ams.s16.ld.r32.decp\t $qu, $as, $qz, $qz1, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qz1;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qm;
+ bits<1> sel2;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = sel2{0};
+ let Inst{24} = qz1{2};
+ let Inst{23} = qz{0};
+ let Inst{22-20} = qy{2-0};
+ let Inst{19} = qz1{1};
+ let Inst{18-16} = qm{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qz{2-1};
+ let Inst{11} = qz1{0};
+ let Inst{10-8} = qu{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_AMS_S16_ST_INCP: EE_Inst32<(outs QR:$qz1, AR:$as0r, AR:$asr), (ins QR:$qv, AR:$as0, AR:$as, QR:$qx, QR:$qy, QR:$qm, select_2:$sel2),
+ "ee.fft.ams.s16.st.incp\t $qv, $qz1, $as0, $as, $qx, $qy, $qm, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<3> qz1;
+ bits<4> as0;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qm;
+ bits<1> sel2;
+
+ let mayStore = 1;
+
+ let Constraints = "$as0r = $as0, $asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = sel2{0};
+ let Inst{25-24} = qz1{2-1};
+ let Inst{23} = qm{0};
+ let Inst{22-20} = qv{2-0};
+ let Inst{19} = qz1{0};
+ let Inst{18-16} = qx{2-0};
+ let Inst{15-14} = qy{1-0};
+ let Inst{13-12} = qm{2-1};
+ let Inst{11-8} = as{3-0};
+ let Inst{7-4} = as0{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qy{2};
+}
+
+def EE_FFT_CMUL_S16_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, select_8:$sel8),
+ "ee.fft.cmul.s16.ld.xp\t $qu, $as, $ad, $qz, $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> sel8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 1;
+ let Inst{26} = 1;
+ let Inst{25-24} = sel8{2-1};
+ let Inst{23} = qu{0};
+ let Inst{22-20} = qy{2-0};
+ let Inst{19} = sel8{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qu{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_CMUL_S16_ST_XP: EE_Inst32<(outs AR:$asr), (ins QR:$qx, QR:$qy, QR:$qv, AR:$as, AR:$ad, select_8:$sel8, select_4:$upd4, select_4:$sar4),
+ "ee.fft.cmul.s16.st.xp\t $qx, $qy, $qv, $as, $ad, $sel8, $upd4, $sar4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qv;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> sel8;
+ bits<2> upd4;
+ bits<2> sar4;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26-25} = sar4{1-0};
+ let Inst{24} = upd4{1};
+ let Inst{23} = sel8{0};
+ let Inst{22-20} = qy{2-0};
+ let Inst{19} = upd4{0};
+ let Inst{18-16} = qv{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = sel8{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_R2BF_S16: EE_Inst24<(outs QR:$qa0, QR:$qa1), (ins QR:$qx, QR:$qy, select_2:$sel2),
+ "ee.fft.r2bf.s16\t $qa0, $qa1, $qx, $qy, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa0;
+ bits<3> qa1;
+ bits<3> qx;
+ bits<3> qy;
+ bits<1> sel2;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa0{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qa0{0};
+ let Inst{14-12} = qa1{2-0};
+ let Inst{11-10} = qy{2-1};
+ let Inst{9} = 0x0;
+ let Inst{8} = sel2{0};
+ let Inst{7-6} = qx{2-1};
+ let Inst{5} = qy{0};
+ let Inst{4} = qx{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_FFT_R2BF_S16_ST_INCP: EE_Inst32<(outs QR:$qa0, AR:$asr), (ins QR:$qx, QR:$qy, AR:$as, select_4:$sar4),
+ "ee.fft.r2bf.s16.st.incp\t $qa0, $qx, $qy, $as, $sar4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa0;
+ bits<3> qx;
+ bits<3> qy;
+ bits<4> as;
+ bits<2> sar4;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = sar4{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qy{2-0};
+ let Inst{18-16} = qa0{2-0};
+ let Inst{13} = 0;
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{12} = sar4{1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_FFT_VST_R32_DECP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, select_2:$sar2),
+ "ee.fft.vst.r32.decp\t $qv, $as, $sar2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<1> sar2;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qv{0};
+ let Inst{14-11} = 0x6;
+ let Inst{10} = sar2{0};
+ let Inst{9-8} = 0x3;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDF_128_IP: EE_Inst32<(outs FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, offset_16_16:$imm16f),
+ "ee.ldf.128.ip\t $fu3, $fu2, $fu1, $fu0, $as, $imm16f", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fu3;
+ bits<4> fu2;
+ bits<4> fu1;
+ bits<4> fu0;
+ bits<4> as;
+ bits<4> imm16f;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26-24} = fu3{3-1};
+ let Inst{23-20} = fu0{3-0};
+ let Inst{19} = fu3{0};
+ let Inst{18-16} = fu2{3-1};
+ let Inst{15-12} = fu1{3-0};
+ let Inst{11-8} = imm16f{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = fu2{0};
+}
+
+def EE_LDF_128_XP: EE_Inst32<(outs FPR:$fu3, FPR:$fu2, FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldf.128.xp\t $fu3, $fu2, $fu1, $fu0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fu3;
+ bits<4> fu2;
+ bits<4> fu1;
+ bits<4> fu0;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26-24} = fu3{3-1};
+ let Inst{23-20} = fu0{3-0};
+ let Inst{19} = fu3{0};
+ let Inst{18-16} = fu2{3-1};
+ let Inst{15-12} = fu1{3-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = fu2{0};
+}
+
+def EE_LDF_64_IP: EE_Inst32<(outs FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, offset_256_8:$imm8),
+ "ee.ldf.64.ip\t $fu1, $fu0, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fu1;
+ bits<4> fu0;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = imm8{7-6};
+ let Inst{23-20} = fu0{3-0};
+ let Inst{19-16} = imm8{5-2};
+ let Inst{11} = 0;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{15-12} = fu1{3-0};
+ let Inst{8} = imm8{0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = imm8{1};
+}
+
+def EE_LDF_64_XP: EE_Inst24<(outs FPR:$fu1, FPR:$fu0, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldf.64.xp\t $fu1, $fu0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fu1;
+ bits<4> fu0;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-20} = fu0{3-0};
+ let Inst{19-16} = 0x6;
+ let Inst{15-12} = fu1{3-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def EE_LDQA_S16_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ldqa.s16.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x2;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_S16_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldqa.s16.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-12} = 0x7e4;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_S8_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ldqa.s8.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x22;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_S8_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldqa.s8.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-12} = 0x714;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_U16_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ldqa.u16.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0xa;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_U16_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldqa.u16.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-12} = 0x7a4;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_U8_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ldqa.u8.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x2a;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDQA_U8_128_XP: EE_Inst24<(outs AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ldqa.u8.128.xp\t $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-12} = 0x704;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LDXQ_32: EE_Inst32<(outs QR:$qu), (ins QR:$qs, AR:$as, select_4:$sel4, select_8:$sel8),
+ "ee.ldxq.32\t $qu, $qs, $as, $sel4, $sel8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<3> qs;
+ bits<4> as;
+ bits<2> sel4;
+ bits<3> sel8;
+
+ let mayLoad = 1;
+
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = sel4{1};
+ let Inst{22} = 1;
+ let Inst{21} = 1;
+ let Inst{20} = 1;
+ let Inst{23} = sel8{0};
+ let Inst{19} = sel4{0};
+ let Inst{18-16} = qu{2-0};
+ let Inst{15-14} = qs{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = sel8{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qs{2};
+}
+
+def EE_LD_128_USAR_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ld.128.usar.ip\t $qu, $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm16{7};
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x1;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_128_USAR_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.ld.128.usar.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x0;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_ACCX_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_8:$imm8),
+ "ee.ld.accx.ip\t $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm8{7};
+ let Inst{21-15} = 0x1c;
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_QACC_H_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4),
+ "ee.ld.qacc_h.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm4;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm4{7};
+ let Inst{21-15} = 0x3c;
+ let Inst{14-8} = imm4{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_QACC_H_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ld.qacc_h.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0xc;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_QACC_L_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4),
+ "ee.ld.qacc_l.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm4;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm4{7};
+ let Inst{21-15} = 0x2c;
+ let Inst{14-8} = imm4{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_QACC_L_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ld.qacc_l.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x0;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_LD_UA_STATE_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.ld.ua_state.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x20;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_MOVI_32_A: EE_Inst24<(outs AR:$au), (ins QR:$qs, select_4:$sel4),
+ "ee.movi.32.a\t $qs, $au, $sel4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+ bits<4> au;
+ bits<2> sel4;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-12} = 0x7;
+ let Inst{11-10} = sel4{1-0};
+ let Inst{9-8} = 0x1;
+ let Inst{7-4} = au{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_MOVI_32_Q: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_4:$sel4),
+ "ee.movi.32.q\t $qu, $as, $sel4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<2> sel4;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x3;
+ let Inst{11-10} = sel4{1-0};
+ let Inst{9-8} = 0x2;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_MOV_S16_QACC: EE_Inst24<(outs), (ins QR:$qs),
+ "ee.mov.s16.qacc\t $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-0} = 0x7f24;
+}
+
+def EE_MOV_S8_QACC: EE_Inst24<(outs), (ins QR:$qs),
+ "ee.mov.s8.qacc\t $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-0} = 0x7f34;
+}
+
+def EE_MOV_U16_QACC: EE_Inst24<(outs), (ins QR:$qs),
+ "ee.mov.u16.qacc\t $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-0} = 0x7f64;
+}
+
+def EE_MOV_U8_QACC: EE_Inst24<(outs), (ins QR:$qs),
+ "ee.mov.u8.qacc\t $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-0} = 0x7f74;
+}
+
+def EE_NOTQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx),
+ "ee.notq\t $qa, $qx", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-8} = 0x7f;
+ let Inst{7-6} = qx{2-1};
+ let Inst{5} = 0x0;
+ let Inst{4} = qx{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ORQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.orq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-12} = 0x7;
+ let Inst{11-10} = qy{2-1};
+ let Inst{9-8} = 0x0;
+ let Inst{7-6} = qx{2-1};
+ let Inst{5} = qy{0};
+ let Inst{4} = qx{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SLCI_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r), (ins QR:$qs1, QR:$qs0, select_16:$sar16),
+ "ee.slci.2q\t $qs1, $qs0, $sar16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs1;
+ bits<3> qs0;
+ bits<4> sar16;
+
+
+ let Constraints = "$qs1r = $qs1, $qs0r = $qs0";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-8} = 0x6;
+ let Inst{7-4} = sar16{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SLCXXP_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r, AR:$asr), (ins QR:$qs1, QR:$qs0, AR:$as, AR:$ad),
+ "ee.slcxxp.2q\t $qs1, $qs0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs1;
+ bits<3> qs0;
+ bits<4> as;
+ bits<4> ad;
+
+
+ let Constraints = "$qs1r = $qs1, $qs0r = $qs0, $asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0x6;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRCI_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r), (ins QR:$qs1, QR:$qs0, select_16:$sar16),
+ "ee.srci.2q\t $qs1, $qs0, $sar16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs1;
+ bits<3> qs0;
+ bits<4> sar16;
+
+
+ let Constraints = "$qs1r = $qs1, $qs0r = $qs0";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-8} = 0xa;
+ let Inst{7-4} = sar16{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRCMB_S16_QACC: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_2:$sel2),
+ "ee.srcmb.s16.qacc\t $qu, $as, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<1> sel2;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-11} = 0xe;
+ let Inst{10} = sel2{0};
+ let Inst{9-8} = 0x2;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRCMB_S8_QACC: EE_Inst24<(outs QR:$qu), (ins AR:$as, select_2:$sel2),
+ "ee.srcmb.s8.qacc\t $qu, $as, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<1> sel2;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-11} = 0xf;
+ let Inst{10} = sel2{0};
+ let Inst{9-8} = 0x2;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRCQ_128_ST_INCP: EE_Inst24<(outs AR:$asr), (ins QR:$qs0, QR:$qs1, AR:$as),
+ "ee.srcq.128.st.incp\t $qs0, $qs1, $as", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+ bits<4> as;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-8} = 0xe;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRCXXP_2Q: EE_Inst24<(outs QR:$qs1r, QR:$qs0r, AR:$asr), (ins QR:$qs1, QR:$qs0, AR:$as, AR:$ad),
+ "ee.srcxxp.2q\t $qs1, $qs0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs1;
+ bits<3> qs0;
+ bits<4> as;
+ bits<4> ad;
+
+
+ let Constraints = "$qs1r = $qs1, $qs0r = $qs0, $asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0x6;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRC_Q: EE_Inst24<(outs QR:$qa), (ins QR:$qs0, QR:$qs1),
+ "ee.src.q\t $qa, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-7} = 0x6;
+ let Inst{6-4} = qa{2-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRC_Q_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_256_16:$imm16, QR:$qs0, QR:$qs1),
+ "ee.src.q.ld.ip\t $qu, $as, $imm16, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = imm16{7-6};
+ let Inst{23} = imm16{2};
+ let Inst{22-20} = qs1{2-0};
+ let Inst{19} = imm16{5};
+ let Inst{18-16} = qu{2-0};
+ let Inst{15-14} = qs0{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{13-12} = imm16{4-3};
+ let Inst{9-8} = imm16{1-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qs0{2};
+}
+
+def EE_SRC_Q_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qs0, QR:$qs1),
+ "ee.src.q.ld.xp\t $qu, $as, $ad, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = 0;
+ let Inst{19} = 0;
+ let Inst{22-20} = qs1{2-0};
+ let Inst{18-16} = qu{2-0};
+ let Inst{13} = 0;
+ let Inst{12} = 0;
+ let Inst{15-14} = qs0{1-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qs0{2};
+}
+
+def EE_SRC_Q_QUP: EE_Inst24<(outs QR:$qa, QR:$qs0r), (ins QR:$qs0, QR:$qs1),
+ "ee.src.q.qup\t $qa, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-7} = 0xe;
+ let Inst{6-4} = qa{2-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_SRS_ACCX: EE_Inst24<(outs AR:$au), (ins AR:$as, select_2:$sel2),
+ "ee.srs.accx\t $au, $as, $sel2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> au;
+ bits<4> as;
+ bits<1> sel2;
+
+
+ let Inst{23-15} = 0xfc;
+ let Inst{14} = sel2{0};
+ let Inst{13-12} = 0x1;
+ let Inst{11-8} = au{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_STF_128_IP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, offset_16_16:$imm16f),
+ "ee.stf.128.ip\t $fv3, $fv2, $fv1, $fv0, $as, $imm16f", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fv3;
+ bits<4> fv2;
+ bits<4> fv1;
+ bits<4> fv0;
+ bits<4> as;
+ bits<4> imm16f;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26-24} = fv3{3-1};
+ let Inst{23-20} = fv0{3-0};
+ let Inst{19} = fv3{0};
+ let Inst{18-16} = fv2{3-1};
+ let Inst{15-12} = fv1{3-0};
+ let Inst{11-8} = imm16f{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = fv2{0};
+}
+
+def EE_STF_128_XP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv3, FPR:$fv2, FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad),
+ "ee.stf.128.xp\t $fv3, $fv2, $fv1, $fv0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fv3;
+ bits<4> fv2;
+ bits<4> fv1;
+ bits<4> fv0;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27} = 1;
+ let Inst{26-24} = fv3{3-1};
+ let Inst{23-20} = fv0{3-0};
+ let Inst{19} = fv3{0};
+ let Inst{18-16} = fv2{3-1};
+ let Inst{15-12} = fv1{3-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = fv2{0};
+}
+
+def EE_STF_64_IP: EE_Inst32<(outs AR:$asr), (ins FPR:$fv1, FPR:$fv0, AR:$as, offset_256_8:$imm8),
+ "ee.stf.64.ip\t $fv1, $fv0, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fv1;
+ bits<4> fv0;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = imm8{7-6};
+ let Inst{23-20} = fv0{3-0};
+ let Inst{19-16} = imm8{5-2};
+ let Inst{11} = 0;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{15-12} = fv1{3-0};
+ let Inst{8} = imm8{0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = imm8{1};
+}
+
+def EE_STF_64_XP: EE_Inst24<(outs AR:$asr), (ins FPR:$fv1, FPR:$fv0, AR:$as, AR:$ad),
+ "ee.stf.64.xp\t $fv1, $fv0, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> fv1;
+ bits<4> fv0;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-20} = fv0{3-0};
+ let Inst{19-16} = 0x7;
+ let Inst{15-12} = fv1{3-0};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def EE_STXQ_32: EE_Inst32<(outs), (ins QR:$qv, QR:$qs, AR:$as, select_4:$sel4, select_8:$sel8),
+ "ee.stxq.32\t $qv, $qs, $as, $sel4, $sel8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<3> qs;
+ bits<4> as;
+ bits<2> sel4;
+ bits<3> sel8;
+
+ let mayStore = 1;
+
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 1;
+ let Inst{24} = sel4{1};
+ let Inst{23} = sel8{0};
+ let Inst{22-20} = qv{2-0};
+ let Inst{18} = 0;
+ let Inst{17} = 0;
+ let Inst{16} = 0;
+ let Inst{19} = sel4{0};
+ let Inst{15-14} = qs{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = sel8{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qs{2};
+}
+
+def EE_ST_ACCX_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_8:$imm8),
+ "ee.st.accx.ip\t $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm8{7};
+ let Inst{21-15} = 0x4;
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ST_QACC_H_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4),
+ "ee.st.qacc_h.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm4;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm4{7};
+ let Inst{21-15} = 0x24;
+ let Inst{14-8} = imm4{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ST_QACC_H_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.st.qacc_h.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x1a;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ST_QACC_L_H_32_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_4:$imm4),
+ "ee.st.qacc_l.h.32.ip\t $as, $imm4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm4;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm4{7};
+ let Inst{21-15} = 0x3a;
+ let Inst{14-8} = imm4{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ST_QACC_L_L_128_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.st.qacc_l.l.128.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x18;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ST_UA_STATE_IP: EE_Inst24<(outs AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.st.ua_state.ip\t $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x0;
+ let Inst{22} = imm16{7};
+ let Inst{21-15} = 0x38;
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VADDS_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vadds.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x64;
+}
+
+def EE_VADDS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VADDS_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VADDS_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vadds.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x74;
+}
+
+def EE_VADDS_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VADDS_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VADDS_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vadds.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VADDS_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VADDS_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vadds.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VCMP_EQ_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.eq.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x94;
+}
+
+def EE_VCMP_EQ_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.eq.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xa4;
+}
+
+def EE_VCMP_EQ_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.eq.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xb4;
+}
+
+def EE_VCMP_GT_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.gt.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VCMP_GT_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.gt.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xd4;
+}
+
+def EE_VCMP_GT_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.gt.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xe4;
+}
+
+def EE_VCMP_LT_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.lt.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xf4;
+}
+
+def EE_VCMP_LT_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.lt.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x4;
+}
+
+def EE_VCMP_LT_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vcmp.lt.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x14;
+}
+
+def EE_VLDBC_16: EE_Inst24<(outs QR:$qu), (ins AR:$as),
+ "ee.vldbc.16\t $qu, $as", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+
+ let mayLoad = 1;
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = 0x73;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_16_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_128_2:$imm2),
+ "ee.vldbc.16.ip\t $qu, $as, $imm2", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<7> imm2;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x5;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm2{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_16_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vldbc.16.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x4;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_32: EE_Inst24<(outs QR:$qu), (ins AR:$as),
+ "ee.vldbc.32\t $qu, $as", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+
+ let mayLoad = 1;
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = 0x77;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_32_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_4:$imm4),
+ "ee.vldbc.32.ip\t $qu, $as, $imm4", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm4;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm4{7};
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x2;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm4{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_32_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vldbc.32.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x1;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_8: EE_Inst24<(outs QR:$qu), (ins AR:$as),
+ "ee.vldbc.8\t $qu, $as", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+
+ let mayLoad = 1;
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = 0x3b;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_8_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_128_1:$imm1),
+ "ee.vldbc.8.ip\t $qu, $as, $imm1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<7> imm1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x5;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm1{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDBC_8_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vldbc.8.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x5;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLDHBC_16_INCP: EE_Inst24<(outs QR:$qu, QR:$qu1, AR:$asr), (ins AR:$as),
+ "ee.vldhbc.16.incp\t $qu, $qu1, $as", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<3> qu1;
+ bits<4> as;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = qu1{2-0};
+ let Inst{11-8} = 0x2;
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_128_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_16:$imm16),
+ "ee.vld.128.ip\t $qu, $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm16{7};
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x3;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_128_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vld.128.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x2;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_H_64_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_8:$imm8),
+ "ee.vld.h.64.ip\t $qu, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm8{7};
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x8;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_H_64_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vld.h.64.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x6;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_L_64_IP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_256_8:$imm8),
+ "ee.vld.l.64.ip\t $qu, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm8{7};
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0x9;
+ let Inst{15} = qu{0};
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VLD_L_64_XP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad),
+ "ee.vld.l.64.xp\t $qu, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qu{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qu{0};
+ let Inst{14-12} = 0x3;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VMAX_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmax.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x24;
+}
+
+def EE_VMAX_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMAX_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMAX_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmax.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x34;
+}
+
+def EE_VMAX_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMAX_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 0;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMAX_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmax.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x44;
+}
+
+def EE_VMAX_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMAX_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmax.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmin.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x54;
+}
+
+def EE_VMIN_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 0;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmin.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x64;
+}
+
+def EE_VMIN_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vmin.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x74;
+}
+
+def EE_VMIN_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMIN_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmin.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 0;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.s16.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x34;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VMULAS_S16_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.s16.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 0;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s16.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.s16.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 0;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s16.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.s16.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x34;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VMULAS_S16_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmulas.s16.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-21} = 0x4;
+ let Inst{20} = qu{2};
+ let Inst{19-16} = 0x7;
+ let Inst{15} = qu{1};
+ let Inst{14} = qy{2};
+ let Inst{13} = qu{0};
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VMULAS_S16_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s16.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.s16.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 0;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s16.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 0;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.s16.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 0;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S16_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s16.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.s8.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x34;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VMULAS_S8_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.s8.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 1;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s8.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.s8.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 1;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s8.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.s8.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x34;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VMULAS_S8_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmulas.s8.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-21} = 0x5;
+ let Inst{20} = qu{2};
+ let Inst{19-16} = 0x7;
+ let Inst{15} = qu{1};
+ let Inst{14} = qy{2};
+ let Inst{13} = qu{0};
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VMULAS_S8_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s8.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.s8.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 1;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s8.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.s8.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 0;
+ let Inst{17} = 1;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_S8_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.s8.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 0;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 1;
+ let Inst{26} = 1;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.u16.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x14;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VMULAS_U16_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.u16.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 0;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u16.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.u16.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 0;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u16.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.u16.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x14;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VMULAS_U16_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmulas.u16.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-21} = 0x6;
+ let Inst{20} = qu{2};
+ let Inst{19-16} = 0x7;
+ let Inst{15} = qu{1};
+ let Inst{14} = qy{2};
+ let Inst{13} = qu{0};
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VMULAS_U16_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u16.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.u16.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 0;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u16.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.u16.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 0;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U16_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u16.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_ACCX: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.u8.accx\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x14;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VMULAS_U8_ACCX_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.u8.accx.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 1;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_ACCX_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u8.accx.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_ACCX_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.u8.accx.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 1;
+ let Inst{16} = 0;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_ACCX_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u8.accx.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy),
+ "ee.vmulas.u8.qacc\t $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-15} = 0x14;
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VMULAS_U8_QACC_LDBC_INCP: EE_Inst24<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmulas.u8.qacc.ldbc.incp\t $qu, $as, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-21} = 0x7;
+ let Inst{20} = qu{2};
+ let Inst{19-16} = 0x7;
+ let Inst{15} = qu{1};
+ let Inst{14} = qy{2};
+ let Inst{13} = qu{0};
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VMULAS_U8_QACC_LDBC_INCP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u8.qacc.ldbc.incp.qup\t $qu, $as, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_QACC_LD_IP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy),
+ "ee.vmulas.u8.qacc.ld.ip\t $qu, $as, $imm16, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 1;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_QACC_LD_IP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, offset_64_16:$imm16, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u8.qacc.ld.ip.qup\t $qu, $as, $imm16, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<8> imm16;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 0;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27-26} = imm16{5-4};
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = imm16{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_QACC_LD_XP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy),
+ "ee.vmulas.u8.qacc.ld.xp\t $qu, $as, $ad, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 1;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{18} = 1;
+ let Inst{17} = 1;
+ let Inst{16} = 1;
+ let Inst{19} = qu{0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMULAS_U8_QACC_LD_XP_QUP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qs0r), (ins AR:$as, AR:$ad, QR:$qx, QR:$qy, QR:$qs0, QR:$qs1),
+ "ee.vmulas.u8.qacc.ld.xp.qup\t $qu, $as, $ad, $qx, $qy, $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<4> ad;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> qs0;
+ bits<3> qs1;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as, $qs0r = $qs0";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 0;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 1;
+ let Inst{25-24} = qu{2-1};
+ let Inst{23} = qy{0};
+ let Inst{22-20} = qs0{2-0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qs1{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{13-12} = qy{2-1};
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy),
+ "ee.vmul.s16\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x84;
+}
+
+def EE_VMUL_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.s16.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.s16.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_S8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy),
+ "ee.vmul.s8\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0x94;
+}
+
+def EE_VMUL_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.s8.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.s8.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 0;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_U16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy),
+ "ee.vmul.u16\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xa4;
+}
+
+def EE_VMUL_U16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.u16.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_U16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.u16.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 1;
+ let Inst{25} = 0;
+ let Inst{24} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_U8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy),
+ "ee.vmul.u8\t $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xb4;
+}
+
+def EE_VMUL_U8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qz), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.u8.ld.incp\t $qu, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 1;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VMUL_U8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qz), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vmul.u8.st.incp\t $qv, $as, $qz, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qz{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VPRELU_S16: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, AR:$ay),
+ "ee.vprelu.s16\t $qz, $qx, $qy, $ay", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<4> ay;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = ay{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VPRELU_S8: EE_Inst24<(outs QR:$qz), (ins QR:$qx, QR:$qy, AR:$ay),
+ "ee.vprelu.s8\t $qz, $qx, $qy, $ay", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qz;
+ bits<3> qx;
+ bits<3> qy;
+ bits<4> ay;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qz{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qz{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-4} = ay{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VRELU_S16: EE_Inst24<(outs QR:$qsr), (ins QR:$qs, AR:$ax, AR:$ay),
+ "ee.vrelu.s16\t $qs, $ax, $ay", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+ bits<4> ax;
+ bits<4> ay;
+
+
+ let Constraints = "$qsr = $qs";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-12} = 0x1;
+ let Inst{11-8} = ax{3-0};
+ let Inst{7-4} = ay{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VRELU_S8: EE_Inst24<(outs QR:$qsr), (ins QR:$qs, AR:$ax, AR:$ay),
+ "ee.vrelu.s8\t $qs, $ax, $ay", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs;
+ bits<4> ax;
+ bits<4> ay;
+
+
+ let Constraints = "$qsr = $qs";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-12} = 0x5;
+ let Inst{11-8} = ax{3-0};
+ let Inst{7-4} = ay{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VSL_32: EE_Inst24<(outs QR:$qa), (ins QR:$qs),
+ "ee.vsl.32\t $qa, $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-7} = 0x7e;
+ let Inst{6-4} = qa{2-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VSMULAS_S16_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy, select_8:$sel8),
+ "ee.vsmulas.s16.qacc\t $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> sel8;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = sel8{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = sel8{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xc4;
+}
+
+def EE_VSMULAS_S16_QACC_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy, select_8:$sel8),
+ "ee.vsmulas.s16.qacc.ld.incp\t $qu, $as, $qx, $qy, $sel8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<3> sel8;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 1;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = sel8{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSMULAS_S8_QACC: EE_Inst24<(outs), (ins QR:$qx, QR:$qy, select_16:$sel16),
+ "ee.vsmulas.s8.qacc\t $qx, $qy, $sel16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qx;
+ bits<3> qy;
+ bits<4> sel16;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = sel16{3-2};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = sel16{1};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x0;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-5} = 0x2;
+ let Inst{4} = sel16{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VSMULAS_S8_QACC_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr), (ins AR:$as, QR:$qx, QR:$qy, select_16:$sel16),
+ "ee.vsmulas.s8.qacc.ld.incp\t $qu, $as, $qx, $qy, $sel16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qx;
+ bits<3> qy;
+ bits<4> sel16;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 0;
+ let Inst{21} = 1;
+ let Inst{23} = qy{0};
+ let Inst{20} = sel16{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = sel16{3-1};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSR_32: EE_Inst24<(outs QR:$qa), (ins QR:$qs),
+ "ee.vsr.32\t $qa, $qs", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qs;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qs{0};
+ let Inst{14-7} = 0x7f;
+ let Inst{6-4} = qa{2-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_128_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_16:$imm16),
+ "ee.vst.128.ip\t $qv, $as, $imm16", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<8> imm16;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm16{7};
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xa;
+ let Inst{15} = qv{0};
+ let Inst{14-8} = imm16{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_128_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad),
+ "ee.vst.128.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qv{0};
+ let Inst{14-12} = 0x7;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_H_64_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_8:$imm8),
+ "ee.vst.h.64.ip\t $qv, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm8{7};
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xb;
+ let Inst{15} = qv{0};
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_H_64_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad),
+ "ee.vst.h.64.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qv{0};
+ let Inst{14-12} = 0x0;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_L_64_IP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, offset_256_8:$imm8),
+ "ee.vst.l.64.ip\t $qv, $as, $imm8", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<8> imm8;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23} = 0x1;
+ let Inst{22} = imm8{7};
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0x4;
+ let Inst{15} = qv{0};
+ let Inst{14-8} = imm8{6-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VST_L_64_XP: EE_Inst24<(outs AR:$asr), (ins QR:$qv, AR:$as, AR:$ad),
+ "ee.vst.l.64.xp\t $qv, $as, $ad", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<4> ad;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qv{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qv{0};
+ let Inst{14-12} = 0x4;
+ let Inst{11-8} = ad{3-0};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_VSUBS_S16: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vsubs.s16\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xd4;
+}
+
+def EE_VSUBS_S16_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s16.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 0;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSUBS_S16_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s16.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSUBS_S32: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vsubs.s32\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xe4;
+}
+
+def EE_VSUBS_S32_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s32.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 0;
+ let Inst{20} = 1;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSUBS_S32_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s32.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 0;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSUBS_S8: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.vsubs.s8\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xe;
+ let Inst{15} = qa{0};
+ let Inst{14} = qy{2};
+ let Inst{13} = 0x1;
+ let Inst{12-11} = qy{1-0};
+ let Inst{10-8} = qx{2-0};
+ let Inst{7-0} = 0xf4;
+}
+
+def EE_VSUBS_S8_LD_INCP: EE_Inst32<(outs QR:$qu, AR:$asr, QR:$qa), (ins AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s8.ld.incp\t $qu, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qu;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayLoad = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 0;
+ let Inst{26} = 0;
+ let Inst{25-24} = qu{2-1};
+ let Inst{22} = 1;
+ let Inst{21} = 1;
+ let Inst{20} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = qu{0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 1;
+ let Inst{10} = 1;
+ let Inst{9} = 0;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VSUBS_S8_ST_INCP: EE_Inst32<(outs AR:$asr, QR:$qa), (ins QR:$qv, AR:$as, QR:$qx, QR:$qy),
+ "ee.vsubs.s8.st.incp\t $qv, $as, $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qv;
+ bits<4> as;
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+ let mayStore = 1;
+
+ let Constraints = "$asr = $as";
+ let Inst{31} = 1;
+ let Inst{30} = 1;
+ let Inst{29} = 1;
+ let Inst{28} = 0;
+ let Inst{27} = 1;
+ let Inst{26} = 0;
+ let Inst{25} = 0;
+ let Inst{24} = 0;
+ let Inst{23} = qy{0};
+ let Inst{19} = 1;
+ let Inst{22-20} = qv{2-0};
+ let Inst{18-16} = qa{2-0};
+ let Inst{15-14} = qx{1-0};
+ let Inst{11} = 0;
+ let Inst{10} = 0;
+ let Inst{9} = 1;
+ let Inst{8} = 1;
+ let Inst{13-12} = qy{2-1};
+ let Inst{7-4} = as{3-0};
+ let Inst{3-1} = 0b111;
+ let Inst{0} = qx{2};
+}
+
+def EE_VUNZIP_16: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vunzip.16\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x384;
+}
+
+def EE_VUNZIP_32: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vunzip.32\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x394;
+}
+
+def EE_VUNZIP_8: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vunzip.8\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x3a4;
+}
+
+def EE_VZIP_16: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vzip.16\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x3b4;
+}
+
+def EE_VZIP_32: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vzip.32\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x3c4;
+}
+
+def EE_VZIP_8: EE_Inst24<(outs QR:$qs0r, QR:$qs1r), (ins QR:$qs0, QR:$qs1),
+ "ee.vzip.8\t $qs0, $qs1", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qs0;
+ bits<3> qs1;
+
+
+ let Constraints = "$qs0r = $qs0, $qs1r = $qs1";
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qs1{2-1};
+ let Inst{19-16} = 0xc;
+ let Inst{15} = qs1{0};
+ let Inst{14-12} = qs0{2-0};
+ let Inst{11-0} = 0x3d4;
+}
+
+def EE_XORQ: EE_Inst24<(outs QR:$qa), (ins QR:$qx, QR:$qy),
+ "ee.xorq\t $qa, $qx, $qy", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+ bits<3> qx;
+ bits<3> qy;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-12} = 0x3;
+ let Inst{11-10} = qy{2-1};
+ let Inst{9-8} = 0x1;
+ let Inst{7-6} = qx{2-1};
+ let Inst{5} = qy{0};
+ let Inst{4} = qx{0};
+ let Inst{3-0} = 0x4;
+}
+
+def EE_ZERO_ACCX: EE_Inst24<(outs), (ins),
+ "ee.zero.accx\t", []>, Requires<[HasESP32S3Ops]>
+{
+
+
+ let Inst{23-0} = 0x250804;
+}
+
+def EE_ZERO_Q: EE_Inst24<(outs QR:$qa), (ins),
+ "ee.zero.q\t $qa", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> qa;
+
+
+ let Inst{23-22} = 0x3;
+ let Inst{21-20} = qa{2-1};
+ let Inst{19-16} = 0xd;
+ let Inst{15} = qa{0};
+ let Inst{14-0} = 0x7fa4;
+}
+
+def EE_ZERO_QACC: EE_Inst24<(outs), (ins),
+ "ee.zero.qacc\t", []>, Requires<[HasESP32S3Ops]>
+{
+
+
+ let Inst{23-0} = 0x250844;
+}
+
+def RUR_ACCX_0: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.accx_0\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x0;
+}
+
+def RUR_ACCX_1: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.accx_1\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x10;
+}
+
+def RUR_FFT_BIT_WIDTH: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.fft_bit_width\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xe0;
+}
+
+def RUR_GPIO_OUT: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.gpio_out\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xc0;
+}
+
+def RUR_QACC_H_0: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_h_0\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x20;
+}
+
+def RUR_QACC_H_1: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_h_1\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x30;
+}
+
+def RUR_QACC_H_2: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_h_2\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x40;
+}
+
+def RUR_QACC_H_3: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_h_3\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x50;
+}
+
+def RUR_QACC_H_4: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_h_4\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x60;
+}
+
+def RUR_QACC_L_0: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_l_0\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x70;
+}
+
+def RUR_QACC_L_1: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_l_1\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x80;
+}
+
+def RUR_QACC_L_2: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_l_2\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x90;
+}
+
+def RUR_QACC_L_3: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_l_3\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xa0;
+}
+
+def RUR_QACC_L_4: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.qacc_l_4\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xb0;
+}
+
+def RUR_SAR_BYTE: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.sar_byte\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xd0;
+}
+
+def RUR_UA_STATE_0: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.ua_state_0\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0xf0;
+}
+
+def RUR_UA_STATE_1: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.ua_state_1\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x100;
+}
+
+def RUR_UA_STATE_2: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.ua_state_2\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x110;
+}
+
+def RUR_UA_STATE_3: EE_Inst24<(outs AR:$arr), (ins),
+ "rur.ua_state_3\t $arr", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> arr;
+
+
+ let Inst{23-16} = 0xe3;
+ let Inst{15-12} = arr{3-0};
+ let Inst{11-0} = 0x120;
+}
+
+def WUR_ACCX_0: EE_Inst24<(outs), (ins AR:$art),
+ "wur.accx_0\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf300;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_ACCX_1: EE_Inst24<(outs), (ins AR:$art),
+ "wur.accx_1\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf301;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_FFT_BIT_WIDTH: EE_Inst24<(outs), (ins AR:$art),
+ "wur.fft_bit_width\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30e;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_GPIO_OUT: EE_Inst24<(outs), (ins AR:$art),
+ "wur.gpio_out\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30c;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_H_0: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_h_0\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf302;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_H_1: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_h_1\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf303;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_H_2: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_h_2\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf304;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_H_3: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_h_3\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf305;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_H_4: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_h_4\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf306;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_L_0: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_l_0\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf307;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_L_1: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_l_1\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf308;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_L_2: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_l_2\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf309;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_L_3: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_l_3\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30a;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_QACC_L_4: EE_Inst24<(outs), (ins AR:$art),
+ "wur.qacc_l_4\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30b;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_SAR_BYTE: EE_Inst24<(outs), (ins AR:$art),
+ "wur.sar_byte\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30d;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_UA_STATE_0: EE_Inst24<(outs), (ins AR:$art),
+ "wur.ua_state_0\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf30f;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_UA_STATE_1: EE_Inst24<(outs), (ins AR:$art),
+ "wur.ua_state_1\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf310;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_UA_STATE_2: EE_Inst24<(outs), (ins AR:$art),
+ "wur.ua_state_2\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf311;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def WUR_UA_STATE_3: EE_Inst24<(outs), (ins AR:$art),
+ "wur.ua_state_3\t $art", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<4> art;
+
+
+ let Inst{23-8} = 0xf312;
+ let Inst{7-4} = art{3-0};
+ let Inst{3-0} = 0x0;
+}
+
+def mv_QR: EE_Inst24<(outs QR:$a), (ins QR:$b),
+ "mv.qr\t $a, $b", []>, Requires<[HasESP32S3Ops]>
+{
+ bits<3> a;
+ bits<3> b;
+
+
+ let Inst{23-22} = 0x2;
+ let Inst{21-20} = a{2-1};
+ let Inst{19-16} = 0xf;
+ let Inst{15} = a{0};
+ let Inst{14-12} = 0x0;
+ let Inst{11-10} = b{2-1};
+ let Inst{9-6} = 0x0;
+ let Inst{5} = b{0};
+ let Inst{4-0} = 0x4;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 007cc78047e69..5bf99b85c90ab 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -96,6 +96,7 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
bool hasException() const { return HasException; }
bool hasTHREADPTR() const { return HasTHREADPTR; }
bool hasESP32S2Ops() const { return HasESP32S2Ops; }
+ bool hasESP32S3Ops() const { return HasESP32S3Ops; }
bool isWindowedABI() const { return hasWindowed(); }
// Automatically generated by tblgen.
diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s
new file mode 100755
index 0000000000000..40d1637cd4a1e
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s
@@ -0,0 +1,1030 @@
+# RUN: llvm-mc %s -triple=xtensa -mcpu=esp32s3 -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+LBL0:
+
+# CHECK-INST: ee.clr_bit_gpio_out 52
+# CHECK: encoding: [0x44,0x43,0x76]
+ee.clr_bit_gpio_out 52
+
+# CHECK-INST: ee.get_gpio_in a2
+# CHECK: encoding: [0x24,0x08,0x65]
+ee.get_gpio_in a2
+
+# CHECK-INST: ee.set_bit_gpio_out 18
+# CHECK: encoding: [0x24,0x41,0x75]
+ee.set_bit_gpio_out 18
+
+# CHECK-INST: ee.wr_mask_gpio_out a3, a2
+# CHECK: encoding: [0x34,0x42,0x72]
+ee.wr_mask_gpio_out a3, a2
+
+# CHECK-INST: ee.andq q5, q6, q4
+# CHECK: encoding: [0xc4,0xb8,0xed]
+ee.andq q5, q6, q4
+
+# CHECK-INST: ee.bitrev q2, a6
+# CHECK: encoding: [0x64,0x7b,0xdd]
+ee.bitrev q2, a6
+
+# CHECK-INST: ee.cmul.s16 q3, q6, q2, 3
+# CHECK: encoding: [0x34,0x96,0x9e]
+ee.cmul.s16 q3, q6, q2, 3
+
+# CHECK-INST: ee.cmul.s16.ld.incp q2, a7, q5, q1, q4, 2
+# CHECK: encoding: [0x7e,0x6e,0x05,0xe1]
+ee.cmul.s16.ld.incp q2, a7, q5, q1, q4, 2
+
+# CHECK-INST: ee.cmul.s16.st.incp q7, a11, q1, q5, q2, 3
+# CHECK: encoding: [0xbf,0x53,0x71,0xe4]
+ee.cmul.s16.st.incp q7, a11, q1, q5, q2, 3
+
+# CHECK-INST: ee.fft.ams.s16.ld.incp q5, a5, q3, q1, q1, q2, q5, 1
+# CHECK: encoding: [0x5e,0x5d,0xa5,0xd2]
+ee.fft.ams.s16.ld.incp q5, a5, q3, q1, q1, q2, q5, 1
+
+# CHECK-INST: ee.fft.ams.s16.ld.incp.uaup q7, a12, q4, q1, q5, q6, q3, 0
+# CHECK: encoding: [0xcf,0x6f,0x63,0xd4]
+ee.fft.ams.s16.ld.incp.uaup q7, a12, q4, q1, q5, q6, q3, 0
+
+# CHECK-INST: ee.fft.ams.s16.ld.r32.decp q6, a5, q0, q2, q7, q2, q0, 0
+# CHECK: encoding: [0x5f,0xc6,0x28,0xd8]
+ee.fft.ams.s16.ld.r32.decp q6, a5, q0, q2, q7, q2, q0, 0
+
+# CHECK-INST: ee.fft.ams.s16.st.incp q3, q6, a7, a6, q5, q5, q1, 1
+# CHECK: encoding: [0x7f,0x46,0xb5,0xa7]
+ee.fft.ams.s16.st.incp q3, q6, a7, a6, q5, q5, q1, 1
+
+# CHECK-INST: ee.fft.cmul.s16.ld.xp q3, a12, a6, q7, q0, q7, 2
+# CHECK: encoding: [0xce,0x16,0xf7,0xdd]
+ee.fft.cmul.s16.ld.xp q3, a12, a6, q7, q0, q7, 2
+
+# CHECK-INST: ee.fft.cmul.s16.st.xp q4, q0, q0, a2, a8, 6, 1, 1
+# CHECK: encoding: [0x2f,0x38,0x08,0xaa]
+ee.fft.cmul.s16.st.xp q4, q0, q0, a2, a8, 6, 1, 1
+
+# CHECK-INST: ee.fft.r2bf.s16 q7, q1, q3, q6, 1
+# CHECK: encoding: [0x54,0x9d,0xfc]
+ee.fft.r2bf.s16 q7, q1, q3, q6, 1
+
+# CHECK-INST: ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 2
+# CHECK: encoding: [0x2e,0xd4,0x7f,0xe8]
+ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 2
+
+# CHECK-INST: ee.fft.vst.r32.decp q3, a14, 0
+# CHECK: encoding: [0xe4,0xb3,0xdd]
+ee.fft.vst.r32.decp q3, a14, 0
+
+# CHECK-INST: ee.ldf.128.ip f3, f5, f8, f0, a13, 64
+# CHECK: encoding: [0xdf,0x84,0x0a,0x81]
+ee.ldf.128.ip f3, f5, f8, f0, a13, 64
+
+# CHECK-INST: ee.ldf.128.xp f5, f2, f4, f4, a7, a8
+# CHECK: encoding: [0x7e,0x48,0x49,0x8a]
+ee.ldf.128.xp f5, f2, f4, f4, a7, a8
+
+# CHECK-INST: ee.ldf.64.ip f6, f5, a1, 488
+# CHECK: encoding: [0x1e,0x65,0x5f,0xe0]
+ee.ldf.64.ip f6, f5, a1, 488
+
+# CHECK-INST: ee.ldf.64.xp f0, f6, a3, a8
+# CHECK: encoding: [0x30,0x08,0x66]
+ee.ldf.64.xp f0, f6, a3, a8
+
+# CHECK-INST: ee.ldqa.s16.128.ip a11, 1904
+# CHECK: encoding: [0xb4,0x77,0x01]
+ee.ldqa.s16.128.ip a11, 1904
+
+# CHECK-INST: ee.ldqa.s16.128.xp a6, a2
+# CHECK: encoding: [0x64,0x42,0x7e]
+ee.ldqa.s16.128.xp a6, a2
+
+# CHECK-INST: ee.ldqa.s8.128.ip a8, 320
+# CHECK: encoding: [0x84,0x14,0x11]
+ee.ldqa.s8.128.ip a8, 320
+
+# CHECK-INST: ee.ldqa.s8.128.xp a6, a11
+# CHECK: encoding: [0x64,0x4b,0x71]
+ee.ldqa.s8.128.xp a6, a11
+
+# CHECK-INST: ee.ldqa.u16.128.ip a2, -1424
+# CHECK: encoding: [0x24,0x27,0x45]
+ee.ldqa.u16.128.ip a2, -1424
+
+# CHECK-INST: ee.ldqa.u16.128.xp a3, a4
+# CHECK: encoding: [0x34,0x44,0x7a]
+ee.ldqa.u16.128.xp a3, a4
+
+# CHECK-INST: ee.ldqa.u8.128.ip a4, 784
+# CHECK: encoding: [0x44,0x31,0x15]
+ee.ldqa.u8.128.ip a4, 784
+
+# CHECK-INST: ee.ldqa.u8.128.xp a4, a9
+# CHECK: encoding: [0x44,0x49,0x70]
+ee.ldqa.u8.128.xp a4, a9
+
+# CHECK-INST: ee.ldxq.32 q2, q6, a11, 2, 1
+# CHECK: encoding: [0xbf,0x8d,0xf2,0xe1]
+ee.ldxq.32 q2, q6, a11, 2, 1
+
+# CHECK-INST: ee.ld.128.usar.ip q4, a8, -592
+# CHECK: encoding: [0x84,0x5b,0xe1]
+ee.ld.128.usar.ip q4, a8, -592
+
+# CHECK-INST: ee.ld.128.usar.xp q1, a9, a7
+# CHECK: encoding: [0x94,0x87,0x8d]
+ee.ld.128.usar.xp q1, a9, a7
+
+# CHECK-INST: ee.ld.accx.ip a2, 720
+# CHECK: encoding: [0x24,0x5a,0x0e]
+ee.ld.accx.ip a2, 720
+
+# CHECK-INST: ee.ld.qacc_h.h.32.ip a6, -292
+# CHECK: encoding: [0x64,0x37,0x5e]
+ee.ld.qacc_h.h.32.ip a6, -292
+
+# CHECK-INST: ee.ld.qacc_h.l.128.ip a14, 96
+# CHECK: encoding: [0xe4,0x06,0x06]
+ee.ld.qacc_h.l.128.ip a14, 96
+
+# CHECK-INST: ee.ld.qacc_l.h.32.ip a0, -184
+# CHECK: encoding: [0x04,0x52,0x56]
+ee.ld.qacc_l.h.32.ip a0, -184
+
+# CHECK-INST: ee.ld.qacc_l.l.128.ip a5, -352
+# CHECK: encoding: [0x54,0x6a,0x40]
+ee.ld.qacc_l.l.128.ip a5, -352
+
+# CHECK-INST: ee.ld.ua_state.ip a3, 864
+# CHECK: encoding: [0x34,0x36,0x10]
+ee.ld.ua_state.ip a3, 864
+
+# CHECK-INST: ee.movi.32.a q7, a0, 1
+# CHECK: encoding: [0x04,0xf5,0xfd]
+ee.movi.32.a q7, a0, 1
+
+# CHECK-INST: ee.movi.32.q q5, a5, 3
+# CHECK: encoding: [0x54,0xbe,0xed]
+ee.movi.32.q q5, a5, 3
+
+# CHECK-INST: ee.mov.s16.qacc q1
+# CHECK: encoding: [0x24,0xff,0xcd]
+ee.mov.s16.qacc q1
+
+# CHECK-INST: ee.mov.s8.qacc q7
+# CHECK: encoding: [0x34,0xff,0xfd]
+ee.mov.s8.qacc q7
+
+# CHECK-INST: ee.mov.u16.qacc q2
+# CHECK: encoding: [0x64,0x7f,0xdd]
+ee.mov.u16.qacc q2
+
+# CHECK-INST: ee.mov.u8.qacc q2
+# CHECK: encoding: [0x74,0x7f,0xdd]
+ee.mov.u8.qacc q2
+
+# CHECK-INST: ee.notq q7, q0
+# CHECK: encoding: [0x04,0xff,0xfd]
+ee.notq q7, q0
+
+# CHECK-INST: ee.orq q1, q5, q3
+# CHECK: encoding: [0xb4,0xf4,0xcd]
+ee.orq q1, q5, q3
+
+# CHECK-INST: ee.slci.2q q7, q4, 2
+# CHECK: encoding: [0x24,0xc6,0xfc]
+ee.slci.2q q7, q4, 2
+
+# CHECK-INST: ee.slcxxp.2q q6, q7, a11, a4
+# CHECK: encoding: [0xb4,0x74,0xb6]
+ee.slcxxp.2q q6, q7, a11, a4
+
+# CHECK-INST: ee.srci.2q q6, q6, 14
+# CHECK: encoding: [0xe4,0x6a,0xfc]
+ee.srci.2q q6, q6, 14
+
+# CHECK-INST: ee.srcmb.s16.qacc q3, a7, 0
+# CHECK: encoding: [0x74,0xf2,0xdd]
+ee.srcmb.s16.qacc q3, a7, 0
+
+# CHECK-INST: ee.srcmb.s8.qacc q4, a1, 1
+# CHECK: encoding: [0x14,0x7e,0xed]
+ee.srcmb.s8.qacc q4, a1, 1
+
+# CHECK-INST: ee.srcq.128.st.incp q1, q4, a6
+# CHECK: encoding: [0x64,0x1e,0xec]
+ee.srcq.128.st.incp q1, q4, a6
+
+# CHECK-INST: ee.srcxxp.2q q6, q0, a2, a14
+# CHECK: encoding: [0x24,0x0e,0xf6]
+ee.srcxxp.2q q6, q0, a2, a14
+
+# CHECK-INST: ee.src.q q6, q7, q5
+# CHECK: encoding: [0x64,0xf3,0xec]
+ee.src.q q6, q7, q5
+
+# CHECK-INST: ee.src.q.ld.ip q2, a2, 1792, q6, q7
+# CHECK: encoding: [0x2f,0xa0,0x7a,0xe1]
+ee.src.q.ld.ip q2, a2, 1792, q6, q7
+
+# CHECK-INST: ee.src.q.ld.xp q2, a4, a9, q1, q7
+# CHECK: encoding: [0x4e,0x49,0x72,0xe8]
+ee.src.q.ld.xp q2, a4, a9, q1, q7
+
+# CHECK-INST: ee.src.q.qup q4, q3, q7
+# CHECK: encoding: [0x44,0xb7,0xfc]
+ee.src.q.qup q4, q3, q7
+
+# CHECK-INST: ee.srs.accx a12, a1, 0
+# CHECK: encoding: [0x14,0x1c,0x7e]
+ee.srs.accx a12, a1, 0
+
+# CHECK-INST: ee.stf.128.ip f4, f3, f8, f2, a4, -128
+# CHECK: encoding: [0x4f,0x88,0x21,0x92]
+ee.stf.128.ip f4, f3, f8, f2, a4, -128
+
+# CHECK-INST: ee.stf.128.xp f2, f0, f5, f8, a11, a5
+# CHECK: encoding: [0xbe,0x55,0x80,0x99]
+ee.stf.128.xp f2, f0, f5, f8, a11, a5
+
+# CHECK-INST: ee.stf.64.ip f3, f6, a10, -848
+# CHECK: encoding: [0xaf,0x36,0x65,0xe2]
+ee.stf.64.ip f3, f6, a10, -848
+
+# CHECK-INST: ee.stf.64.xp f2, f1, a1, a14
+# CHECK: encoding: [0x10,0x2e,0x17]
+ee.stf.64.xp f2, f1, a1, a14
+
+# CHECK-INST: ee.stxq.32 q5, q2, a5, 0, 1
+# CHECK: encoding: [0x5e,0x80,0xd0,0xe6]
+ee.stxq.32 q5, q2, a5, 0, 1
+
+# CHECK-INST: ee.st.accx.ip a10, 24
+# CHECK: encoding: [0xa4,0x03,0x02]
+ee.st.accx.ip a10, 24
+
+# CHECK-INST: ee.st.qacc_h.h.32.ip a14, 380
+# CHECK: encoding: [0xe4,0x5f,0x12]
+ee.st.qacc_h.h.32.ip a14, 380
+
+# CHECK-INST: ee.st.qacc_h.l.128.ip a7, -624
+# CHECK: encoding: [0x74,0x59,0x4d]
+ee.st.qacc_h.l.128.ip a7, -624
+
+# CHECK-INST: ee.st.qacc_l.h.32.ip a10, -20
+# CHECK: encoding: [0xa4,0x7b,0x5d]
+ee.st.qacc_l.h.32.ip a10, -20
+
+# CHECK-INST: ee.st.qacc_l.l.128.ip a4, 1936
+# CHECK: encoding: [0x44,0x79,0x0c]
+ee.st.qacc_l.l.128.ip a4, 1936
+
+# CHECK-INST: ee.st.ua_state.ip a4, -1728
+# CHECK: encoding: [0x44,0x14,0x5c]
+ee.st.ua_state.ip a4, -1728
+
+# CHECK-INST: ee.vadds.s16 q5, q1, q4
+# CHECK: encoding: [0x64,0xc1,0xae]
+ee.vadds.s16 q5, q1, q4
+
+# CHECK-INST: ee.vadds.s16.ld.incp q6, a6, q1, q3, q1
+# CHECK: encoding: [0x6e,0xcd,0xa1,0xe3]
+ee.vadds.s16.ld.incp q6, a6, q1, q3, q1
+
+# CHECK-INST: ee.vadds.s16.st.incp q4, a0, q1, q3, q1
+# CHECK: encoding: [0x0e,0xc0,0xc9,0xe4]
+ee.vadds.s16.st.incp q4, a0, q1, q3, q1
+
+# CHECK-INST: ee.vadds.s32 q3, q5, q2
+# CHECK: encoding: [0x74,0x95,0x9e]
+ee.vadds.s32 q3, q5, q2
+
+# CHECK-INST: ee.vadds.s32.ld.incp q4, a4, q1, q6, q5
+# CHECK: encoding: [0x4f,0xad,0xb1,0xe2]
+ee.vadds.s32.ld.incp q4, a4, q1, q6, q5
+
+# CHECK-INST: ee.vadds.s32.st.incp q5, a1, q0, q6, q0
+# CHECK: encoding: [0x1f,0x81,0x58,0xe4]
+ee.vadds.s32.st.incp q5, a1, q0, q6, q0
+
+# CHECK-INST: ee.vadds.s8 q4, q4, q5
+# CHECK: encoding: [0x84,0x4c,0xae]
+ee.vadds.s8 q4, q4, q5
+
+# CHECK-INST: ee.vadds.s8.ld.incp q2, a14, q0, q3, q3
+# CHECK: encoding: [0xee,0xdc,0x90,0xe1]
+ee.vadds.s8.ld.incp q2, a14, q0, q3, q3
+
+# CHECK-INST: ee.vadds.s8.st.incp q0, a9, q4, q7, q0
+# CHECK: encoding: [0x9f,0xc2,0x0c,0xe4]
+ee.vadds.s8.st.incp q0, a9, q4, q7, q0
+
+# CHECK-INST: ee.vcmp.eq.s16 q5, q3, q0
+# CHECK: encoding: [0x94,0x83,0xae]
+ee.vcmp.eq.s16 q5, q3, q0
+
+# CHECK-INST: ee.vcmp.eq.s32 q5, q5, q4
+# CHECK: encoding: [0xa4,0xc5,0xae]
+ee.vcmp.eq.s32 q5, q5, q4
+
+# CHECK-INST: ee.vcmp.eq.s8 q0, q4, q2
+# CHECK: encoding: [0xb4,0x14,0x8e]
+ee.vcmp.eq.s8 q0, q4, q2
+
+# CHECK-INST: ee.vcmp.gt.s16 q1, q5, q2
+# CHECK: encoding: [0xc4,0x95,0x8e]
+ee.vcmp.gt.s16 q1, q5, q2
+
+# CHECK-INST: ee.vcmp.gt.s32 q4, q1, q5
+# CHECK: encoding: [0xd4,0x49,0xae]
+ee.vcmp.gt.s32 q4, q1, q5
+
+# CHECK-INST: ee.vcmp.gt.s8 q3, q6, q3
+# CHECK: encoding: [0xe4,0x9e,0x9e]
+ee.vcmp.gt.s8 q3, q6, q3
+
+# CHECK-INST: ee.vcmp.lt.s16 q3, q7, q0
+# CHECK: encoding: [0xf4,0x87,0x9e]
+ee.vcmp.lt.s16 q3, q7, q0
+
+# CHECK-INST: ee.vcmp.lt.s32 q2, q2, q1
+# CHECK: encoding: [0x04,0x2a,0x9e]
+ee.vcmp.lt.s32 q2, q2, q1
+
+# CHECK-INST: ee.vcmp.lt.s8 q7, q1, q6
+# CHECK: encoding: [0x14,0xf1,0xbe]
+ee.vcmp.lt.s8 q7, q1, q6
+
+# CHECK-INST: ee.vldbc.16 q6, a11
+# CHECK: encoding: [0xb4,0x73,0xfd]
+ee.vldbc.16 q6, a11
+
+# CHECK-INST: ee.vldbc.16.ip q6, a4, 124
+# CHECK: encoding: [0x44,0x3e,0xb5]
+ee.vldbc.16.ip q6, a4, 124
+
+# CHECK-INST: ee.vldbc.16.xp q2, a0, a7
+# CHECK: encoding: [0x04,0x47,0x9d]
+ee.vldbc.16.xp q2, a0, a7
+
+# CHECK-INST: ee.vldbc.32 q4, a0
+# CHECK: encoding: [0x04,0x77,0xed]
+ee.vldbc.32 q4, a0
+
+# CHECK-INST: ee.vldbc.32.ip q6, a12, 308
+# CHECK: encoding: [0xc4,0x4d,0xb2]
+ee.vldbc.32.ip q6, a12, 308
+
+# CHECK-INST: ee.vldbc.32.xp q1, a11, a0
+# CHECK: encoding: [0xb4,0x90,0x8d]
+ee.vldbc.32.xp q1, a11, a0
+
+# CHECK-INST: ee.vldbc.8 q2, a3
+# CHECK: encoding: [0x34,0x3b,0xdd]
+ee.vldbc.8 q2, a3
+
+# CHECK-INST: ee.vldbc.8.ip q3, a3, 103
+# CHECK: encoding: [0x34,0xe7,0xd5]
+ee.vldbc.8.ip q3, a3, 103
+
+# CHECK-INST: ee.vldbc.8.xp q2, a0, a13
+# CHECK: encoding: [0x04,0x5d,0x9d]
+ee.vldbc.8.xp q2, a0, a13
+
+# CHECK-INST: ee.vldhbc.16.incp q5, q5, a14
+# CHECK: encoding: [0xe4,0xd2,0xec]
+ee.vldhbc.16.incp q5, q5, a14
+
+# CHECK-INST: ee.vld.128.ip q3, a14, 1248
+# CHECK: encoding: [0xe4,0xce,0x93]
+ee.vld.128.ip q3, a14, 1248
+
+# CHECK-INST: ee.vld.128.xp q5, a10, a12
+# CHECK: encoding: [0xa4,0xac,0xad]
+ee.vld.128.xp q5, a10, a12
+
+# CHECK-INST: ee.vld.h.64.ip q4, a14, 240
+# CHECK: encoding: [0xe4,0x1e,0xa8]
+ee.vld.h.64.ip q4, a14, 240
+
+# CHECK-INST: ee.vld.h.64.xp q7, a4, a8
+# CHECK: encoding: [0x44,0xe8,0xbd]
+ee.vld.h.64.xp q7, a4, a8
+
+# CHECK-INST: ee.vld.l.64.ip q1, a8, 8
+# CHECK: encoding: [0x84,0x81,0x89]
+ee.vld.l.64.ip q1, a8, 8
+
+# CHECK-INST: ee.vld.l.64.xp q1, a2, a9
+# CHECK: encoding: [0x24,0xb9,0x8d]
+ee.vld.l.64.xp q1, a2, a9
+
+# CHECK-INST: ee.vmax.s16 q2, q5, q6
+# CHECK: encoding: [0x24,0x75,0x9e]
+ee.vmax.s16 q2, q5, q6
+
+# CHECK-INST: ee.vmax.s16.ld.incp q0, a0, q6, q1, q2
+# CHECK: encoding: [0x0e,0x5d,0x16,0xe0]
+ee.vmax.s16.ld.incp q0, a0, q6, q1, q2
+
+# CHECK-INST: ee.vmax.s16.st.incp q5, a10, q6, q6, q7
+# CHECK: encoding: [0xaf,0xb3,0xde,0xe4]
+ee.vmax.s16.st.incp q5, a10, q6, q6, q7
+
+# CHECK-INST: ee.vmax.s32 q3, q2, q7
+# CHECK: encoding: [0x34,0xfa,0x9e]
+ee.vmax.s32 q3, q2, q7
+
+# CHECK-INST: ee.vmax.s32.ld.incp q1, a3, q1, q1, q0
+# CHECK: encoding: [0x3e,0x4e,0x19,0xe0]
+ee.vmax.s32.ld.incp q1, a3, q1, q1, q0
+
+# CHECK-INST: ee.vmax.s32.st.incp q3, a12, q4, q6, q3
+# CHECK: encoding: [0xcf,0x90,0xb4,0xe5]
+ee.vmax.s32.st.incp q3, a12, q4, q6, q3
+
+# CHECK-INST: ee.vmax.s8 q4, q1, q6
+# CHECK: encoding: [0x44,0x71,0xae]
+ee.vmax.s8 q4, q1, q6
+
+# CHECK-INST: ee.vmax.s8.ld.incp q3, a10, q5, q1, q5
+# CHECK: encoding: [0xae,0x6f,0x9d,0xe1]
+ee.vmax.s8.ld.incp q3, a10, q5, q1, q5
+
+# CHECK-INST: ee.vmax.s8.st.incp q3, a9, q3, q6, q7
+# CHECK: encoding: [0x9f,0xb0,0xbb,0xe5]
+ee.vmax.s8.st.incp q3, a9, q3, q6, q7
+
+# CHECK-INST: ee.vmin.s16 q6, q2, q5
+# CHECK: encoding: [0x54,0x6a,0xbe]
+ee.vmin.s16 q6, q2, q5
+
+# CHECK-INST: ee.vmin.s16.ld.incp q5, a3, q2, q4, q0
+# CHECK: encoding: [0x3f,0x0e,0x2a,0xe2]
+ee.vmin.s16.ld.incp q5, a3, q2, q4, q0
+
+# CHECK-INST: ee.vmin.s16.st.incp q4, a9, q4, q6, q0
+# CHECK: encoding: [0x9f,0x81,0x44,0xe5]
+ee.vmin.s16.st.incp q4, a9, q4, q6, q0
+
+# CHECK-INST: ee.vmin.s32 q1, q1, q6
+# CHECK: encoding: [0x64,0xf1,0x8e]
+ee.vmin.s32 q1, q1, q6
+
+# CHECK-INST: ee.vmin.s32.ld.incp q0, a1, q3, q2, q0
+# CHECK: encoding: [0x1e,0x8e,0x33,0xe0]
+ee.vmin.s32.ld.incp q0, a1, q3, q2, q0
+
+# CHECK-INST: ee.vmin.s32.st.incp q0, a12, q4, q4, q3
+# CHECK: encoding: [0xcf,0x11,0x8c,0xe5]
+ee.vmin.s32.st.incp q0, a12, q4, q4, q3
+
+# CHECK-INST: ee.vmin.s8 q7, q6, q0
+# CHECK: encoding: [0x74,0xa6,0xbe]
+ee.vmin.s8 q7, q6, q0
+
+# CHECK-INST: ee.vmin.s8.ld.incp q2, a13, q7, q7, q3
+# CHECK: encoding: [0xdf,0xdf,0xa7,0xe1]
+ee.vmin.s8.ld.incp q2, a13, q7, q7, q3
+
+# CHECK-INST: ee.vmin.s8.st.incp q2, a4, q4, q7, q1
+# CHECK: encoding: [0x4f,0xc2,0xa4,0xe5]
+ee.vmin.s8.st.incp q2, a4, q4, q7, q1
+
+# CHECK-INST: ee.vmulas.s16.accx q0, q7
+# CHECK: encoding: [0x84,0x58,0x1a]
+ee.vmulas.s16.accx q0, q7
+
+# CHECK-INST: ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0
+# CHECK: encoding: [0x7e,0x8f,0x08,0xff]
+ee.vmulas.s16.accx.ld.ip q7, a7, -16, q2, q0
+
+# CHECK-INST: ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2
+# CHECK: encoding: [0xee,0x12,0x0a,0x02]
+ee.vmulas.s16.accx.ld.ip.qup q5, a14, 32, q0, q2, q0, q2
+
+# CHECK-INST: ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6
+# CHECK: encoding: [0x0e,0xb1,0x18,0xf0]
+ee.vmulas.s16.accx.ld.xp q1, a0, a1, q2, q6
+
+# CHECK-INST: ee.vmulas.s16.accx.ld.xp.qup q4, a8, a10, q4, q0, q0, q3
+# CHECK: encoding: [0x8f,0x0a,0x03,0xb2]
+ee.vmulas.s16.accx.ld.xp.qup q4, a8, a10, q4, q0, q0, q3
+
+# CHECK-INST: ee.vmulas.s16.qacc q0, q6
+# CHECK: encoding: [0x84,0x70,0x1a]
+ee.vmulas.s16.qacc q0, q6
+
+# CHECK-INST: ee.vmulas.s16.qacc.ldbc.incp q2, a6, q3, q4
+# CHECK: encoding: [0x64,0xc3,0x87]
+ee.vmulas.s16.qacc.ldbc.incp q2, a6, q3, q4
+
+# CHECK-INST: ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5
+# CHECK: encoding: [0x4e,0x78,0x45,0xe0]
+ee.vmulas.s16.qacc.ldbc.incp.qup q0, a4, q1, q6, q4, q5
+
+# CHECK-INST: ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7
+# CHECK: encoding: [0x7f,0xfc,0x89,0xff]
+ee.vmulas.s16.qacc.ld.ip q7, a7, -64, q7, q7
+
+# CHECK-INST: ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6
+# CHECK: encoding: [0xae,0xf3,0x36,0x10]
+ee.vmulas.s16.qacc.ld.ip.qup q0, a10, 48, q3, q6, q3, q6
+
+# CHECK-INST: ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5
+# CHECK: encoding: [0xbf,0x24,0x99,0xf1]
+ee.vmulas.s16.qacc.ld.xp q3, a11, a4, q4, q5
+
+# CHECK-INST: ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7
+# CHECK: encoding: [0x9e,0xd1,0x17,0xb5]
+ee.vmulas.s16.qacc.ld.xp.qup q2, a9, a1, q3, q2, q1, q7
+
+# CHECK-INST: ee.vmulas.s8.accx q1, q0
+# CHECK: encoding: [0xc4,0x01,0x1a]
+ee.vmulas.s8.accx q1, q0
+
+# CHECK-INST: ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0
+# CHECK: encoding: [0x8e,0xc5,0x02,0xf1]
+ee.vmulas.s8.accx.ld.ip q2, a8, 80, q3, q0
+
+# CHECK-INST: ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3
+# CHECK: encoding: [0x9e,0x5b,0x63,0x2d]
+ee.vmulas.s8.accx.ld.ip.qup q2, a9, -80, q1, q2, q6, q3
+
+# CHECK-INST: ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7
+# CHECK: encoding: [0x3f,0x34,0x9a,0xf1]
+ee.vmulas.s8.accx.ld.xp q3, a3, a4, q4, q7
+
+# CHECK-INST: ee.vmulas.s8.accx.ld.xp.qup q0, a3, a1, q4, q5, q3, q3
+# CHECK: encoding: [0x3f,0x21,0xb3,0xb8]
+ee.vmulas.s8.accx.ld.xp.qup q0, a3, a1, q4, q5, q3, q3
+
+# CHECK-INST: ee.vmulas.s8.qacc q5, q7
+# CHECK: encoding: [0xc4,0x7d,0x1a]
+ee.vmulas.s8.qacc q5, q7
+
+# CHECK-INST: ee.vmulas.s8.qacc.ldbc.incp q7, a1, q6, q1
+# CHECK: encoding: [0x14,0xae,0xb7]
+ee.vmulas.s8.qacc.ldbc.incp q7, a1, q6, q1
+
+# CHECK-INST: ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6
+# CHECK: encoding: [0xbf,0x39,0x5e,0xe1]
+ee.vmulas.s8.qacc.ldbc.incp.qup q3, a11, q4, q6, q5, q6
+
+# CHECK-INST: ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0
+# CHECK: encoding: [0xae,0x0f,0x0b,0xfe]
+ee.vmulas.s8.qacc.ld.ip q5, a10, -16, q0, q0
+
+# CHECK-INST: ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2
+# CHECK: encoding: [0x9f,0x9d,0x1a,0x3f]
+ee.vmulas.s8.qacc.ld.ip.qup q7, a9, -48, q6, q2, q1, q2
+
+# CHECK-INST: ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0
+# CHECK: encoding: [0x1f,0x4c,0x1b,0xf0]
+ee.vmulas.s8.qacc.ld.xp q1, a1, a12, q5, q0
+
+# CHECK-INST: ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4
+# CHECK: encoding: [0x1e,0x7e,0x24,0xbc]
+ee.vmulas.s8.qacc.ld.xp.qup q0, a1, a14, q1, q6, q2, q4
+
+# CHECK-INST: ee.vmulas.u16.accx q7, q1
+# CHECK: encoding: [0x84,0x0f,0x0a]
+ee.vmulas.u16.accx q7, q1
+
+# CHECK-INST: ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4
+# CHECK: encoding: [0x8e,0x6e,0x0c,0xfe]
+ee.vmulas.u16.accx.ld.ip q5, a8, -32, q1, q4
+
+# CHECK-INST: ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0
+# CHECK: encoding: [0x0f,0xe3,0x48,0x40]
+ee.vmulas.u16.accx.ld.ip.qup q1, a0, 48, q7, q4, q4, q0
+
+# CHECK-INST: ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4
+# CHECK: encoding: [0xef,0x64,0x1c,0xf1]
+ee.vmulas.u16.accx.ld.xp q3, a14, a4, q5, q4
+
+# CHECK-INST: ee.vmulas.u16.accx.ld.xp.qup q4, a3, a7, q6, q2, q4, q4
+# CHECK: encoding: [0x3f,0x97,0x44,0xc2]
+ee.vmulas.u16.accx.ld.xp.qup q4, a3, a7, q6, q2, q4, q4
+
+# CHECK-INST: ee.vmulas.u16.qacc q5, q5
+# CHECK: encoding: [0x84,0x6d,0x0a]
+ee.vmulas.u16.qacc q5, q5
+
+# CHECK-INST: ee.vmulas.u16.qacc.ldbc.incp q6, a7, q0, q3
+# CHECK: encoding: [0x74,0x98,0xd7]
+ee.vmulas.u16.qacc.ldbc.incp q6, a7, q0, q3
+
+# CHECK-INST: ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0
+# CHECK: encoding: [0xcf,0x9a,0xa0,0xe0]
+ee.vmulas.u16.qacc.ldbc.incp.qup q0, a12, q6, q3, q2, q0
+
+# CHECK-INST: ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2
+# CHECK: encoding: [0xae,0xd1,0x05,0xf2]
+ee.vmulas.u16.qacc.ld.ip q4, a10, 16, q3, q2
+
+# CHECK-INST: ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6
+# CHECK: encoding: [0x4f,0x60,0x26,0x51]
+ee.vmulas.u16.qacc.ld.ip.qup q2, a4, 0, q5, q4, q2, q6
+
+# CHECK-INST: ee.vmulas.u16.qacc.ld.xp q6, a14, a2, q4, q0
+# CHECK: encoding: [0xef,0x02,0x15,0xf3]
+ee.vmulas.u16.qacc.ld.xp q6, a14, a2, q4, q0
+
+# CHECK-INST: ee.vmulas.u16.qacc.ld.xp.qup q6, a12, a11, q6, q7, q4, q1
+# CHECK: encoding: [0xcf,0xbb,0xc1,0xc7]
+ee.vmulas.u16.qacc.ld.xp.qup q6, a12, a11, q6, q7, q4, q1
+
+# CHECK-INST: ee.vmulas.u8.accx q2, q1
+# CHECK: encoding: [0xc4,0x0a,0x0a]
+ee.vmulas.u8.accx q2, q1
+
+# CHECK-INST: ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7
+# CHECK: encoding: [0x3e,0xb9,0x86,0xff]
+ee.vmulas.u8.accx.ld.ip q6, a3, -112, q2, q7
+
+# CHECK-INST: ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5
+# CHECK: encoding: [0x3e,0xde,0xfd,0x6f]
+ee.vmulas.u8.accx.ld.ip.qup q7, a3, -32, q3, q3, q7, q5
+
+# CHECK-INST: ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0
+# CHECK: encoding: [0x4f,0x09,0x16,0xf2]
+ee.vmulas.u8.accx.ld.xp q4, a4, a9, q4, q0
+
+# CHECK-INST: ee.vmulas.u8.accx.ld.xp.qup q5, a7, a13, q4, q7, q2, q6
+# CHECK: encoding: [0x7f,0x3d,0xae,0xca]
+ee.vmulas.u8.accx.ld.xp.qup q5, a7, a13, q4, q7, q2, q6
+
+# CHECK-INST: ee.vmulas.u8.qacc q3, q6
+# CHECK: encoding: [0xc4,0x73,0x0a]
+ee.vmulas.u8.qacc q3, q6
+
+# CHECK-INST: ee.vmulas.u8.qacc.ldbc.incp q4, a1, q0, q5
+# CHECK: encoding: [0x14,0x48,0xf7]
+ee.vmulas.u8.qacc.ldbc.incp q4, a1, q0, q5
+
+# CHECK-INST: ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4
+# CHECK: encoding: [0x1f,0x7b,0xe4,0xe1]
+ee.vmulas.u8.qacc.ldbc.incp.qup q2, a1, q5, q7, q6, q4
+
+# CHECK-INST: ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4
+# CHECK: encoding: [0xce,0x62,0x07,0xf1]
+ee.vmulas.u8.qacc.ld.ip q2, a12, 32, q1, q4
+
+# CHECK-INST: ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0
+# CHECK: encoding: [0x6e,0x03,0x60,0x70]
+ee.vmulas.u8.qacc.ld.ip.qup q0, a6, 48, q0, q0, q6, q0
+
+# CHECK-INST: ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5
+# CHECK: encoding: [0x1e,0xa1,0x97,0xf3]
+ee.vmulas.u8.qacc.ld.xp q6, a1, a1, q2, q5
+
+# CHECK-INST: ee.vmulas.u8.qacc.ld.xp.qup q1, a8, a10, q3, q7, q1, q3
+# CHECK: encoding: [0x8e,0xfa,0x9b,0xcc]
+ee.vmulas.u8.qacc.ld.xp.qup q1, a8, a10, q3, q7, q1, q3
+
+# CHECK-INST: ee.vmul.s16 q0, q4, q1
+# CHECK: encoding: [0x84,0x2c,0x8e]
+ee.vmul.s16 q0, q4, q1
+
+# CHECK-INST: ee.vmul.s16.ld.incp q4, a5, q1, q5, q5
+# CHECK: encoding: [0x5f,0x6f,0xb1,0xe2]
+ee.vmul.s16.ld.incp q4, a5, q1, q5, q5
+
+# CHECK-INST: ee.vmul.s16.st.incp q4, a4, q2, q5, q0
+# CHECK: encoding: [0x4f,0x42,0x4a,0xe5]
+ee.vmul.s16.st.incp q4, a4, q2, q5, q0
+
+# CHECK-INST: ee.vmul.s8 q5, q3, q2
+# CHECK: encoding: [0x94,0xb3,0xae]
+ee.vmul.s8 q5, q3, q2
+
+# CHECK-INST: ee.vmul.s8.ld.incp q6, a11, q3, q6, q4
+# CHECK: encoding: [0xbf,0xac,0x43,0xe3]
+ee.vmul.s8.ld.incp q6, a11, q3, q6, q4
+
+# CHECK-INST: ee.vmul.s8.st.incp q5, a5, q5, q2, q4
+# CHECK: encoding: [0x5e,0xa3,0x55,0xe5]
+ee.vmul.s8.st.incp q5, a5, q5, q2, q4
+
+# CHECK-INST: ee.vmul.u16 q0, q0, q5
+# CHECK: encoding: [0xa4,0x68,0x8e]
+ee.vmul.u16 q0, q0, q5
+
+# CHECK-INST: ee.vmul.u16.ld.incp q4, a2, q0, q1, q1
+# CHECK: encoding: [0x2e,0x4c,0xd0,0xe2]
+ee.vmul.u16.ld.incp q4, a2, q0, q1, q1
+
+# CHECK-INST: ee.vmul.u16.st.incp q6, a5, q1, q2, q7
+# CHECK: encoding: [0x5e,0xb3,0xe9,0xe5]
+ee.vmul.u16.st.incp q6, a5, q1, q2, q7
+
+# CHECK-INST: ee.vmul.u8 q6, q4, q5
+# CHECK: encoding: [0xb4,0x6c,0xbe]
+ee.vmul.u8 q6, q4, q5
+
+# CHECK-INST: ee.vmul.u8.ld.incp q1, a5, q4, q1, q1
+# CHECK: encoding: [0x5e,0x4c,0xec,0xe0]
+ee.vmul.u8.ld.incp q1, a5, q4, q1, q1
+
+# CHECK-INST: ee.vmul.u8.st.incp q4, a12, q5, q0, q4
+# CHECK: encoding: [0xce,0x20,0x4d,0xe8]
+ee.vmul.u8.st.incp q4, a12, q5, q0, q4
+
+# CHECK-INST: ee.vprelu.s16 q2, q7, q0, a1
+# CHECK: encoding: [0x14,0x07,0x9c]
+ee.vprelu.s16 q2, q7, q0, a1
+
+# CHECK-INST: ee.vprelu.s8 q5, q6, q5, a13
+# CHECK: encoding: [0xd4,0xee,0xac]
+ee.vprelu.s8 q5, q6, q5, a13
+
+# CHECK-INST: ee.vrelu.s16 q2, a14, a5
+# CHECK: encoding: [0x54,0x1e,0xdd]
+ee.vrelu.s16 q2, a14, a5
+
+# CHECK-INST: ee.vrelu.s8 q4, a14, a1
+# CHECK: encoding: [0x14,0x5e,0xed]
+ee.vrelu.s8 q4, a14, a1
+
+# CHECK-INST: ee.vsl.32 q0, q1
+# CHECK: encoding: [0x04,0xbf,0xcd]
+ee.vsl.32 q0, q1
+
+# CHECK-INST: ee.vsmulas.s16.qacc q2, q7, 2
+# CHECK: encoding: [0xc4,0x7a,0x9e]
+ee.vsmulas.s16.qacc q2, q7, 2
+
+# CHECK-INST: ee.vsmulas.s16.qacc.ld.incp q7, a3, q3, q4, 3
+# CHECK: encoding: [0x3e,0xec,0x7b,0xe3]
+ee.vsmulas.s16.qacc.ld.incp q7, a3, q3, q4, 3
+
+# CHECK-INST: ee.vsmulas.s8.qacc q3, q6, 3
+# CHECK: encoding: [0x54,0xd3,0x8e]
+ee.vsmulas.s8.qacc q3, q6, 3
+
+# CHECK-INST: ee.vsmulas.s8.qacc.ld.incp q1, a8, q1, q1, 4
+# CHECK: encoding: [0x8e,0x4c,0xaa,0xe0]
+ee.vsmulas.s8.qacc.ld.incp q1, a8, q1, q1, 4
+
+# CHECK-INST: ee.vsr.32 q4, q3
+# CHECK: encoding: [0xc4,0xbf,0xdd]
+ee.vsr.32 q4, q3
+
+# CHECK-INST: ee.vst.128.ip q3, a6, -816
+# CHECK: encoding: [0x64,0xcd,0xda]
+ee.vst.128.ip q3, a6, -816
+
+# CHECK-INST: ee.vst.128.xp q6, a12, a14
+# CHECK: encoding: [0xc4,0x7e,0xbd]
+ee.vst.128.xp q6, a12, a14
+
+# CHECK-INST: ee.vst.h.64.ip q2, a5, 40
+# CHECK: encoding: [0x54,0x05,0x9b]
+ee.vst.h.64.ip q2, a5, 40
+
+# CHECK-INST: ee.vst.h.64.xp q2, a13, a6
+# CHECK: encoding: [0xd4,0x06,0xdd]
+ee.vst.h.64.xp q2, a13, a6
+
+# CHECK-INST: ee.vst.l.64.ip q5, a8, 16
+# CHECK: encoding: [0x84,0x82,0xa4]
+ee.vst.l.64.ip q5, a8, 16
+
+# CHECK-INST: ee.vst.l.64.xp q0, a13, a6
+# CHECK: encoding: [0xd4,0x46,0xcd]
+ee.vst.l.64.xp q0, a13, a6
+
+# CHECK-INST: ee.vsubs.s16 q5, q1, q4
+# CHECK: encoding: [0xd4,0xe1,0xae]
+ee.vsubs.s16 q5, q1, q4
+
+# CHECK-INST: ee.vsubs.s16.ld.incp q1, a4, q6, q0, q1
+# CHECK: encoding: [0x4e,0x0d,0xce,0xe0]
+ee.vsubs.s16.ld.incp q1, a4, q6, q0, q1
+
+# CHECK-INST: ee.vsubs.s16.st.incp q7, a13, q7, q5, q2
+# CHECK: encoding: [0xdf,0x51,0x7f,0xe8]
+ee.vsubs.s16.st.incp q7, a13, q7, q5, q2
+
+# CHECK-INST: ee.vsubs.s32 q2, q7, q6
+# CHECK: encoding: [0xe4,0x77,0x9e]
+ee.vsubs.s32 q2, q7, q6
+
+# CHECK-INST: ee.vsubs.s32.ld.incp q1, a8, q1, q4, q0
+# CHECK: encoding: [0x8f,0x0d,0x59,0xe0]
+ee.vsubs.s32.ld.incp q1, a8, q1, q4, q0
+
+# CHECK-INST: ee.vsubs.s32.st.incp q1, a5, q7, q4, q0
+# CHECK: encoding: [0x5f,0x02,0x1f,0xe8]
+ee.vsubs.s32.st.incp q1, a5, q7, q4, q0
+
+# CHECK-INST: ee.vsubs.s8 q7, q1, q5
+# CHECK: encoding: [0xf4,0xe9,0xbe]
+ee.vsubs.s8 q7, q1, q5
+
+# CHECK-INST: ee.vsubs.s8.ld.incp q4, a2, q6, q1, q6
+# CHECK: encoding: [0x2e,0x7d,0x66,0xe2]
+ee.vsubs.s8.ld.incp q4, a2, q6, q1, q6
+
+# CHECK-INST: ee.vsubs.s8.st.incp q6, a1, q6, q2, q3
+# CHECK: encoding: [0x1e,0x93,0xee,0xe8]
+ee.vsubs.s8.st.incp q6, a1, q6, q2, q3
+
+# CHECK-INST: ee.vunzip.16 q6, q5
+# CHECK: encoding: [0x84,0xe3,0xec]
+ee.vunzip.16 q6, q5
+
+# CHECK-INST: ee.vunzip.32 q0, q6
+# CHECK: encoding: [0x94,0x03,0xfc]
+ee.vunzip.32 q0, q6
+
+# CHECK-INST: ee.vunzip.8 q5, q1
+# CHECK: encoding: [0xa4,0xd3,0xcc]
+ee.vunzip.8 q5, q1
+
+# CHECK-INST: ee.vzip.16 q2, q0
+# CHECK: encoding: [0xb4,0x23,0xcc]
+ee.vzip.16 q2, q0
+
+# CHECK-INST: ee.vzip.32 q0, q3
+# CHECK: encoding: [0xc4,0x83,0xdc]
+ee.vzip.32 q0, q3
+
+# CHECK-INST: ee.vzip.8 q4, q5
+# CHECK: encoding: [0xd4,0xc3,0xec]
+ee.vzip.8 q4, q5
+
+# CHECK-INST: ee.xorq q1, q3, q4
+# CHECK: encoding: [0x54,0xb9,0xcd]
+ee.xorq q1, q3, q4
+
+# CHECK-INST: ee.zero.accx
+# CHECK: encoding: [0x04,0x08,0x25]
+ee.zero.accx
+
+# CHECK-INST: ee.zero.q q0
+# CHECK: encoding: [0xa4,0x7f,0xcd]
+ee.zero.q q0
+
+# CHECK-INST: ee.zero.qacc
+# CHECK: encoding: [0x44,0x08,0x25]
+ee.zero.qacc
+
+# CHECK-INST: rur a11, accx_0
+# CHECK: encoding: [0x00,0xb0,0xe3]
+rur.accx_0 a11
+
+# CHECK-INST: rur a11, accx_1
+# CHECK: encoding: [0x10,0xb0,0xe3]
+rur.accx_1 a11
+
+# CHECK-INST: rur a11, fft_bit_width
+# CHECK: encoding: [0xe0,0xb0,0xe3]
+rur.fft_bit_width a11
+
+# CHECK-INST: rur a3, gpio_out
+# CHECK: encoding: [0xc0,0x30,0xe3]
+rur.gpio_out a3
+
+# CHECK-INST: rur a1, qacc_h_0
+# CHECK: encoding: [0x20,0x10,0xe3]
+rur.qacc_h_0 a1
+
+# CHECK-INST: rur a10, qacc_h_1
+# CHECK: encoding: [0x30,0xa0,0xe3]
+rur.qacc_h_1 a10
+
+# CHECK-INST: rur a2, qacc_h_2
+# CHECK: encoding: [0x40,0x20,0xe3]
+rur.qacc_h_2 a2
+
+# CHECK-INST: rur a11, qacc_h_3
+# CHECK: encoding: [0x50,0xb0,0xe3]
+rur.qacc_h_3 a11
+
+# CHECK-INST: rur a13, qacc_h_4
+# CHECK: encoding: [0x60,0xd0,0xe3]
+rur.qacc_h_4 a13
+
+# CHECK-INST: rur a8, qacc_l_0
+# CHECK: encoding: [0x70,0x80,0xe3]
+rur.qacc_l_0 a8
+
+# CHECK-INST: rur a7, qacc_l_1
+# CHECK: encoding: [0x80,0x70,0xe3]
+rur.qacc_l_1 a7
+
+# CHECK-INST: rur a2, qacc_l_2
+# CHECK: encoding: [0x90,0x20,0xe3]
+rur.qacc_l_2 a2
+
+# CHECK-INST: rur a13, qacc_l_3
+# CHECK: encoding: [0xa0,0xd0,0xe3]
+rur.qacc_l_3 a13
+
+# CHECK-INST: rur a7, qacc_l_4
+# CHECK: encoding: [0xb0,0x70,0xe3]
+rur.qacc_l_4 a7
+
+# CHECK-INST: rur a9, sar_byte
+# CHECK: encoding: [0xd0,0x90,0xe3]
+rur.sar_byte a9
+
+# CHECK-INST: rur a12, ua_state_0
+# CHECK: encoding: [0xf0,0xc0,0xe3]
+rur.ua_state_0 a12
+
+# CHECK-INST: rur a2, ua_state_1
+# CHECK: encoding: [0x00,0x21,0xe3]
+rur.ua_state_1 a2
+
+# CHECK-INST: rur a5, ua_state_2
+# CHECK: encoding: [0x10,0x51,0xe3]
+rur.ua_state_2 a5
+
+# CHECK-INST: rur a3, ua_state_3
+# CHECK: encoding: [0x20,0x31,0xe3]
+rur.ua_state_3 a3
+
+# CHECK-INST: wur a6, accx_0
+# CHECK: encoding: [0x60,0x00,0xf3]
+wur.accx_0 a6
+
+# CHECK-INST: wur a6, accx_1
+# CHECK: encoding: [0x60,0x01,0xf3]
+wur.accx_1 a6
+
+# CHECK-INST: wur a13, fft_bit_width
+# CHECK: encoding: [0xd0,0x0e,0xf3]
+wur.fft_bit_width a13
+
+# CHECK-INST: wur a0, gpio_out
+# CHECK: encoding: [0x00,0x0c,0xf3]
+wur.gpio_out a0
+
+# CHECK-INST: wur a12, qacc_h_0
+# CHECK: encoding: [0xc0,0x02,0xf3]
+wur.qacc_h_0 a12
+
+# CHECK-INST: wur a1, qacc_h_1
+# CHECK: encoding: [0x10,0x03,0xf3]
+wur.qacc_h_1 a1
+
+# CHECK-INST: wur a2, qacc_h_2
+# CHECK: encoding: [0x20,0x04,0xf3]
+wur.qacc_h_2 a2
+
+# CHECK-INST: wur a12, qacc_h_3
+# CHECK: encoding: [0xc0,0x05,0xf3]
+wur.qacc_h_3 a12
+
+# CHECK-INST: wur a14, qacc_h_4
+# CHECK: encoding: [0xe0,0x06,0xf3]
+wur.qacc_h_4 a14
+
+# CHECK-INST: wur a6, qacc_l_0
+# CHECK: encoding: [0x60,0x07,0xf3]
+wur.qacc_l_0 a6
+
+# CHECK-INST: wur a5, qacc_l_1
+# CHECK: encoding: [0x50,0x08,0xf3]
+wur.qacc_l_1 a5
+
+# CHECK-INST: wur a6, qacc_l_2
+# CHECK: encoding: [0x60,0x09,0xf3]
+wur.qacc_l_2 a6
+
+# CHECK-INST: wur a6, qacc_l_3
+# CHECK: encoding: [0x60,0x0a,0xf3]
+wur.qacc_l_3 a6
+
+# CHECK-INST: wur a7, qacc_l_4
+# CHECK: encoding: [0x70,0x0b,0xf3]
+wur.qacc_l_4 a7
+
+# CHECK-INST: wur a9, sar_byte
+# CHECK: encoding: [0x90,0x0d,0xf3]
+wur.sar_byte a9
+
+# CHECK-INST: wur a8, ua_state_0
+# CHECK: encoding: [0x80,0x0f,0xf3]
+wur.ua_state_0 a8
+
+# CHECK-INST: wur a14, ua_state_1
+# CHECK: encoding: [0xe0,0x10,0xf3]
+wur.ua_state_1 a14
+
+# CHECK-INST: wur a9, ua_state_2
+# CHECK: encoding: [0x90,0x11,0xf3]
+wur.ua_state_2 a9
+
+# CHECK-INST: wur a10, ua_state_3
+# CHECK: encoding: [0xa0,0x12,0xf3]
+wur.ua_state_3 a10
+
+# CHECK-INST: mv.qr q4, q7
+# CHECK: encoding: [0x24,0x0c,0xaf]
+mv.qr q4, q7
>From f6de58cca11aa7db2c90c0821e4825e223344f1b Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Sun, 13 Sep 2026 03:59:59 +0300
Subject: [PATCH 2/2] [Xtensa] Add test for esp32s3 target, minor fixes.
- Add test for esp32s3 specific instruction operands.
- Fix code format.
- Fix comment and remove redundant code in XtensaDisassembler
---
.../Disassembler/XtensaDisassembler.cpp | 38 +++----------
.../Xtensa/MCTargetDesc/XtensaInstPrinter.cpp | 47 +++++++++-------
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 2 +-
llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s | 55 +++++++++++++++++++
4 files changed, 92 insertions(+), 50 deletions(-)
create mode 100644 llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 4bc34fff4f00b..e5ac4afeead46 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -603,7 +603,8 @@ static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
/// Read three bytes from the ArrayRef and return 24 bit data
static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint64_t &Insn,
- bool IsLittleEndian, bool CheckTIE = false) {
+ bool IsLittleEndian,
+ bool CheckTIE = false) {
// We want to read exactly 3 Bytes of data.
if (Bytes.size() < 3) {
Size = 0;
@@ -621,7 +622,7 @@ static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
return MCDisassembler::Success;
}
-/// Read three bytes from the ArrayRef and return 32 bit data
+/// Read four bytes from the ArrayRef and return 32 bit data
static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint64_t &Insn,
bool IsLittleEndian) {
@@ -636,35 +637,13 @@ static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
} else {
if ((Bytes[0] & 0x8) == 0)
return MCDisassembler::Fail;
- Insn = (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
+ Insn =
+ (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
}
return MCDisassembler::Success;
}
-/// Read InstSize bytes from the ArrayRef and return 24 bit data
-static DecodeStatus readInstructionN(ArrayRef<uint8_t> Bytes, uint64_t Address,
- unsigned InstSize,
- uint64_t &Size, uint64_t &Insn,
- bool IsLittleEndian) {
- // We want to read exactly 3 Bytes of data.
- if (Bytes.size() < InstSize) {
- Size = 0;
- return MCDisassembler::Fail;
- }
-
- if (!IsLittleEndian) {
- report_fatal_error("Big-endian mode currently is not supported!");
- } else {
- Insn = 0;
- for (unsigned i = 0; i < InstSize; i++)
- Insn |= (Bytes[i] << 8*i);
- }
-
- Size = InstSize;
- return MCDisassembler::Success;
-}
-
#include "XtensaGenDisassemblerTables.inc"
DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
@@ -700,7 +679,8 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (hasESP32S3Ops()) {
// Parse ESP32S3 24-bit instructions
- Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian, true);
+ Result =
+ readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian, true);
if (Result != MCDisassembler::Fail) {
LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (24-bit opcodes):\n");
Result = decodeInstruction(DecoderTableESP32S324, MI, Insn, Address, this,
@@ -716,8 +696,8 @@ DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
LLVM_DEBUG(dbgs() << "Trying ESP32S3 table (32-bit opcodes):\n");
- Result = decodeInstruction(DecoderTableESP32S332, MI, Insn,
- Address, this, STI);
+ Result =
+ decodeInstruction(DecoderTableESP32S332, MI, Insn, Address, this, STI);
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
index 4ccfb614e068f..083e4ecaf93a5 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -441,7 +441,7 @@ void XtensaInstPrinter::printImm7_22_AsmOperand(const MCInst *MI, int OpNum,
}
void XtensaInstPrinter::printSelect_2_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 1) &&
@@ -452,7 +452,7 @@ void XtensaInstPrinter::printSelect_2_AsmOperand(const MCInst *MI, int OpNum,
}
void XtensaInstPrinter::printSelect_4_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 3) &&
@@ -463,7 +463,7 @@ void XtensaInstPrinter::printSelect_4_AsmOperand(const MCInst *MI, int OpNum,
}
void XtensaInstPrinter::printSelect_8_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 7) &&
@@ -474,7 +474,7 @@ void XtensaInstPrinter::printSelect_8_AsmOperand(const MCInst *MI, int OpNum,
}
void XtensaInstPrinter::printSelect_16_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 15) &&
@@ -495,21 +495,23 @@ void XtensaInstPrinter::printSelect_256_AsmOperand(const MCInst *MI, int OpNum,
printOperand(MI, OpNum, O);
}
-void XtensaInstPrinter::printOffset_16_16_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_16_16_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= -128 && Value <= 112 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-128,112], first 4 bits "
"should be zero");
O << Value;
- } else{
+ } else {
printOperand(MI, OpNum, O);
}
}
-void XtensaInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= -1024 && Value <= 1016 && (Value & 0x7) == 0) &&
@@ -520,21 +522,23 @@ void XtensaInstPrinter::printOffset_256_8_AsmOperand(const MCInst *MI, int OpNum
printOperand(MI, OpNum, O);
}
-void XtensaInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= -2048 && Value <= 2032 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-2048,2032], first 4 "
"bits should be zero");
O << Value;
- } else{
+ } else {
printOperand(MI, OpNum, O);
}
}
-void XtensaInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= -512 && Value <= 508 && (Value & 0x3) == 0) &&
@@ -545,8 +549,9 @@ void XtensaInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum
printOperand(MI, OpNum, O);
}
-void XtensaInstPrinter::printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_128_2_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 254 && (Value & 0x1) == 0) &&
@@ -557,8 +562,9 @@ void XtensaInstPrinter::printOffset_128_2_AsmOperand(const MCInst *MI, int OpNum
printOperand(MI, OpNum, O);
}
-void XtensaInstPrinter::printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_128_1_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= 0 && Value <= 127) &&
@@ -568,8 +574,9 @@ void XtensaInstPrinter::printOffset_128_1_AsmOperand(const MCInst *MI, int OpNum
printOperand(MI, OpNum, O);
}
-void XtensaInstPrinter::printOffset_64_16_AsmOperand(const MCInst *MI, int OpNum,
- raw_ostream &O) {
+void XtensaInstPrinter::printOffset_64_16_AsmOperand(const MCInst *MI,
+ int OpNum,
+ raw_ostream &O) {
if (MI->getOperand(OpNum).isImm()) {
int64_t Value = MI->getOperand(OpNum).getImm();
assert((Value >= -512 && Value <= 496 && (Value & 0xf) == 0) &&
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
index 619f231803c3e..d6c1627045e82 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -59,7 +59,7 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
}
// Reserve stack pointer.
Reserved.set(Xtensa::SP);
- //Reserve QR regs
+ // Reserve QR regs
Reserved.set(Xtensa::Q0);
Reserved.set(Xtensa::Q1);
Reserved.set(Xtensa::Q2);
diff --git a/llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s b/llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s
new file mode 100644
index 0000000000000..2056c91626b5b
--- /dev/null
+++ b/llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s
@@ -0,0 +1,55 @@
+# RUN: not llvm-mc %s -triple=xtensa -mcpu=esp32s3 2>&1 | FileCheck %s
+
+.align 4
+
+LBL0:
+
+# Out of range immediates
+
+# Select_2
+ee.fft.r2bf.s16 q7, q1, q3, q6, 6
+# CHECK: :[[#@LINE-1]]:33: error: expected immediate in range [0, 1]
+
+# Select_4
+ee.fft.r2bf.s16.st.incp q7, q3, q7, a2, 4
+# CHECK: :[[#@LINE-1]]:41: error: expected immediate in range [0, 3]
+
+# Select_8
+ee.ldxq.32 q2, q6, a11, 2, 9
+# CHECK: :[[#@LINE-1]]:28: error: expected immediate in range [0, 7]
+
+# Select_16
+ee.slci.2q q7, q4, 17
+# CHECK: :[[#@LINE-1]]:20: error: expected immediate in range [0, 15]
+
+# Select_256
+ee.set_bit_gpio_out 300
+# CHECK: :[[#@LINE-1]]:21: error: expected immediate in range [0, 255]
+
+# Offset_16_16
+ee.ldf.128.ip f3, f5, f8, f0, a13, 120
+# CHECK: :[[#@LINE-1]]:36: error: expected immediate in range [-128, 112], first 4 bits should be zero
+
+# Offset_256_8
+ee.ldf.64.ip f6, f5, a1, 2000
+# CHECK: :[[#@LINE-1]]:26: error: expected immediate in range [-1024, 1016], first 3 bits should be zero
+
+# Offset_256_16
+ee.ldqa.s16.128.ip a11, 3000
+# CHECK: :[[#@LINE-1]]:25: error: expected immediate in range [-2048, 2032], first 4 bits should be zero
+
+# Offset_256_4
+ee.ld.qacc_h.h.32.ip a6, -600
+# CHECK: :[[#@LINE-1]]:26: error: expected immediate in range [-512, 508], first 2 bits should be zero
+
+# Offset_128_2
+ee.vldbc.16.ip q6, a4, 300
+# CHECK: :[[#@LINE-1]]:24: error: expected immediate in range [0, 254], first bit should be zero
+
+# Offset_128_1
+ee.vldbc.8.ip q3, a3, 140
+# CHECK: :[[#@LINE-1]]:23: error: expected immediate in range [0, 127]
+
+# Offset_64_16
+ee.vmulas.s16.accx.ld.ip.qup q5, a14, 600, q0, q2, q0, q2
+# CHECK: :[[#@LINE-1]]:39: error: expected immediate in range [-512, 496], first 4 bits should be zero
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