[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Christudasan Devadasan via llvm-commits]

================
@@ -3602,12 +3631,44 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
         }
       }
 
+      if (RestoreFrameReg) {
+        // Put FrameReg back now that MI has consumed the scaled address.
+        // S_MUL_I32 undoes the scaling without writing SCC, which S_LSHL_B32
+        // would. When MI leaves SCC live, fold the offset back with the carry
+        // sequence that smuggles SCC through bit 0, which the scaling has just
+        // cleared.
+        MachineBasicBlock::iterator InsPt = std::next(MI);
+        BuildMI(*MBB, InsPt, DL, TII->get(AMDGPU::S_MUL_I32), FrameReg)
+            .addReg(FrameReg)
+            .addImm(ST.getWavefrontSize());
+
+        int64_t ScaledOffset = -Offset * ST.getWavefrontSize();
+        bool SCCLiveAfterMI = MI->definesRegister(AMDGPU::SCC, this) &&
+                              !MI->registerDefIsDead(AMDGPU::SCC, this);
+        if (Offset && !SCCLiveAfterMI) {
+          BuildMI(*MBB, InsPt, DL, TII->get(AMDGPU::S_ADD_I32), FrameReg)
+              .addReg(FrameReg)
+              .addImm(ScaledOffset);
+        } else if (Offset) {
----------------
cdevadas wrote:

Again, you could avoid checking Offset twice here.
```
if (Offset) {
  if (!SCCLivAfterMI) {
  ---
  }
  else { 
  ---
  }
}
```

https://github.com/llvm/llvm-project/pull/221972