[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Christudasan Devadasan via llvm-commits]

================
@@ -0,0 +1,184 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa -run-pass=prolog-epilog -o - %s 2>&1 | FileCheck %s
+---
+name:            scc_live_across_scalar_frame_index
+alignment:       4
----------------
cdevadas wrote:

Here the aligment as 4,  below the MaxAlign as 16, and later at the stack object, the alignment 16. Are they really required to reproduce the scenario?
I would assume the separate alignment and maxAlignment can be removed, and the alignment: 4 would suffice for the id: 0 field at line 10 below?

https://github.com/llvm/llvm-project/pull/221972