[llvm] [AMDGPU] Don't merge M0 initializations across calls that clobber M0 (PR #221963)

[Matt Arsenault via llvm-commits]

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@@ -458,6 +458,7 @@ getFirstNonPrologue(MachineBasicBlock *MBB, const TargetInstrInfo *TII) {
 // SGPR. A VGPR cannot be processed since we cannot guarantee vector
 // executioon.
 static bool hoistAndMergeSGPRInits(unsigned Reg,
+                                   ArrayRef<MachineInstr *> RegMaskInstrs,
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arsenm wrote:

Can you just check MRI.getUsedPhysRegsMask() instead of collecting your own set 

https://github.com/llvm/llvm-project/pull/221963