[llvm] [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 with Zfh (PR #222829)
Kane Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 11 02:25:57 PDT 2026
https://github.com/ReVe1uv updated https://github.com/llvm/llvm-project/pull/222829
>From d5a44c948984de98dc33dc69fa6fcd8e5b58aa52 Mon Sep 17 00:00:00 2001
From: Kane Wang <wangqiang1 at kylinos.cn>
Date: Thu, 10 Sep 2026 17:35:04 +0800
Subject: [PATCH 1/3] [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32
with Zfh
f16 is the only FP type whose finite values always fit in an i32 after
truncation towards zero, so the conversion can be done in i32 and
extended instead of a __fix(un)hfdi libcall. Out of range values and
NaN are poison, so the fcvt clamping is acceptable.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 34 +-
.../test/CodeGen/RISCV/half-convert-strict.ll | 28 +-
llvm/test/CodeGen/RISCV/half-convert.ll | 56 +--
llvm/test/CodeGen/RISCV/half-round-conv.ll | 320 ++----------------
4 files changed, 91 insertions(+), 347 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5f8ad5da42da1..d61edda2a0489 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -907,6 +907,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
MVT::i32, Custom);
setOperationAction(ISD::LROUND, MVT::i32, Custom);
+ } else if (Subtarget.hasStdExtZfhOrZhinx()) {
+ // f16 is the only FP type whose finite values always fit in an i32 after
+ // truncation towards zero, so an f16 to i64 conversion can be done by
+ // converting to i32 and extending, rather than using a libcall.
+ setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT,
+ ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
+ MVT::i64, Custom);
}
if (Subtarget.hasStdExtFOrZfinx()) {
@@ -16363,12 +16370,35 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: {
- assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
- "Unexpected custom legalisation");
bool IsStrict = N->isStrictFPOpcode();
bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
+
+ // On RV32, only f16 operands are handled here; other operand types fall
+ // back to the default expansion, which uses a libcall.
+ if (!Subtarget.is64Bit()) {
+ assert(N->getValueType(0) == MVT::i64 &&
+ "Unexpected custom legalisation");
+ if (Op0.getValueType() != MVT::f16)
+ return;
+ SDValue Cvt;
+ if (IsStrict) {
+ Cvt = DAG.getNode(
+ IsSigned ? ISD::STRICT_FP_TO_SINT : ISD::STRICT_FP_TO_UINT, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0), Op0);
+ } else {
+ Cvt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, DL,
+ MVT::i32, Op0);
+ }
+ Results.push_back(DAG.getNode(
+ IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, MVT::i64, Cvt));
+ if (IsStrict)
+ Results.push_back(Cvt.getValue(1));
+ return;
+ }
+
+ assert(N->getValueType(0) == MVT::i32 && "Unexpected custom legalisation");
if (getTypeAction(*DAG.getContext(), Op0.getValueType()) !=
TargetLowering::TypeSoftenFloat) {
if (!isTypeLegal(Op0.getValueType()))
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 4a6f8a0d9a6d3..73aca398827c6 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -399,11 +399,8 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp {
define i64 @fcvt_l_h(half %a) nounwind strictfp {
; CHECK32-IZFH-LABEL: fcvt_l_h:
; CHECK32-IZFH: # %bb.0:
-; CHECK32-IZFH-NEXT: addi sp, sp, -16
-; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFH-NEXT: call __fixhfdi
-; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFH-NEXT: addi sp, sp, 16
+; CHECK32-IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; CHECK32-IZFH-NEXT: srai a1, a0, 31
; CHECK32-IZFH-NEXT: ret
;
; CHECK64-IZFH-LABEL: fcvt_l_h:
@@ -413,11 +410,8 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINX-LABEL: fcvt_l_h:
; CHECK32-IZHINX: # %bb.0:
-; CHECK32-IZHINX-NEXT: addi sp, sp, -16
-; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINX-NEXT: call __fixhfdi
-; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINX-NEXT: addi sp, sp, 16
+; CHECK32-IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; CHECK32-IZHINX-NEXT: srai a1, a0, 31
; CHECK32-IZHINX-NEXT: ret
;
; CHECK64-IZHINX-LABEL: fcvt_l_h:
@@ -475,11 +469,8 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
define i64 @fcvt_lu_h(half %a) nounwind strictfp {
; CHECK32-IZFH-LABEL: fcvt_lu_h:
; CHECK32-IZFH: # %bb.0:
-; CHECK32-IZFH-NEXT: addi sp, sp, -16
-; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFH-NEXT: call __fixunshfdi
-; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFH-NEXT: addi sp, sp, 16
+; CHECK32-IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; CHECK32-IZFH-NEXT: li a1, 0
; CHECK32-IZFH-NEXT: ret
;
; CHECK64-IZFH-LABEL: fcvt_lu_h:
@@ -489,11 +480,8 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINX-LABEL: fcvt_lu_h:
; CHECK32-IZHINX: # %bb.0:
-; CHECK32-IZHINX-NEXT: addi sp, sp, -16
-; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINX-NEXT: call __fixunshfdi
-; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINX-NEXT: addi sp, sp, 16
+; CHECK32-IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; CHECK32-IZHINX-NEXT: li a1, 0
; CHECK32-IZHINX-NEXT: ret
;
; CHECK64-IZHINX-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 646b13c825195..fe2de98417df8 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -1991,11 +1991,8 @@ start:
define i64 @fcvt_l_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_l_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_l_h:
@@ -2005,11 +2002,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IDZFH-LABEL: fcvt_l_h:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: call __fixhfdi
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: srai a1, a0, 31
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_l_h:
@@ -2019,11 +2013,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_l_h:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_l_h:
@@ -2033,11 +2024,8 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; RV32IZDINXZHINX-LABEL: fcvt_l_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: call __fixhfdi
-; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT: srai a1, a0, 31
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_l_h:
@@ -2753,11 +2741,8 @@ start:
define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_lu_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: addi sp, sp, 16
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_lu_h:
@@ -2767,11 +2752,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IDZFH-LABEL: fcvt_lu_h:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: addi sp, sp, -16
-; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IDZFH-NEXT: call __fixunshfdi
-; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IDZFH-NEXT: addi sp, sp, 16
+; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: li a1, 0
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_lu_h:
@@ -2781,11 +2763,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IZHINX-LABEL: fcvt_lu_h:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: addi sp, sp, 16
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_lu_h:
@@ -2795,11 +2774,8 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; RV32IZDINXZHINX-LABEL: fcvt_lu_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
-; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZDINXZHINX-NEXT: call __fixunshfdi
-; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT: li a1, 0
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 7c3ef17d952a8..4a08868723da5 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -309,26 +309,8 @@ define signext i32 @test_floor_si32(half %x) {
define i64 @test_floor_si64(half %x) {
; RV32IZFH-LABEL: test_floor_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB3_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB3_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_si64:
@@ -348,15 +330,8 @@ define i64 @test_floor_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB3_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_si64:
@@ -755,26 +730,8 @@ define signext i32 @test_floor_ui32(half %x) {
define i64 @test_floor_ui64(half %x) {
; RV32IZFH-LABEL: test_floor_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB7_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB7_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_ui64:
@@ -794,15 +751,8 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB7_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_floor_ui64:
@@ -1201,26 +1151,8 @@ define signext i32 @test_ceil_si32(half %x) {
define i64 @test_ceil_si64(half %x) {
; RV32IZFH-LABEL: test_ceil_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB11_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB11_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_si64:
@@ -1240,15 +1172,8 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB11_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_si64:
@@ -1647,26 +1572,8 @@ define signext i32 @test_ceil_ui32(half %x) {
define i64 @test_ceil_ui64(half %x) {
; RV32IZFH-LABEL: test_ceil_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB15_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB15_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_ui64:
@@ -1686,15 +1593,8 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB15_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_ceil_ui64:
@@ -2093,26 +1993,8 @@ define signext i32 @test_trunc_si32(half %x) {
define i64 @test_trunc_si64(half %x) {
; RV32IZFH-LABEL: test_trunc_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB19_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB19_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_si64:
@@ -2132,15 +2014,8 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB19_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_si64:
@@ -2539,26 +2414,8 @@ define signext i32 @test_trunc_ui32(half %x) {
define i64 @test_trunc_ui64(half %x) {
; RV32IZFH-LABEL: test_trunc_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB23_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB23_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_ui64:
@@ -2578,15 +2435,8 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB23_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_trunc_ui64:
@@ -2985,26 +2835,8 @@ define signext i32 @test_round_si32(half %x) {
define i64 @test_round_si64(half %x) {
; RV32IZFH-LABEL: test_round_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB27_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB27_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_si64:
@@ -3024,15 +2856,8 @@ define i64 @test_round_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB27_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_si64:
@@ -3431,26 +3256,8 @@ define signext i32 @test_round_ui32(half %x) {
define i64 @test_round_ui64(half %x) {
; RV32IZFH-LABEL: test_round_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB31_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB31_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_ui64:
@@ -3470,15 +3277,8 @@ define i64 @test_round_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB31_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_round_ui64:
@@ -3877,26 +3677,8 @@ define signext i32 @test_roundeven_si32(half %x) {
define i64 @test_roundeven_si64(half %x) {
; RV32IZFH-LABEL: test_roundeven_si64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB35_2
-; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB35_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixhfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: srai a1, a0, 31
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_si64:
@@ -3916,15 +3698,8 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB35_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixhfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT: srai a1, a0, 31
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_si64:
@@ -4323,26 +4098,8 @@ define signext i32 @test_roundeven_ui32(half %x) {
define i64 @test_roundeven_ui64(half %x) {
; RV32IZFH-LABEL: test_roundeven_ui64:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: li a0, 25
-; RV32IZFH-NEXT: slli a0, a0, 10
-; RV32IZFH-NEXT: fmv.h.x fa5, a0
-; RV32IZFH-NEXT: fabs.h fa4, fa0
-; RV32IZFH-NEXT: flt.h a0, fa4, fa5
-; RV32IZFH-NEXT: beqz a0, .LBB39_2
-; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
-; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
-; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
-; RV32IZFH-NEXT: .LBB39_2:
-; RV32IZFH-NEXT: addi sp, sp, -16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT: .cfi_offset ra, -4
-; RV32IZFH-NEXT: call __fixunshfdi
-; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT: .cfi_restore ra
-; RV32IZFH-NEXT: addi sp, sp, 16
-; RV32IZFH-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_ui64:
@@ -4362,15 +4119,8 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
; RV32IZHINX-NEXT: .LBB39_2:
-; RV32IZHINX-NEXT: addi sp, sp, -16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT: .cfi_offset ra, -4
-; RV32IZHINX-NEXT: call __fixunshfdi
-; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT: .cfi_restore ra
-; RV32IZHINX-NEXT: addi sp, sp, 16
-; RV32IZHINX-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: li a1, 0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: test_roundeven_ui64:
>From 08e8d8d2814f634dc56f72f3efdf47d4e5c541af Mon Sep 17 00:00:00 2001
From: Kane Wang <wangqiang1 at kylinos.cn>
Date: Fri, 11 Sep 2026 17:14:56 +0800
Subject: [PATCH 2/3] [RISCV] Extend f16 to i64 fp_to_[su]int lowering to
Zfhmin/Zhinxmin
Zfhmin/Zhinxmin already custom lower f16 to i32 conversions by promoting
f16 to f32, so the same lowering applies to i64 and RV32 stops emitting
calls to __fixhfdi/__fixunshfdi, which compiler-rt does not provide.
Both extensions imply F/Zfinx, so f32 is always legal here.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 17 +-
.../test/CodeGen/RISCV/half-convert-strict.ll | 32 +--
llvm/test/CodeGen/RISCV/half-convert.ll | 48 ++--
llvm/test/CodeGen/RISCV/half-round-conv.ll | 260 +++++-------------
4 files changed, 110 insertions(+), 247 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d61edda2a0489..b3f6a00cff2e8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -907,10 +907,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
MVT::i32, Custom);
setOperationAction(ISD::LROUND, MVT::i32, Custom);
- } else if (Subtarget.hasStdExtZfhOrZhinx()) {
- // f16 is the only FP type whose finite values always fit in an i32 after
- // truncation towards zero, so an f16 to i64 conversion can be done by
- // converting to i32 and extending, rather than using a libcall.
+ } else if (Subtarget.hasStdExtZfhminOrZhinxmin()) {
+ // i64 is not a legal type on RV32, so these are custom expanded in
+ // ReplaceNodeResults: f16 sources are converted to i32 and extended, other
+ // FP sources fall back to the default libcall expansion.
setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT,
ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
MVT::i64, Custom);
@@ -16375,8 +16375,11 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
- // On RV32, only f16 operands are handled here; other operand types fall
- // back to the default expansion, which uses a libcall.
+ // On RV32 only f16 is handled here: it is the only FP type whose finite
+ // values always fit in an i32 after truncation towards zero, so convert in
+ // i32 and extend instead of calling __fix(un)hfdi, which compiler-rt does
+ // not provide. Out of range values and NaN are poison, so the fcvt clamping
+ // is acceptable. Without Zfh/Zhinx the i32 conversion promotes f16 to f32.
if (!Subtarget.is64Bit()) {
assert(N->getValueType(0) == MVT::i64 &&
"Unexpected custom legalisation");
@@ -16386,7 +16389,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
if (IsStrict) {
Cvt = DAG.getNode(
IsSigned ? ISD::STRICT_FP_TO_SINT : ISD::STRICT_FP_TO_UINT, DL,
- DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0), Op0);
+ {MVT::i32, MVT::Other}, {N->getOperand(0), Op0});
} else {
Cvt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, DL,
MVT::i32, Op0);
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 73aca398827c6..8653943cc94c9 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -421,11 +421,9 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
;
; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
; CHECK32-IZFHMIN: # %bb.0:
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFHMIN-NEXT: call __fixhfdi
-; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: srai a1, a0, 31
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
@@ -436,11 +434,9 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_l_h:
; CHECK32-IZHINXMIN: # %bb.0:
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: call __fixhfdi
-; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: srai a1, a0, 31
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_l_h:
@@ -491,11 +487,9 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp {
;
; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
; CHECK32-IZFHMIN: # %bb.0:
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFHMIN-NEXT: call __fixunshfdi
-; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: li a1, 0
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
@@ -506,11 +500,9 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h:
; CHECK32-IZHINXMIN: # %bb.0:
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi
-; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: li a1, 0
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index fe2de98417df8..22d5e58886e67 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -2098,11 +2098,9 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
; CHECK32-IZFHMIN: # %bb.0:
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFHMIN-NEXT: call __fixhfdi
-; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: srai a1, a0, 31
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
@@ -2113,11 +2111,9 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_l_h:
; CHECK32-IZHINXMIN: # %bb.0:
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: call __fixhfdi
-; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: srai a1, a0, 31
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_l_h:
@@ -2128,11 +2124,9 @@ define i64 @fcvt_l_h(half %a) nounwind {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi
-; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: srai a1, a0, 31
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h:
@@ -2848,11 +2842,9 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
; CHECK32-IZFHMIN: # %bb.0:
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZFHMIN-NEXT: call __fixunshfdi
-; CHECK32-IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: li a1, 0
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
@@ -2863,11 +2855,9 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h:
; CHECK32-IZHINXMIN: # %bb.0:
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZHINXMIN-NEXT: call __fixunshfdi
-; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: li a1, 0
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h:
@@ -2878,11 +2868,9 @@ define i64 @fcvt_lu_h(half %a) nounwind {
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi
-; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: li a1, 0
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 4a08868723da5..b0214728bb69a 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -362,16 +362,10 @@ define i64 @test_floor_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB3_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixhfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: srai a1, a0, 31
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_si64:
@@ -404,16 +398,10 @@ define i64 @test_floor_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB3_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixhfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: srai a1, a0, 31
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_si64:
@@ -783,16 +771,10 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB7_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixunshfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: li a1, 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_ui64:
@@ -825,16 +807,10 @@ define i64 @test_floor_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB7_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixunshfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: li a1, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_ui64:
@@ -1204,16 +1180,10 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB11_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixhfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: srai a1, a0, 31
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_si64:
@@ -1246,16 +1216,10 @@ define i64 @test_ceil_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB11_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixhfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: srai a1, a0, 31
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_si64:
@@ -1625,16 +1589,10 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB15_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixunshfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: li a1, 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_ui64:
@@ -1667,16 +1625,10 @@ define i64 @test_ceil_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB15_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixunshfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: li a1, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_ui64:
@@ -2046,16 +1998,10 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB19_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixhfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: srai a1, a0, 31
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_si64:
@@ -2088,16 +2034,10 @@ define i64 @test_trunc_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB19_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixhfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: srai a1, a0, 31
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_si64:
@@ -2467,16 +2407,10 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB23_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixunshfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: li a1, 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_ui64:
@@ -2509,16 +2443,10 @@ define i64 @test_trunc_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB23_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixunshfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: li a1, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_ui64:
@@ -2888,16 +2816,10 @@ define i64 @test_round_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB27_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixhfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: srai a1, a0, 31
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_si64:
@@ -2930,16 +2852,10 @@ define i64 @test_round_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB27_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixhfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: srai a1, a0, 31
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_si64:
@@ -3309,16 +3225,10 @@ define i64 @test_round_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB31_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixunshfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: li a1, 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_ui64:
@@ -3351,16 +3261,10 @@ define i64 @test_round_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB31_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixunshfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: li a1, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_ui64:
@@ -3730,16 +3634,10 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB35_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixhfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: srai a1, a0, 31
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_si64:
@@ -3772,16 +3670,10 @@ define i64 @test_roundeven_si64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB35_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixhfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: srai a1, a0, 31
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_si64:
@@ -4151,16 +4043,10 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
; RV32IZFHMIN-NEXT: .LBB39_2:
-; RV32IZFHMIN-NEXT: addi sp, sp, -16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
-; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; RV32IZFHMIN-NEXT: call __fixunshfdi
-; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT: .cfi_restore ra
-; RV32IZFHMIN-NEXT: addi sp, sp, 16
-; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: li a1, 0
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_ui64:
@@ -4193,16 +4079,10 @@ define i64 @test_roundeven_ui64(half %x) {
; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
; RV32IZHINXMIN-NEXT: .LBB39_2:
-; RV32IZHINXMIN-NEXT: addi sp, sp, -16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
-; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
-; RV32IZHINXMIN-NEXT: call __fixunshfdi
-; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT: .cfi_restore ra
-; RV32IZHINXMIN-NEXT: addi sp, sp, 16
-; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: li a1, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
>From 505d7a416b6f566693b1d82225fe9cc8ab1f9c1e Mon Sep 17 00:00:00 2001
From: Kane Wang <wangqiang1 at kylinos.cn>
Date: Fri, 11 Sep 2026 17:25:39 +0800
Subject: [PATCH 3/3] [RISCV][NFC] Fix code formating issue
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b3f6a00cff2e8..3e29ba2d23f03 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16387,9 +16387,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
return;
SDValue Cvt;
if (IsStrict) {
- Cvt = DAG.getNode(
- IsSigned ? ISD::STRICT_FP_TO_SINT : ISD::STRICT_FP_TO_UINT, DL,
- {MVT::i32, MVT::Other}, {N->getOperand(0), Op0});
+ Cvt = DAG.getNode(IsSigned ? ISD::STRICT_FP_TO_SINT
+ : ISD::STRICT_FP_TO_UINT,
+ DL, {MVT::i32, MVT::Other}, {N->getOperand(0), Op0});
} else {
Cvt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, DL,
MVT::i32, Op0);
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