[llvm] [RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 with Zfh (PR #222829)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 330f3195b..450d2e61a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16522,9 +16522,9 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
         return;
       SDValue Cvt;
       if (IsStrict) {
-        Cvt = DAG.getNode(
-            IsSigned ? ISD::STRICT_FP_TO_SINT : ISD::STRICT_FP_TO_UINT, DL,
-            {MVT::i32, MVT::Other}, {N->getOperand(0), Op0});
+        Cvt = DAG.getNode(IsSigned ? ISD::STRICT_FP_TO_SINT
+                                   : ISD::STRICT_FP_TO_UINT,
+                          DL, {MVT::i32, MVT::Other}, {N->getOperand(0), Op0});
       } else {
         Cvt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, DL,
                           MVT::i32, Op0);

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https://github.com/llvm/llvm-project/pull/222829