[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Simon Pilgrim via llvm-commits]

================
@@ -8837,6 +8837,43 @@ static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
   return SDValue();
 }
 
+// Fold an OR with a masked destination and a left-shifted
+// source into a shift + double-precision shift (SHRD):
+static SDValue combineOrOnSHLToSHRD(SDNode *N, SDLoc &DL, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
+
+  APInt Mask;
+  uint64_t ShiftAmount;
+  SDValue X, Y;
+
+  // Check for the following pattern:
+  //   (or (and X, HighBitsMask(C)), (srl Y, C))
+  // Do not combine if there are multi-use AND and OR.
+  // It does not result in more performant code.
+  if (!sd_match(N, m_Or(m_OneUse(m_And(m_Value(X), m_ConstInt(Mask))),
+                        m_OneUse(m_Shl(m_Value(Y), m_ConstInt(ShiftAmount))))))
+    return SDValue();
+
+  // Max bit-width of operands
+  uint64_t MaxMaskBitWidth = VT.getScalarSizeInBits();
+
+  // Check for Mask and ShiftAmount
+  //
+  // (shl Y, ShiftAmount) fills the top (MaxMaskBitWidth - ShiftAmount) bits,
+  // so X must keep exactly the low ShiftAmount.
+  APInt ExpectedMask = APInt::getLowBitsSet(MaxMaskBitWidth, ShiftAmount);
+
+  if (!((ShiftAmount > 0) && (ShiftAmount < MaxMaskBitWidth) &&
+        (Mask == ExpectedMask)))
+    return SDValue();
+
+  uint64_t InvShAmt = MaxMaskBitWidth - ShiftAmount;
----------------
RKSimon wrote:

```suggestion
  uint64_t InvShAmt = MaxMaskBitWidth - ShiftAmount.getZExtValue();
```

https://github.com/llvm/llvm-project/pull/220182