[llvm] [SystemZ] Expand and automate .insn directive coverage (PR #222031)

[Ulrich Weigand via llvm-commits]

================
@@ -1758,241 +1758,17 @@ class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 }
 
 //===----------------------------------------------------------------------===//
-// Instruction classes for .insn directives
+// Base class for all .insn directive instructions
 //===----------------------------------------------------------------------===//
-
-class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstE<0, outs, ins, asmstr, pattern> {
-  bits<16> enc;
-
-  let Inst = enc;
-}
-
-class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRIa<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-24} = enc{31-24};
-  let Inst{19-16} = enc{19-16};
-}
-
-class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRIEd<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
-}
-
-class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRILa<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-  string type;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{35-32} = enc{35-32};
-}
-
-class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRIS<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
-}
-
-class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRR<0, outs, ins, asmstr, pattern> {
-  bits<16> enc;
-
-  let Inst{15-8} = enc{15-8};
-}
-
-class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRRE<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRRFa<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-16} = enc{31-16};
-}
-
-class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRRS<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
-}
-
-class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRSa<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRSEa<6, outs, ins, asmstr, pattern> {
-  bits <48> enc;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
-}
-
-class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRSI<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRSYa<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
-}
-
-class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRXa<0, outs, ins, asmstr, pattern> {
-  bits<32> enc;
-
-  let Inst{31-24} = enc{31-24};
-}
-
-class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : InstRXE<0, outs, ins, asmstr, pattern> {
-  bits<48> enc;
-
-  let M3 = 0;
-
-  let Inst{47-40} = enc{47-40};
-  let Inst{7-0}   = enc{7-0};
+// This marker class is used to identify .insn directive instructions
+// for the SystemZInsnDirectiveEmitter. It must be the rightmost parent
+// in the inheritance list to ensure these properties take precedence over
+// the ones set by the InstFoo base classes.
+class InsnDirectiveBase {
----------------
uweigand wrote:

This is an interesting trick, but it seems a bit wordy to use.   Could we instead add a new field like `IsInsnDirective`  to `InstSystemZ`, defaulting to 0, and then just place all the directives inside a single

```
let IsInsnDirective =1, isCodeGenOnly = 1, hasSideEffects = 1 in {
...
}
```

block?   TableGen would then have to find all records derived from `InstSystemZ` where this field is 1.

https://github.com/llvm/llvm-project/pull/222031