[llvm] [SystemZ] Expand and automate .insn directive coverage (PR #222031)
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 10 05:59:35 PDT 2026
================
@@ -2275,121 +2275,879 @@ let hasSideEffects = 1 in {
// .insn directive instructions
//===----------------------------------------------------------------------===//
-let isCodeGenOnly = 1, hasSideEffects = 1 in {
- def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
- def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- imm32sx16:$I2),
- ".insn ri,$enc,$R1,$I2", []>;
- def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, brtarget16:$I2),
- ".insn rie,$enc,$R1,$R3,$I2", []>;
- def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- brtarget32:$I2),
- ".insn ril,$enc,$R1,$I2", []>;
- def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- uimm32:$I2),
- ".insn rilu,$enc,$R1,$I2", []>;
- def InsnRIS : DirectiveInsnRIS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- imm32sx8:$I2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>;
- def InsnRR : DirectiveInsnRR<(outs),
- (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2),
- ".insn rr,$enc,$R1,$R2", []>;
- def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc,
- AnyReg:$R1, AnyReg:$R2),
- ".insn rre,$enc,$R1,$R2", []>;
- def InsnRRF : DirectiveInsnRRF<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- AnyReg:$R3, imm32zx4:$M4),
- ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
- def InsnRRS : DirectiveInsnRRS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R2, imm32zx4:$M3,
- (bdaddr12only $B4, $D4):$BD4),
- ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>;
- def InsnRS : DirectiveInsnRS<(outs),
- (ins imm64zx32:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
- ".insn rs,$enc,$R1,$R3,$BD2", []>;
- def InsnRSE : DirectiveInsnRSE<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2),
- ".insn rse,$enc,$R1,$R3,$BD2", []>;
- def InsnRSI : DirectiveInsnRSI<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, brtarget16:$RI2),
- ".insn rsi,$enc,$R1,$R3,$RI2", []>;
- def InsnRSY : DirectiveInsnRSY<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2),
- ".insn rsy,$enc,$R1,$R3,$BD2", []>;
- def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rx,$enc,$R1,$XBD2", []>;
- def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxe,$enc,$R1,$XBD2", []>;
- def InsnRXF : DirectiveInsnRXF<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1,
- AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
- ".insn rxf,$enc,$R1,$R3,$XBD2", []>;
- def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
- (bdxaddr20only $B2, $D2, $X2):$XBD2),
- ".insn rxy,$enc,$R1,$XBD2", []>;
- def InsnS : DirectiveInsnS<(outs),
- (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2),
- ".insn s,$enc,$BD2", []>;
- def InsnSI : DirectiveInsnSI<(outs),
- (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1,
- imm32sx8:$I2),
- ".insn si,$enc,$BD1,$I2", []>;
- def InsnSIY : DirectiveInsnSIY<(outs),
- (ins imm64zx48:$enc,
- (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2),
- ".insn siy,$enc,$BD1,$I2", []>;
- def InsnSIL : DirectiveInsnSIL<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- imm32zx16:$I2),
- ".insn sil,$enc,$BD1,$I2", []>;
- def InsnSS : DirectiveInsnSS<(outs),
- (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ss,$enc,$RBD1,$BD2,$R3", []>;
- def InsnSSE : DirectiveInsnSSE<(outs),
- (ins imm64zx48:$enc,
- (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2),
- ".insn sse,$enc,$BD1,$BD2", []>;
- def InsnSSF : DirectiveInsnSSF<(outs),
- (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1,
- (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3),
- ".insn ssf,$enc,$BD1,$BD2,$R3", []>;
- def InsnVRI : DirectiveInsnVRI<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
- ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>;
- def InsnVRR : DirectiveInsnVRR<(outs),
- (ins imm64zx48:$enc, VR128:$V1, VR128:$V2,
- VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
- imm32zx4:$M6),
- ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>;
- def InsnVRS : DirectiveInsnVRS<(outs),
- (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3,
- (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
- ".insn vrs,$enc,$BD2,$M4", []>;
- def InsnVRV : DirectiveInsnVRV<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3),
- ".insn vrv,$enc,$V1,$VBD2,$M3", []>;
- def InsnVRX : DirectiveInsnVRX<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
- ".insn vrx,$enc,$V1,$XBD2,$M3", []>;
- def InsnVSI : DirectiveInsnVSI<(outs),
- (ins imm64zx48:$enc, VR128:$V1,
- (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
- ".insn vsi,$enc,$V1,$BD2,$I3", []>;
+def InsnE : InstE<0, (outs), (ins imm64zx16:$enc), ".insn e,$enc", []>,
+ InsnDirectiveBase {
+ bits<16> enc;
+ let Inst = enc;
+}
+def InsnI : InstI<0, (outs), (ins imm64zx16:$enc, imm32zx8:$I1),
+ ".insn i,$enc,$I1", []>,
+ InsnDirectiveBase {
+ bits<16> enc;
+ let Inst{15-8} = enc{15-8};
----------------
uweigand wrote:
Having all this encoding stuff here is a bit unfortunate; separating that out was the main reason for having the Directive... classes in the first place.
Maybe there is a way to move the encoding handling all the way into the main Inst... class. We could likely extend those to get the opcode bits *either* from an immediate `op` operand *or* from the `enc` pattern field (if `op` is zero).
I'm thinking of something along the lines of (for example):
```
class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<2, outs, ins, asmstr, pattern> {
field bits<16> Inst;
bits<16> enc;
bits<4> R1;
bits<4> R2;
let Inst{15-8} = !if(!ne(op, 0), op, enc{15-8});
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
```
This makes the Inst... classes a bit more verbose, but keeps all the opcode encoding in one place and makes it obvious what to do to add new formats in the future.
https://github.com/llvm/llvm-project/pull/222031
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