[llvm] [AArch64] Enable CMP+CSEL fusion under Generic (PR #222280)
Shanzhi Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 20:48:34 PDT 2026
https://github.com/chenshanzhi updated https://github.com/llvm/llvm-project/pull/222280
>From 2ba085a2381dd4284a810a6ac91a465ddc5299b9 Mon Sep 17 00:00:00 2001
From: Shanzhi Chen <chenshanzhi at huawei.com>
Date: Wed, 9 Sep 2026 16:56:58 +0800
Subject: [PATCH 1/3] [AArch64] Enable CMP+CSEL fusion under Generic
Enable FeatureFuseCmpCSel under Generic, as many modern cores support
this fusion and it has minimal performance impact on cores that do not
support it.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index f996522ba4d09..5eae632c3b03b 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1287,10 +1287,13 @@ def ProcessorFeatures {
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations. We use a fixed load latency of 4 as the a510 scheduling model
// has a latency of 2 for most loads which is disproportionately low for many
-// cpus.
+// cpus. FeatureFuseCmpCSel is enabled under Generic, as many modern cores
+// support this fusion and it has minimal performance impact on cores that do
+// not support it.
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
[FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
- FeatureEnableSelectOptimize, FeatureFixedLoadLatency4]>;
+ FeatureEnableSelectOptimize, FeatureFixedLoadLatency4,
+ FeatureFuseCmpCSel]>;
def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
[TuneA35]>;
def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
>From d6e76b23e484c78a51cbec6b8aec303ddc4d35cb Mon Sep 17 00:00:00 2001
From: Shanzhi Chen <chenshanzhi at huawei.com>
Date: Thu, 10 Sep 2026 10:55:24 +0800
Subject: [PATCH 2/3] Update tests
---
.../GlobalISel/split-wide-shifts-multiway.ll | 3081 ++++++++---------
llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll | 8 +-
llvm/test/CodeGen/AArch64/active_lane_mask.ll | 2 +-
llvm/test/CodeGen/AArch64/addsub.ll | 102 +-
llvm/test/CodeGen/AArch64/andandshift.ll | 8 +-
llvm/test/CodeGen/AArch64/arm64-csel.ll | 6 +-
llvm/test/CodeGen/AArch64/arm64-fp128.ll | 37 +-
.../AArch64/arm64-indexed-vector-ldst.ll | 4 +-
llvm/test/CodeGen/AArch64/arm64-xaluo.ll | 66 +-
.../test/CodeGen/AArch64/bf16-instructions.ll | 28 +-
llvm/test/CodeGen/AArch64/bitcnt-i256.ll | 152 +-
.../AArch64/bool-vector-bitcast-compare.ll | 12 +-
.../CodeGen/AArch64/branch-relax-alignment.ll | 4 +-
llvm/test/CodeGen/AArch64/csel-cmp-cse.ll | 48 +-
.../test/CodeGen/AArch64/csel-subs-swapped.ll | 12 +-
llvm/test/CodeGen/AArch64/ctlz.ll | 90 +-
.../AArch64/cttz-of-bool-vector-bitcast.ll | 8 +-
llvm/test/CodeGen/AArch64/cttz.ll | 80 +-
.../CodeGen/AArch64/dag-combine-select.ll | 2 +-
llvm/test/CodeGen/AArch64/div-i256.ll | 520 +--
llvm/test/CodeGen/AArch64/fcvt-i256.ll | 400 +--
.../CodeGen/AArch64/fold-csel-cttz-and.ll | 8 +-
llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll | 14 +-
llvm/test/CodeGen/AArch64/fpclamptosat.ll | 24 +-
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 164 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 100 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 666 ++--
.../test/CodeGen/AArch64/fptoui-sat-scalar.ll | 50 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 220 +-
llvm/test/CodeGen/AArch64/fsh.ll | 528 +--
llvm/test/CodeGen/AArch64/funnel-shift.ll | 62 +-
llvm/test/CodeGen/AArch64/gpr_cttz.ll | 6 +-
.../insert-subvector-res-legalization.ll | 48 +-
.../AArch64/intrinsic-cttz-elts-sve.ll | 10 +-
llvm/test/CodeGen/AArch64/itofp-bf16.ll | 102 +-
.../AArch64/machine_cse_impdef_killflags.ll | 6 +-
.../AArch64/named-vector-shuffles-neon.ll | 2 +-
.../AArch64/named-vector-shuffles-sve.ll | 16 +-
llvm/test/CodeGen/AArch64/overflow-vec.ll | 1168 +++----
llvm/test/CodeGen/AArch64/sadd_sat.ll | 44 +-
llvm/test/CodeGen/AArch64/sadd_sat_plus.ll | 22 +-
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 20 +-
llvm/test/CodeGen/AArch64/sat-add.ll | 2 +-
llvm/test/CodeGen/AArch64/sbc.ll | 4 +-
llvm/test/CodeGen/AArch64/sdivpow2.ll | 4 +-
llvm/test/CodeGen/AArch64/select_const.ll | 2 +-
llvm/test/CodeGen/AArch64/shift.ll | 48 +-
llvm/test/CodeGen/AArch64/smul_fix_sat.ll | 180 +-
.../CodeGen/AArch64/split-vector-insert.ll | 56 +-
.../CodeGen/AArch64/srem-seteq-optsize.ll | 12 +-
llvm/test/CodeGen/AArch64/ssub_sat.ll | 44 +-
llvm/test/CodeGen/AArch64/ssub_sat_plus.ll | 22 +-
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 20 +-
.../sve-extract-fixed-from-scalable-vector.ll | 4 +-
.../CodeGen/AArch64/sve-insert-element.ll | 2 +-
.../CodeGen/AArch64/sve-mask-partition.ll | 84 +-
.../CodeGen/AArch64/sve-split-extract-elt.ll | 8 +-
.../CodeGen/AArch64/sve-split-insert-elt.ll | 4 +-
...-streaming-mode-fixed-length-int-reduce.ll | 816 ++---
...streaming-mode-fixed-length-int-vselect.ll | 321 +-
...mode-fixed-length-masked-gather-scatter.ll | 26 +-
.../sve-streaming-mode-fixed-length-ptest.ll | 4 +-
.../CodeGen/AArch64/sve-vector-compress.ll | 4 +-
.../CodeGen/AArch64/typepromotion-overflow.ll | 48 +-
llvm/test/CodeGen/AArch64/uadd_sat.ll | 10 +-
llvm/test/CodeGen/AArch64/uadd_sat_plus.ll | 8 +-
.../umin-sub-to-usubo-select-combine.ll | 4 +-
llvm/test/CodeGen/AArch64/umul_fix_sat.ll | 26 +-
.../CodeGen/AArch64/urem-seteq-optsize.ll | 12 +-
.../AArch64/vecreduce-umax-legalization.ll | 28 +-
llvm/test/CodeGen/AArch64/vector-compress.ll | 169 +-
.../AArch64/vector-extract-last-active.ll | 2 +-
.../CodeGen/AArch64/vselect-masked-shift.ll | 4 +-
73 files changed, 4915 insertions(+), 5013 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll b/llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
index ce1dae3cdfeff..e420f894958bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
@@ -85,40 +85,40 @@ define void @test_shl_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: .cfi_offset w26, -64
; GISEL-NEXT: .cfi_offset w27, -72
; GISEL-NEXT: .cfi_offset w28, -80
-; GISEL-NEXT: ldp x11, x15, [x1]
+; GISEL-NEXT: ldp x12, x15, [x1]
; GISEL-NEXT: mov w8, w2
; GISEL-NEXT: lsr x9, x8, #6
; GISEL-NEXT: and x14, x8, #0x3f
; GISEL-NEXT: mov w13, #64 ; =0x40
; GISEL-NEXT: sub x16, x13, x14
; GISEL-NEXT: ldp x3, x6, [x1, #16]
-; GISEL-NEXT: lsl x10, x11, x14
+; GISEL-NEXT: lsl x10, x12, x14
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: ldp x20, x21, [x1, #32]
-; GISEL-NEXT: csel x12, x10, xzr, eq
+; GISEL-NEXT: ldp x20, x22, [x1, #32]
+; GISEL-NEXT: csel x11, x10, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: lsr x26, x21, x16
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: lsr x26, x22, x16
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: csel x13, xzr, x12, eq
+; GISEL-NEXT: csel x13, xzr, x11, eq
+; GISEL-NEXT: lsr x11, x12, x16
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsr x12, x11, x16
-; GISEL-NEXT: csel x13, x11, x13, eq
-; GISEL-NEXT: lsl x11, x15, x14
+; GISEL-NEXT: csel x13, x12, x13, eq
+; GISEL-NEXT: lsl x12, x15, x14
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x17, xzr, x12, eq
+; GISEL-NEXT: csel x17, xzr, x11, eq
+; GISEL-NEXT: orr x17, x12, x17
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x17, x11, x17
; GISEL-NEXT: csel x17, x17, xzr, eq
; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x17, x10, x17, eq
@@ -134,19 +134,19 @@ define void @test_shl_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x17, xzr, x17, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x2, xzr, x17, eq
-; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: lsr x17, x15, x16
+; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x15, x15, x2, eq
; GISEL-NEXT: lsl x2, x3, x14
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x4, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: orr x4, x2, x4
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x4, x4, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x5, xzr, x12, eq
+; GISEL-NEXT: csel x5, xzr, x11, eq
+; GISEL-NEXT: orr x5, x12, x5
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x5, x11, x5
; GISEL-NEXT: csel x4, x5, x4, eq
; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x4, x10, x4, eq
@@ -160,24 +160,24 @@ define void @test_shl_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x4, xzr, x4, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x5, xzr, x4, eq
-; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: lsr x4, x3, x16
+; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x3, x3, x5, eq
; GISEL-NEXT: lsl x5, x6, x14
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x7, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: orr x7, x5, x7
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x7, x7, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x19, x2, x19
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x7, x19, x7, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: csel x19, xzr, x11, eq
+; GISEL-NEXT: orr x19, x12, x19
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x19, x11, x19
; GISEL-NEXT: csel x7, x19, x7, eq
; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x7, x10, x7, eq
@@ -189,111 +189,111 @@ define void @test_shl_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x7, xzr, x7, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x19, xzr, x7, eq
-; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: lsr x7, x6, x16
+; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x6, x6, x19, eq
; GISEL-NEXT: lsl x19, x20, x14
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x22, xzr, x7, eq
+; GISEL-NEXT: csel x21, xzr, x7, eq
+; GISEL-NEXT: orr x21, x19, x21
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x22, x19, x22
-; GISEL-NEXT: csel x22, x22, xzr, eq
+; GISEL-NEXT: csel x21, x21, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x23, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x23, x5, x23
-; GISEL-NEXT: csel x22, x23, x22, eq
+; GISEL-NEXT: cmp x9, #1
+; GISEL-NEXT: csel x21, x23, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x23, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x23, x2, x23
-; GISEL-NEXT: csel x22, x23, x22, eq
+; GISEL-NEXT: cmp x9, #2
+; GISEL-NEXT: csel x21, x23, x21, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x23, xzr, x12, eq
+; GISEL-NEXT: csel x23, xzr, x11, eq
+; GISEL-NEXT: orr x23, x12, x23
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x23, x11, x23
-; GISEL-NEXT: csel x22, x23, x22, eq
+; GISEL-NEXT: csel x21, x23, x21, eq
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: csel x22, x10, x22, eq
+; GISEL-NEXT: csel x21, x10, x21, eq
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: csel x22, xzr, x22, eq
+; GISEL-NEXT: csel x21, xzr, x21, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: csel x22, xzr, x22, eq
+; GISEL-NEXT: csel x21, xzr, x21, eq
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: csel x23, xzr, x22, eq
+; GISEL-NEXT: csel x23, xzr, x21, eq
+; GISEL-NEXT: lsr x21, x20, x16
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsr x22, x20, x16
; GISEL-NEXT: csel x20, x20, x23, eq
-; GISEL-NEXT: lsl x23, x21, x14
+; GISEL-NEXT: lsl x23, x22, x14
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x24, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: csel x24, xzr, x21, eq
; GISEL-NEXT: orr x24, x23, x24
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x24, x24, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x25, xzr, x7, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x25, x19, x25
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x24, x25, x24, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x25, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x25, x5, x25
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x24, x25, x24, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x25, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: orr x25, x2, x25
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x24, x25, x24, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x25, xzr, x12, eq
+; GISEL-NEXT: csel x25, xzr, x11, eq
+; GISEL-NEXT: orr x25, x12, x25
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x25, x11, x25
; GISEL-NEXT: csel x24, x25, x24, eq
; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x24, x10, x24, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: ldp x25, x1, [x1, #48]
; GISEL-NEXT: csel x24, xzr, x24, eq
+; GISEL-NEXT: ldp x25, x1, [x1, #48]
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: stp x13, x15, [x0]
; GISEL-NEXT: csel x24, xzr, x24, eq
+; GISEL-NEXT: stp x13, x15, [x0]
; GISEL-NEXT: cmp x8, #0
+; GISEL-NEXT: csel x22, x22, x24, eq
; GISEL-NEXT: stp x3, x6, [x0, #16]
-; GISEL-NEXT: csel x21, x21, x24, eq
; GISEL-NEXT: lsl x24, x25, x14
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x27, xzr, x26, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: lsr x16, x25, x16
-; GISEL-NEXT: orr x27, x24, x27
+; GISEL-NEXT: csel x27, xzr, x26, eq
; GISEL-NEXT: lsl x14, x1, x14
-; GISEL-NEXT: stp x20, x21, [x0, #32]
+; GISEL-NEXT: stp x20, x22, [x0, #32]
+; GISEL-NEXT: orr x27, x24, x27
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x27, x27, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x28, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #1
+; GISEL-NEXT: csel x28, xzr, x21, eq
; GISEL-NEXT: orr x28, x23, x28
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x28, xzr, x7, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x28, x19, x28
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x28, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: orr x28, x5, x28
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x28, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: orr x28, x2, x28
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x28, xzr, x12, eq
+; GISEL-NEXT: csel x28, xzr, x11, eq
+; GISEL-NEXT: orr x28, x12, x28
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x28, x11, x28
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: csel x27, x10, x27, eq
@@ -303,41 +303,41 @@ define void @test_shl_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x25, x25, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x16, xzr, x16, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: orr x14, x14, x16
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x14, x14, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x16, xzr, x26, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x16, x24, x16
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x14, x16, x14, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x16, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x16, x23, x16
+; GISEL-NEXT: csel x16, xzr, x21, eq
; GISEL-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x16, x23, x16
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x14, x16, x14, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x16, xzr, x7, eq
-; GISEL-NEXT: cmp x9, #3
+; GISEL-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
; GISEL-NEXT: orr x16, x19, x16
-; GISEL-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x14, x16, x14, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x16, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #4
+; GISEL-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
; GISEL-NEXT: orr x16, x5, x16
-; GISEL-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x14, x16, x14, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x16, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: orr x16, x2, x16
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x13, x16, x14, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x12, x11
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x11, x11, x12
; GISEL-NEXT: csel x11, x11, x13, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x9, x10, x11, eq
@@ -437,131 +437,131 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: mov w8, w2
; GISEL-NEXT: ldp x13, x2, [x1]
; GISEL-NEXT: mov w9, #64 ; =0x40
-; GISEL-NEXT: and x14, x8, #0x3f
+; GISEL-NEXT: and x15, x8, #0x3f
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: sub x17, x9, x14
+; GISEL-NEXT: sub x17, x9, x15
; GISEL-NEXT: ldp x5, x16, [x1, #16]
; GISEL-NEXT: lsl x10, x2, x17
; GISEL-NEXT: lsr x9, x8, #6
-; GISEL-NEXT: lsr x11, x13, x14
-; GISEL-NEXT: lsr x24, x2, x14
+; GISEL-NEXT: lsr x11, x13, x15
+; GISEL-NEXT: lsr x24, x2, x15
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: lsl x23, x5, x17
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x10, x11, x10
; GISEL-NEXT: lsl x22, x16, x17
-; GISEL-NEXT: lsr x21, x5, x14
+; GISEL-NEXT: orr x10, x11, x10
+; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: lsr x21, x5, x15
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x20, x16, x14
+; GISEL-NEXT: lsr x20, x16, x15
; GISEL-NEXT: csel x11, xzr, x23, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x11, x24, x11
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldp x15, x11, [x1, #32]
+; GISEL-NEXT: ldp x14, x11, [x1, #32]
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x12, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: lsl x19, x15, x17
+; GISEL-NEXT: lsl x19, x14, x17
; GISEL-NEXT: orr x12, x21, x12
-; GISEL-NEXT: lsl x6, x11, x17
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x7, x15, x14
+; GISEL-NEXT: lsl x6, x11, x17
; GISEL-NEXT: csel x12, xzr, x19, eq
-; GISEL-NEXT: cmp x9, #3
+; GISEL-NEXT: lsr x7, x14, x15
; GISEL-NEXT: orr x12, x20, x12
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x4, x12, x10, eq
; GISEL-NEXT: ldp x12, x10, [x1, #48]
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x6, eq
-; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: orr x1, x7, x1
; GISEL-NEXT: lsl x3, x12, x17
-; GISEL-NEXT: lsl x17, x10, x17
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x1, x1, x4, eq
-; GISEL-NEXT: lsr x4, x11, x14
+; GISEL-NEXT: lsr x4, x11, x15
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x25, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #5
+; GISEL-NEXT: lsl x17, x10, x17
; GISEL-NEXT: orr x25, x4, x25
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x25, x25, x1, eq
-; GISEL-NEXT: lsr x1, x12, x14
+; GISEL-NEXT: lsr x1, x12, x15
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: lsr x14, x10, x14
+; GISEL-NEXT: lsr x15, x10, x15
; GISEL-NEXT: orr x26, x1, x26
+; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: csel x25, x14, x25, eq
+; GISEL-NEXT: csel x25, x15, x25, eq
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x13, x13, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x23, xzr, x23, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: orr x23, x24, x23
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x23, x23, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x24, x21, x24
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x19, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x24, x20, x24
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x6, eq
-; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: orr x24, x7, x24
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: orr x24, x4, x24
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: orr x24, x1, x24
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: csel x23, x14, x23, eq
+; GISEL-NEXT: csel x23, x15, x23, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x23, xzr, x23, eq
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x2, x2, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x22, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: stp x13, x2, [x0]
; GISEL-NEXT: orr x21, x21, x22
-; GISEL-NEXT: ldp x24, x23, [sp, #16] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x21, x21, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x19, eq
-; GISEL-NEXT: cmp x9, #1
+; GISEL-NEXT: ldp x24, x23, [sp, #16] ; 16-byte Folded Reload
; GISEL-NEXT: orr x22, x20, x22
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x6, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x22, x7, x22
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: orr x22, x4, x22
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: orr x22, x1, x22
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: csel x21, x14, x21, eq
+; GISEL-NEXT: csel x21, x15, x21, eq
; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: csel x21, xzr, x21, eq
; GISEL-NEXT: cmp x9, #7
@@ -570,27 +570,27 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x5, x5, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x19, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x19, x20, x19
; GISEL-NEXT: ldp x22, x21, [sp, #32] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x19, x20, x19
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x19, x19, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x6, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x20, x7, x20
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x20, x4, x20
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: orr x20, x1, x20
+; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: csel x19, x14, x19, eq
+; GISEL-NEXT: csel x19, x15, x19, eq
; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x19, xzr, x19, eq
; GISEL-NEXT: cmp x9, #6
@@ -601,23 +601,23 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x16, x16, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x6, xzr, x6, eq
+; GISEL-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x6, x7, x6
; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: stp x5, x16, [x0, #16]
-; GISEL-NEXT: orr x6, x7, x6
-; GISEL-NEXT: ldp x20, x19, [sp, #48] ; 16-byte Folded Reload
; GISEL-NEXT: csel x6, x6, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x7, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x7, x4, x7
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x6, x7, x6, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x7, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: orr x7, x1, x7
+; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x6, x7, x6, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: csel x6, x14, x6, eq
+; GISEL-NEXT: csel x6, x15, x6, eq
; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x6, xzr, x6, eq
; GISEL-NEXT: cmp x9, #5
@@ -627,19 +627,19 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x6, xzr, x6, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x15, x15, x6, eq
+; GISEL-NEXT: csel x14, x14, x6, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x3, xzr, x3, eq
-; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: orr x3, x4, x3
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x3, x3, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x4, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: orr x4, x1, x4
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x3, x4, x3, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: csel x3, x14, x3, eq
+; GISEL-NEXT: csel x3, x15, x3, eq
; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x3, xzr, x3, eq
; GISEL-NEXT: cmp x9, #4
@@ -654,12 +654,12 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x11, x11, x3, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x17, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: stp x15, x11, [x0, #32]
+; GISEL-NEXT: stp x14, x11, [x0, #32]
; GISEL-NEXT: orr x17, x1, x17
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x17, x17, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: csel x17, x14, x17, eq
+; GISEL-NEXT: csel x17, x15, x17, eq
; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x17, xzr, x17, eq
; GISEL-NEXT: cmp x9, #3
@@ -675,13 +675,13 @@ define void @test_lshr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x12, x12, x17, eq
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: csel x14, x14, xzr, eq
+; GISEL-NEXT: csel x15, x15, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: csel x15, xzr, x15, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: csel x15, xzr, x15, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x15, eq
; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x13, xzr, x13, eq
; GISEL-NEXT: cmp x9, #5
@@ -794,100 +794,100 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: ldr x9, [x1, #56]
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: lsl x12, x4, x15
-; GISEL-NEXT: ldp x7, x3, [x1, #16]
+; GISEL-NEXT: ldp x7, x2, [x1, #16]
; GISEL-NEXT: lsr x13, x14, x16
; GISEL-NEXT: asr x11, x9, #63
; GISEL-NEXT: lsr x26, x4, x16
; GISEL-NEXT: csel x12, xzr, x12, eq
-; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: lsl x25, x7, x15
; GISEL-NEXT: orr x12, x13, x12
-; GISEL-NEXT: lsl x23, x3, x15
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x24, x7, x16
+; GISEL-NEXT: lsl x23, x2, x15
; GISEL-NEXT: csel x13, xzr, x25, eq
-; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: lsr x22, x3, x16
+; GISEL-NEXT: lsr x24, x7, x16
+; GISEL-NEXT: lsr x22, x2, x16
; GISEL-NEXT: orr x13, x26, x13
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: ldp x17, x13, [x1, #32]
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x2, xzr, x23, eq
-; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x2, x24, x2
+; GISEL-NEXT: csel x3, xzr, x23, eq
+; GISEL-NEXT: orr x3, x24, x3
; GISEL-NEXT: lsl x21, x17, x15
-; GISEL-NEXT: lsl x19, x13, x15
-; GISEL-NEXT: csel x2, x2, x12, eq
+; GISEL-NEXT: cmp x10, #2
+; GISEL-NEXT: csel x3, x3, x12, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: ldr x12, [x1, #48]
; GISEL-NEXT: csel x1, xzr, x21, eq
-; GISEL-NEXT: cmp x10, #3
+; GISEL-NEXT: lsl x19, x13, x15
; GISEL-NEXT: lsr x20, x17, x16
; GISEL-NEXT: orr x1, x22, x1
+; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: lsl x5, x12, x15
-; GISEL-NEXT: lsr x6, x13, x16
-; GISEL-NEXT: csel x1, x1, x2, eq
+; GISEL-NEXT: csel x1, x1, x3, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x2, xzr, x19, eq
+; GISEL-NEXT: lsr x6, x13, x16
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: orr x3, x20, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x2, x20, x2
-; GISEL-NEXT: csel x2, x2, x1, eq
+; GISEL-NEXT: csel x3, x3, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #5
; GISEL-NEXT: orr x27, x6, x1
; GISEL-NEXT: lsl x1, x9, x15
-; GISEL-NEXT: lsl x15, x11, x15
-; GISEL-NEXT: csel x27, x27, x2, eq
-; GISEL-NEXT: lsr x2, x12, x16
+; GISEL-NEXT: cmp x10, #5
+; GISEL-NEXT: csel x27, x27, x3, eq
+; GISEL-NEXT: lsr x3, x12, x16
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x28, xzr, x1, eq
-; GISEL-NEXT: cmp x10, #6
+; GISEL-NEXT: lsl x15, x11, x15
; GISEL-NEXT: lsr x16, x9, x16
-; GISEL-NEXT: orr x28, x2, x28
+; GISEL-NEXT: orr x28, x3, x28
+; GISEL-NEXT: cmp x10, #6
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x28, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: orr x28, x16, x28
+; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: csel x27, x28, x27, eq
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x14, x14, x27, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x25, xzr, x25, eq
-; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: orr x25, x26, x25
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x25, x25, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x23, eq
-; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: orr x26, x24, x26
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x21, eq
-; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: orr x26, x22, x26
+; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x19, eq
-; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: orr x26, x20, x26
+; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #4
; GISEL-NEXT: orr x26, x6, x26
+; GISEL-NEXT: cmp x10, #4
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x1, eq
+; GISEL-NEXT: orr x26, x3, x26
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x26, x2, x26
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x26, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #6
; GISEL-NEXT: orr x26, x16, x26
+; GISEL-NEXT: cmp x10, #6
; GISEL-NEXT: csel x25, x26, x25, eq
; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: csel x25, x11, x25, eq
@@ -895,35 +895,35 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x4, x4, x25, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x23, xzr, x23, eq
-; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: stp x14, x4, [x0]
; GISEL-NEXT: orr x23, x24, x23
-; GISEL-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x23, x23, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x21, eq
-; GISEL-NEXT: cmp x10, #1
+; GISEL-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
; GISEL-NEXT: orr x24, x22, x24
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x19, eq
-; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: orr x24, x20, x24
+; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: orr x24, x6, x24
+; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x1, eq
+; GISEL-NEXT: orr x24, x3, x24
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x24, x2, x24
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x24, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #5
; GISEL-NEXT: orr x24, x16, x24
+; GISEL-NEXT: cmp x10, #5
; GISEL-NEXT: csel x23, x24, x23, eq
; GISEL-NEXT: cmp x10, #6
; GISEL-NEXT: csel x23, x11, x23, eq
@@ -933,29 +933,29 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x7, x7, x23, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x21, xzr, x21, eq
-; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x21, x22, x21
; GISEL-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x21, x22, x21
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x21, x21, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x19, eq
-; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: orr x22, x20, x22
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: orr x22, x6, x22
+; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x1, eq
+; GISEL-NEXT: orr x22, x3, x22
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x22, x2, x22
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x22, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #4
; GISEL-NEXT: orr x22, x16, x22
+; GISEL-NEXT: cmp x10, #4
; GISEL-NEXT: csel x21, x22, x21, eq
; GISEL-NEXT: cmp x10, #5
; GISEL-NEXT: csel x21, x11, x21, eq
@@ -964,28 +964,28 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: csel x21, x11, x21, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x3, x3, x21, eq
+; GISEL-NEXT: csel x2, x2, x21, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x19, eq
-; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: stp x7, x3, [x0, #16]
-; GISEL-NEXT: orr x19, x20, x19
; GISEL-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x19, x20, x19
+; GISEL-NEXT: cmp x10, #0
+; GISEL-NEXT: stp x7, x2, [x0, #16]
; GISEL-NEXT: csel x19, x19, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: orr x20, x6, x20
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x1, eq
+; GISEL-NEXT: orr x20, x3, x20
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x20, x2, x20
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x20, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: orr x20, x16, x20
+; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: csel x19, x20, x19, eq
; GISEL-NEXT: cmp x10, #4
; GISEL-NEXT: csel x19, x11, x19, eq
@@ -999,19 +999,19 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x17, x17, x19, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x5, xzr, x5, eq
-; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x5, x6, x5
; GISEL-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x5, x6, x5
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x5, x5, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x6, xzr, x1, eq
+; GISEL-NEXT: orr x6, x3, x6
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x6, x2, x6
; GISEL-NEXT: csel x5, x6, x5, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x6, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: orr x6, x16, x6
+; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x5, x6, x5, eq
; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: csel x5, x11, x5, eq
@@ -1027,15 +1027,15 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x13, x13, x5, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x1, eq
-; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: stp x17, x13, [x0, #32]
-; GISEL-NEXT: orr x1, x2, x1
+; GISEL-NEXT: orr x1, x3, x1
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x1, x1, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x2, xzr, x15, eq
+; GISEL-NEXT: csel x3, xzr, x15, eq
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x2, x16, x2
-; GISEL-NEXT: csel x1, x2, x1, eq
+; GISEL-NEXT: csel x1, x3, x1, eq
; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x1, x11, x1, eq
; GISEL-NEXT: cmp x10, #3
@@ -1052,8 +1052,8 @@ define void @test_ashr_i512(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x12, x12, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x15, xzr, x15, eq
-; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: orr x15, x16, x15
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x15, x15, x11, eq
; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x15, x11, x15, eq
@@ -1219,14 +1219,14 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
;
; GISEL-LABEL: test_shl_i1024:
; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: sub sp, sp, #448
-; GISEL-NEXT: stp x28, x27, [sp, #352] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x26, x25, [sp, #368] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x24, x23, [sp, #384] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x22, x21, [sp, #400] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x20, x19, [sp, #416] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x29, x30, [sp, #432] ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 448
+; GISEL-NEXT: sub sp, sp, #384
+; GISEL-NEXT: stp x28, x27, [sp, #288] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x26, x25, [sp, #304] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x24, x23, [sp, #320] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x22, x21, [sp, #336] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x20, x19, [sp, #352] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x29, x30, [sp, #368] ; 16-byte Folded Spill
+; GISEL-NEXT: .cfi_def_cfa_offset 384
; GISEL-NEXT: .cfi_offset w30, -8
; GISEL-NEXT: .cfi_offset w29, -16
; GISEL-NEXT: .cfi_offset w19, -24
@@ -1245,53 +1245,42 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: and x12, x8, #0x3f
; GISEL-NEXT: and x14, x8, #0x3f
; GISEL-NEXT: mov w13, #64 ; =0x40
-; GISEL-NEXT: mov x6, x1
-; GISEL-NEXT: str x0, [sp, #176] ; 8-byte Spill
-; GISEL-NEXT: lsl x28, x10, x12
+; GISEL-NEXT: and x16, x8, #0x3f
+; GISEL-NEXT: str x0, [sp, #136] ; 8-byte Spill
+; GISEL-NEXT: lsl x26, x10, x12
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: sub x1, x13, x14
-; GISEL-NEXT: lsr x0, x10, x1
+; GISEL-NEXT: sub x27, x13, x14
+; GISEL-NEXT: lsr x23, x10, x27
; GISEL-NEXT: lsl x3, x11, x14
-; GISEL-NEXT: and x14, x8, #0x3f
-; GISEL-NEXT: csel x12, x28, xzr, eq
+; GISEL-NEXT: lsr x14, x11, x27
+; GISEL-NEXT: csel x12, x26, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: lsr x5, x11, x1
+; GISEL-NEXT: str x1, [sp, #280] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: and x16, x8, #0x3f
+; GISEL-NEXT: mov x2, x3
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: mov x2, x0
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: mov x21, x3
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x7, x5
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: mov x23, x6
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: and x30, x8, #0x3f
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: mov x27, x1
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: mov x22, x21
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: mov x20, x7
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: str x7, [sp, #24] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: str x23, [sp, #336] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: str x2, [sp, #320] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #14
; GISEL-NEXT: csel x12, xzr, x12, eq
@@ -1300,13 +1289,13 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x10, x10, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x10, [sp, #264] ; 8-byte Spill
-; GISEL-NEXT: csel x10, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: str x10, [sp, #208] ; 8-byte Spill
+; GISEL-NEXT: csel x10, xzr, x23, eq
; GISEL-NEXT: orr x10, x3, x10
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: csel x10, x28, x10, eq
+; GISEL-NEXT: csel x10, x26, x10, eq
; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #3
@@ -1330,31 +1319,32 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #12
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: csel x13, xzr, x10, eq
+; GISEL-NEXT: csel x12, xzr, x10, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: ldp x12, x10, [x6, #16]
-; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: ldp x13, x10, [x1, #16]
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsl x19, x12, x14
-; GISEL-NEXT: csel x11, x11, x13, eq
+; GISEL-NEXT: csel x11, x11, x12, eq
+; GISEL-NEXT: lsl x15, x13, x16
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #256] ; 8-byte Spill
-; GISEL-NEXT: csel x11, xzr, x5, eq
+; GISEL-NEXT: str x11, [sp, #200] ; 8-byte Spill
+; GISEL-NEXT: csel x11, xzr, x14, eq
+; GISEL-NEXT: lsr x17, x13, x27
+; GISEL-NEXT: lsl x0, x10, x16
+; GISEL-NEXT: orr x11, x15, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: lsr x15, x12, x1
-; GISEL-NEXT: lsl x14, x10, x16
+; GISEL-NEXT: and x16, x8, #0x3f
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x17, x10, x1
-; GISEL-NEXT: csel x13, xzr, x0, eq
+; GISEL-NEXT: stp x26, x15, [sp, #32] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x12, xzr, x23, eq
+; GISEL-NEXT: orr x12, x3, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x13, x3, x13
-; GISEL-NEXT: csel x11, x13, x11, eq
+; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: csel x11, x28, x11, eq
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #4
@@ -1382,25 +1372,26 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x11, x12, x11, eq
+; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #248] ; 8-byte Spill
-; GISEL-NEXT: csel x11, xzr, x15, eq
+; GISEL-NEXT: str x11, [sp, #192] ; 8-byte Spill
+; GISEL-NEXT: csel x11, xzr, x17, eq
+; GISEL-NEXT: orr x11, x0, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x14, x11
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: orr x12, x15, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #2
+; GISEL-NEXT: csel x12, xzr, x23, eq
; GISEL-NEXT: orr x12, x3, x12
+; GISEL-NEXT: cmp x9, #2
+; GISEL-NEXT: lsr x3, x10, x27
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: csel x11, x28, x11, eq
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #5
@@ -1422,41 +1413,41 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #13
; GISEL-NEXT: csel x13, xzr, x11, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: ldp x12, x11, [x6, #32]
; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: ldp x12, x11, [x1, #32]
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x13, xzr, x13, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsl x0, x12, x16
; GISEL-NEXT: csel x10, x10, x13, eq
+; GISEL-NEXT: lsl x30, x12, x16
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x10, [sp, #240] ; 8-byte Spill
-; GISEL-NEXT: csel x10, xzr, x17, eq
+; GISEL-NEXT: str x10, [sp, #184] ; 8-byte Spill
+; GISEL-NEXT: csel x10, xzr, x3, eq
+; GISEL-NEXT: lsr x6, x12, x27
+; GISEL-NEXT: lsl x19, x11, x16
+; GISEL-NEXT: orr x10, x30, x10
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x10, x0, x10
-; GISEL-NEXT: lsr x26, x12, x1
-; GISEL-NEXT: lsl x24, x11, x16
+; GISEL-NEXT: and x16, x8, #0x3f
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x16, x15
-; GISEL-NEXT: csel x13, xzr, x15, eq
+; GISEL-NEXT: lsr x5, x11, x27
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: str x30, [sp, #24] ; 8-byte Spill
+; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: str x0, [sp, #32] ; 8-byte Spill
-; GISEL-NEXT: orr x13, x14, x13
-; GISEL-NEXT: stp x14, x16, [sp, #56] ; 16-byte Folded Spill
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: orr x13, x2, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x13, x3, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: csel x10, x28, x10, eq
+; GISEL-NEXT: csel x10, x26, x10, eq
; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #6
@@ -1482,37 +1473,34 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x10, [sp, #232] ; 8-byte Spill
-; GISEL-NEXT: csel x10, xzr, x26, eq
+; GISEL-NEXT: str x10, [sp, #176] ; 8-byte Spill
+; GISEL-NEXT: csel x10, xzr, x6, eq
+; GISEL-NEXT: orr x10, x19, x10
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x10, x24, x10
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: orr x12, x30, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x15, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: and x15, x8, #0x3f
-; GISEL-NEXT: orr x12, x14, x12
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: orr x12, x15, x12
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: csel x12, xzr, x23, eq
+; GISEL-NEXT: orr x12, x2, x12
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x12, x3, x12
-; GISEL-NEXT: lsr x3, x11, x1
; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: csel x10, x28, x10, eq
+; GISEL-NEXT: csel x10, x26, x10, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: str x3, [sp, #344] ; 8-byte Spill
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x10, xzr, x10, eq
@@ -1529,53 +1517,55 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #13
; GISEL-NEXT: csel x13, xzr, x10, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: ldp x12, x10, [x6, #48]
; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: ldp x12, x10, [x1, #48]
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x13, xzr, x13, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsl x5, x12, x15
; GISEL-NEXT: csel x11, x11, x13, eq
+; GISEL-NEXT: lsl x7, x12, x16
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #224] ; 8-byte Spill
-; GISEL-NEXT: csel x11, xzr, x3, eq
+; GISEL-NEXT: str x11, [sp, #168] ; 8-byte Spill
+; GISEL-NEXT: csel x11, xzr, x5, eq
+; GISEL-NEXT: lsl x20, x10, x16
+; GISEL-NEXT: mov x16, x14
+; GISEL-NEXT: orr x11, x7, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x5, x11
-; GISEL-NEXT: lsl x4, x10, x15
+; GISEL-NEXT: lsr x22, x10, x27
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x26, eq
+; GISEL-NEXT: str x16, [sp, #216] ; 8-byte Spill
+; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: stp x4, x26, [sp, #272] ; 16-byte Folded Spill
-; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: orr x13, x30, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x13, x14, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: orr x13, x2, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: lsr x13, x12, x1
-; GISEL-NEXT: csel x11, x28, x11, eq
+; GISEL-NEXT: lsr x13, x12, x27
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: mov x15, x13
+; GISEL-NEXT: mov x4, x13
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #9
; GISEL-NEXT: csel x11, xzr, x11, eq
@@ -1594,43 +1584,44 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #216] ; 8-byte Spill
+; GISEL-NEXT: str x11, [sp, #160] ; 8-byte Spill
; GISEL-NEXT: csel x11, xzr, x13, eq
+; GISEL-NEXT: orr x11, x20, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x4, x11
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: orr x12, x7, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x12, x5, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x26, eq
+; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: orr x12, x30, x12
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x16, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x12, x14, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x7, eq
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: and x14, x8, #0x3f
+; GISEL-NEXT: orr x12, x15, x12
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: csel x12, xzr, x23, eq
+; GISEL-NEXT: orr x12, x2, x12
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x12, x21, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: csel x11, x28, x11, eq
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #8
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #9
@@ -1647,63 +1638,64 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x12, xzr, x11, eq
-; GISEL-NEXT: ldr x11, [x6, #64]
+; GISEL-NEXT: ldp x11, x21, [x1, #64]
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsr x6, x10, x1
; GISEL-NEXT: csel x12, x10, x12, eq
+; GISEL-NEXT: mov x1, x2
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsl x25, x11, x30
-; GISEL-NEXT: str x12, [sp, #208] ; 8-byte Spill
-; GISEL-NEXT: ldr x1, [x23, #72]
-; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: str x12, [sp, #152] ; 8-byte Spill
+; GISEL-NEXT: mov x10, x16
+; GISEL-NEXT: lsl x24, x11, x14
+; GISEL-NEXT: csel x12, xzr, x22, eq
+; GISEL-NEXT: lsr x25, x11, x27
+; GISEL-NEXT: lsl x28, x21, x14
+; GISEL-NEXT: ldr x14, [sp, #280] ; 8-byte Reload
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: lsr x30, x11, x27
-; GISEL-NEXT: orr x12, x25, x12
-; GISEL-NEXT: mov x10, x3
+; GISEL-NEXT: str x24, [sp, #72] ; 8-byte Spill
; GISEL-NEXT: csel x12, x12, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: str x28, [sp, #16] ; 8-byte Spill
; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: orr x13, x20, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: orr x13, x7, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: mov x3, x4
-; GISEL-NEXT: orr x13, x5, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x26, eq
+; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: orr x13, x30, x13
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x13, x14, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: mov x7, x5
-; GISEL-NEXT: orr x13, x19, x13
-; GISEL-NEXT: str x7, [sp, #120] ; 8-byte Spill
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: orr x13, x2, x13
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x13, x21, x13
+; GISEL-NEXT: mov x2, x17
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: cmp x9, #8
; GISEL-NEXT: and x13, x8, #0x3f
-; GISEL-NEXT: csel x12, x28, x12, eq
+; GISEL-NEXT: csel x12, x26, x12, eq
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: lsl x21, x1, x13
+; GISEL-NEXT: str x2, [sp, #48] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #10
; GISEL-NEXT: csel x12, xzr, x12, eq
@@ -1720,60 +1712,57 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x11, x11, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #200] ; 8-byte Spill
-; GISEL-NEXT: csel x11, xzr, x30, eq
+; GISEL-NEXT: str x11, [sp, #144] ; 8-byte Spill
+; GISEL-NEXT: csel x11, xzr, x25, eq
+; GISEL-NEXT: orr x11, x28, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x21, x11
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: csel x12, xzr, x22, eq
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x12, x25, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x15, eq
+; GISEL-NEXT: csel x12, xzr, x4, eq
+; GISEL-NEXT: orr x12, x20, x12
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x12, x4, x12
-; GISEL-NEXT: mov x4, x25
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x10, eq
+; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: orr x12, x7, x12
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: mov x10, x24
-; GISEL-NEXT: orr x12, x5, x12
-; GISEL-NEXT: lsr x5, x1, x27
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x26, eq
+; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: str x5, [sp, #48] ; 8-byte Spill
-; GISEL-NEXT: orr x12, x24, x12
-; GISEL-NEXT: mov x24, x0
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: orr x12, x30, x12
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x16, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: mov x17, x23
+; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x12, x14, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x20, eq
+; GISEL-NEXT: csel x12, xzr, x16, eq
+; GISEL-NEXT: mov x16, x27
+; GISEL-NEXT: orr x12, x15, x12
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: mov x20, x28
-; GISEL-NEXT: orr x12, x19, x12
-; GISEL-NEXT: str x20, [sp, #328] ; 8-byte Spill
+; GISEL-NEXT: str x16, [sp, #224] ; 8-byte Spill
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: csel x12, xzr, x23, eq
+; GISEL-NEXT: mov x23, x1
+; GISEL-NEXT: orr x12, x1, x12
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x12, x22, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: csel x11, x28, x11, eq
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #10
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #11
@@ -1786,574 +1775,540 @@ define void @test_shl_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x12, xzr, x11, eq
-; GISEL-NEXT: ldp x11, x28, [x23, #80]
+; GISEL-NEXT: ldp x11, x1, [x14, #80]
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: mov x23, x21
-; GISEL-NEXT: csel x12, x1, x12, eq
+; GISEL-NEXT: csel x12, x21, x12, eq
+; GISEL-NEXT: lsr x21, x21, x27
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x1, x30
-; GISEL-NEXT: lsl x0, x11, x13
-; GISEL-NEXT: str x12, [sp, #192] ; 8-byte Spill
-; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: str x12, [sp, #128] ; 8-byte Spill
+; GISEL-NEXT: lsl x27, x11, x13
+; GISEL-NEXT: csel x12, xzr, x21, eq
+; GISEL-NEXT: mov x14, x21
+; GISEL-NEXT: mov x21, x0
+; GISEL-NEXT: orr x12, x27, x12
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x1, [sp, #88] ; 8-byte Spill
-; GISEL-NEXT: orr x12, x0, x12
-; GISEL-NEXT: str x0, [sp, #288] ; 8-byte Spill
+; GISEL-NEXT: str x27, [sp, #80] ; 8-byte Spill
; GISEL-NEXT: csel x12, x12, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x28, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: ldr x30, [sp, #344] ; 8-byte Reload
-; GISEL-NEXT: orr x13, x21, x13
-; GISEL-NEXT: mov x21, x15
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x21, [sp, #296] ; 8-byte Spill
-; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: csel x13, xzr, x22, eq
+; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x25, x13
-; GISEL-NEXT: mov x25, x27
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x25, [sp, #16] ; 8-byte Spill
-; GISEL-NEXT: csel x13, xzr, x15, eq
+; GISEL-NEXT: csel x13, xzr, x4, eq
+; GISEL-NEXT: orr x13, x20, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: mov x15, x17
-; GISEL-NEXT: orr x13, x3, x13
-; GISEL-NEXT: mov x3, x20
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x30, eq
-; GISEL-NEXT: cmp x9, #4
+; GISEL-NEXT: csel x13, xzr, x5, eq
; GISEL-NEXT: orr x13, x7, x13
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x26, eq
+; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x26, x10
-; GISEL-NEXT: orr x13, x10, x13
-; GISEL-NEXT: mov x10, x14
-; GISEL-NEXT: str x26, [sp, #104] ; 8-byte Spill
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: orr x13, x30, x13
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: mov x17, x22
-; GISEL-NEXT: orr x13, x24, x13
-; GISEL-NEXT: mov x24, x19
-; GISEL-NEXT: str x17, [sp, #96] ; 8-byte Spill
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x13, x14, x13
-; GISEL-NEXT: ldr x14, [sp, #24] ; 8-byte Reload
+; GISEL-NEXT: mov x0, x14
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x10, eq
+; GISEL-NEXT: mov x10, x15
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: mov x2, x1
-; GISEL-NEXT: orr x13, x22, x13
-; GISEL-NEXT: mov x22, x23
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: lsr x13, x11, x27
-; GISEL-NEXT: csel x12, x20, x12, eq
+; GISEL-NEXT: lsr x13, x11, x16
+; GISEL-NEXT: csel x12, x26, x12, eq
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: mov x27, x4
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: str x13, [sp, #136] ; 8-byte Spill
+; GISEL-NEXT: stp x13, x0, [sp, #264] ; 16-byte Folded Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: mov x20, x26
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: stp x27, x22, [sp, #72] ; 16-byte Folded Spill
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x11, x11, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #184] ; 8-byte Spill
+; GISEL-NEXT: str x11, [sp, #120] ; 8-byte Spill
; GISEL-NEXT: and x11, x8, #0x3f
-; GISEL-NEXT: lsl x19, x28, x11
+; GISEL-NEXT: lsl x15, x1, x11
; GISEL-NEXT: csel x11, xzr, x13, eq
+; GISEL-NEXT: orr x11, x15, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: str x19, [sp, #304] ; 8-byte Spill
+; GISEL-NEXT: str x15, [sp, #240] ; 8-byte Spill
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: ldr x14, [sp, #216] ; 8-byte Reload
+; GISEL-NEXT: orr x12, x27, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: mov x5, x7
-; GISEL-NEXT: orr x12, x0, x12
-; GISEL-NEXT: ldr x0, [sp, #32] ; 8-byte Reload
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x1, eq
+; GISEL-NEXT: csel x12, xzr, x25, eq
+; GISEL-NEXT: orr x12, x28, x12
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: mov x1, x17
-; GISEL-NEXT: orr x12, x23, x12
-; GISEL-NEXT: mov x23, x21
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: csel x12, xzr, x22, eq
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x12, x4, x12
-; GISEL-NEXT: mov x4, x15
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x21, eq
-; GISEL-NEXT: ldr x21, [sp, #272] ; 8-byte Reload
+; GISEL-NEXT: csel x12, xzr, x4, eq
+; GISEL-NEXT: orr x12, x20, x12
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x12, x21, x12
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x30, eq
-; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x30, x27
+; GISEL-NEXT: csel x12, xzr, x5, eq
; GISEL-NEXT: orr x12, x7, x12
-; GISEL-NEXT: ldr x7, [sp, #280] ; 8-byte Reload
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x7, eq
+; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x12, x26, x12
-; GISEL-NEXT: ldr x26, [sp, #48] ; 8-byte Reload
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x15, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: orr x12, x30, x12
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: ldr x15, [sp, #320] ; 8-byte Reload
-; GISEL-NEXT: orr x12, x0, x12
+; GISEL-NEXT: mov x30, x2
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x16, eq
+; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: mov x2, x0
+; GISEL-NEXT: orr x12, x21, x12
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: mov x16, x14
-; GISEL-NEXT: orr x12, x10, x12
-; GISEL-NEXT: ldr x10, [sp, #336] ; 8-byte Reload
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: orr x12, x10, x12
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x12, x24, x12
+; GISEL-NEXT: ldr x10, [sp, #280] ; 8-byte Reload
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x15, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x23, x12
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x12, x17, x12
-; GISEL-NEXT: mov x17, x13
; GISEL-NEXT: csel x11, x12, x11, eq
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: csel x11, x3, x11, eq
+; GISEL-NEXT: csel x11, x26, x11, eq
; GISEL-NEXT: cmp x9, #12
+; GISEL-NEXT: ldr x26, [sp, #16] ; 8-byte Reload
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #13
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #14
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: csel x12, xzr, x11, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: ldp x11, x3, [x10, #96]
-; GISEL-NEXT: csel x12, x28, x12, eq
-; GISEL-NEXT: str x12, [sp, #168] ; 8-byte Spill
-; GISEL-NEXT: lsr x12, x28, x25
-; GISEL-NEXT: and x10, x8, #0x3f
+; GISEL-NEXT: csel x11, x1, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x28, x0
-; GISEL-NEXT: lsl x14, x11, x10
-; GISEL-NEXT: csel x10, xzr, x12, eq
+; GISEL-NEXT: str x11, [sp, #112] ; 8-byte Spill
+; GISEL-NEXT: lsr x11, x1, x16
+; GISEL-NEXT: ldr x16, [sp, #24] ; 8-byte Reload
+; GISEL-NEXT: ldp x12, x1, [x10, #96]
+; GISEL-NEXT: and x10, x8, #0x3f
+; GISEL-NEXT: str x11, [sp, #232] ; 8-byte Spill
+; GISEL-NEXT: lsl x28, x12, x10
+; GISEL-NEXT: csel x10, xzr, x11, eq
+; GISEL-NEXT: mov x11, x13
+; GISEL-NEXT: orr x10, x28, x10
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x12, [sp, #112] ; 8-byte Spill
-; GISEL-NEXT: ldr x12, [sp, #288] ; 8-byte Reload
-; GISEL-NEXT: orr x10, x14, x10
-; GISEL-NEXT: str x14, [sp, #312] ; 8-byte Spill
-; GISEL-NEXT: mov x14, x6
+; GISEL-NEXT: stp x25, x28, [sp, #56] ; 16-byte Folded Spill
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x14, [sp, #40] ; 8-byte Spill
; GISEL-NEXT: csel x13, xzr, x13, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x26, eq
+; GISEL-NEXT: csel x13, xzr, x0, eq
+; GISEL-NEXT: ldp x15, x0, [sp, #32] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x13, x27, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x12, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x26, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: ldr x2, [sp, #344] ; 8-byte Reload
-; GISEL-NEXT: orr x13, x22, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: csel x13, xzr, x22, eq
+; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: mov x6, x16
-; GISEL-NEXT: orr x13, x27, x13
-; GISEL-NEXT: ldr x27, [sp, #112] ; 8-byte Reload
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: csel x13, xzr, x4, eq
+; GISEL-NEXT: orr x13, x20, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x23, x3
-; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: orr x13, x7, x13
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x13, x5, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x6, eq
+; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x13, x20, x13
-; GISEL-NEXT: ldp x19, x20, [sp, #56] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x4, eq
+; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: orr x13, x16, x13
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x13, x0, x13
-; GISEL-NEXT: ldr x0, [sp, #88] ; 8-byte Reload
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x20, eq
+; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: ldp x30, x14, [sp, #224] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x13, x0, x13
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x13, x24, x13
-; GISEL-NEXT: ldp x16, x5, [sp, #304] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x15, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: mov x15, x25
-; GISEL-NEXT: orr x13, x1, x13
-; GISEL-NEXT: ldr x1, [sp, #328] ; 8-byte Reload
; GISEL-NEXT: csel x10, x13, x10, eq
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: lsr x13, x11, x25
-; GISEL-NEXT: csel x10, x1, x10, eq
+; GISEL-NEXT: lsr x13, x12, x30
+; GISEL-NEXT: csel x10, x15, x10, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: ldr x25, [sp, #120] ; 8-byte Reload
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: str x13, [sp, #144] ; 8-byte Spill
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x10, [sp, #160] ; 8-byte Spill
+; GISEL-NEXT: str x10, [sp, #104] ; 8-byte Spill
; GISEL-NEXT: and x10, x8, #0x3f
-; GISEL-NEXT: lsl x11, x3, x10
+; GISEL-NEXT: lsl x12, x1, x10
; GISEL-NEXT: csel x10, xzr, x13, eq
+; GISEL-NEXT: orr x10, x12, x10
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: mov x13, x21
-; GISEL-NEXT: ldr x3, [sp, #320] ; 8-byte Reload
-; GISEL-NEXT: orr x10, x11, x10
-; GISEL-NEXT: str x11, [sp, #128] ; 8-byte Spill
+; GISEL-NEXT: stp x12, x13, [sp, #248] ; 16-byte Folded Spill
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x27, eq
+; GISEL-NEXT: ldr x13, [sp, #240] ; 8-byte Reload
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: orr x12, x28, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x11, x5, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldr x28, [sp, #216] ; 8-byte Reload
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x17, eq
+; GISEL-NEXT: csel x12, xzr, x11, eq
+; GISEL-NEXT: mov x11, x27
+; GISEL-NEXT: orr x12, x13, x12
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: mov x17, x1
-; GISEL-NEXT: orr x11, x16, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x26, eq
+; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: mov x2, x21
+; GISEL-NEXT: orr x12, x27, x12
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x11, x12, x11
-; GISEL-NEXT: ldr x12, [sp, #296] ; 8-byte Reload
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x27, x26
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x0, eq
+; GISEL-NEXT: csel x12, xzr, x25, eq
+; GISEL-NEXT: mov x25, x20
+; GISEL-NEXT: orr x12, x26, x12
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x11, x22, x11
-; GISEL-NEXT: ldr x22, [sp, #128] ; 8-byte Reload
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x26, x22
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x14, eq
+; GISEL-NEXT: csel x12, xzr, x22, eq
+; GISEL-NEXT: mov x22, x4
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x11, x30, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x24, x7
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x12, eq
+; GISEL-NEXT: csel x12, xzr, x4, eq
+; GISEL-NEXT: orr x12, x20, x12
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x11, x21, x11
-; GISEL-NEXT: ldr x21, [sp, #104] ; 8-byte Reload
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x20, x5
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x2, eq
+; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: mov x5, x16
+; GISEL-NEXT: orr x12, x7, x12
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: mov x2, x19
-; GISEL-NEXT: orr x11, x25, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x7, x6
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x7, eq
+; GISEL-NEXT: csel x12, xzr, x6, eq
+; GISEL-NEXT: mov x6, x3
+; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: mov x7, x28
-; GISEL-NEXT: orr x11, x21, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x4, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: ldr x3, [sp, #48] ; 8-byte Reload
+; GISEL-NEXT: orr x12, x16, x12
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x11, x28, x11
-; GISEL-NEXT: mov x28, x20
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x16, x15
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x20, eq
+; GISEL-NEXT: csel x12, xzr, x3, eq
+; GISEL-NEXT: orr x12, x21, x12
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: ldr x19, [sp, #96] ; 8-byte Reload
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: mov x21, x0
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x6, eq
+; GISEL-NEXT: csel x12, xzr, x28, eq
+; GISEL-NEXT: orr x12, x0, x12
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: orr x11, x24, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x3, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x23, x12
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: csel x10, x12, x10, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: csel x10, x1, x10, eq
+; GISEL-NEXT: csel x10, x15, x10, eq
+; GISEL-NEXT: ldr x15, [sp, #280] ; 8-byte Reload
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: ldr x1, [sp, #336] ; 8-byte Reload
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: csel x11, xzr, x10, eq
+; GISEL-NEXT: csel x12, xzr, x10, eq
+; GISEL-NEXT: ldp x10, x4, [x15, #112]
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x11, x23, x11, eq
-; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #152] ; 8-byte Spill
-; GISEL-NEXT: lsr x11, x23, x15
-; GISEL-NEXT: ldr x23, [sp, #288] ; 8-byte Reload
-; GISEL-NEXT: ldp x10, x15, [x1, #112]
-; GISEL-NEXT: and x1, x8, #0x3f
-; GISEL-NEXT: lsl x20, x10, x1
-; GISEL-NEXT: csel x1, xzr, x11, eq
+; GISEL-NEXT: csel x12, x1, x12, eq
+; GISEL-NEXT: and x15, x8, #0x3f
+; GISEL-NEXT: stp x17, x12, [sp, #88] ; 16-byte Folded Spill
+; GISEL-NEXT: lsr x12, x1, x30
+; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: lsl x0, x10, x15
+; GISEL-NEXT: ldr x15, [sp, #256] ; 8-byte Reload
+; GISEL-NEXT: csel x1, xzr, x12, eq
+; GISEL-NEXT: orr x1, x0, x1
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x20, [sp, #336] ; 8-byte Spill
-; GISEL-NEXT: orr x1, x20, x1
-; GISEL-NEXT: ldr x20, [sp, #144] ; 8-byte Reload
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x20, eq
+; GISEL-NEXT: csel x30, xzr, x15, eq
+; GISEL-NEXT: ldr x15, [sp, #248] ; 8-byte Reload
+; GISEL-NEXT: orr x30, x15, x30
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x30, x22, x30
+; GISEL-NEXT: ldr x15, [sp, #264] ; 8-byte Reload
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x27, eq
+; GISEL-NEXT: csel x30, xzr, x14, eq
+; GISEL-NEXT: ldr x14, [sp, #64] ; 8-byte Reload
+; GISEL-NEXT: orr x30, x14, x30
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x30, x5, x30
-; GISEL-NEXT: ldr x5, [sp, #136] ; 8-byte Reload
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x5, eq
+; GISEL-NEXT: csel x30, xzr, x15, eq
+; GISEL-NEXT: ldr x15, [sp, #56] ; 8-byte Reload
+; GISEL-NEXT: orr x30, x13, x30
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x30, x16, x30
-; GISEL-NEXT: ldr x16, [sp, #80] ; 8-byte Reload
+; GISEL-NEXT: ldr x13, [sp, #272] ; 8-byte Reload
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x26, eq
+; GISEL-NEXT: csel x30, xzr, x13, eq
+; GISEL-NEXT: ldr x13, [sp, #72] ; 8-byte Reload
+; GISEL-NEXT: orr x30, x11, x30
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x30, x23, x30
+; GISEL-NEXT: ldr x11, [sp, #224] ; 8-byte Reload
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x0, eq
+; GISEL-NEXT: csel x30, xzr, x15, eq
+; GISEL-NEXT: orr x30, x27, x30
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x30, x16, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x14, eq
-; GISEL-NEXT: ldr x14, [sp, #72] ; 8-byte Reload
+; GISEL-NEXT: csel x30, xzr, x26, eq
+; GISEL-NEXT: orr x30, x13, x30
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x30, x14, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x12, eq
+; GISEL-NEXT: csel x30, xzr, x22, eq
+; GISEL-NEXT: orr x30, x25, x30
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: ldr x12, [sp, #344] ; 8-byte Reload
-; GISEL-NEXT: orr x30, x13, x30
-; GISEL-NEXT: ldr x13, [sp, #280] ; 8-byte Reload
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x12, eq
+; GISEL-NEXT: csel x30, xzr, x20, eq
+; GISEL-NEXT: orr x30, x24, x30
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x30, x25, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x13, eq
+; GISEL-NEXT: csel x30, xzr, x7, eq
+; GISEL-NEXT: orr x30, x19, x30
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x30, x21, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x4, eq
+; GISEL-NEXT: csel x30, xzr, x6, eq
+; GISEL-NEXT: orr x30, x5, x30
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x30, x7, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x28, eq
-; GISEL-NEXT: cmp x9, #11
+; GISEL-NEXT: csel x30, xzr, x3, eq
; GISEL-NEXT: orr x30, x2, x30
+; GISEL-NEXT: cmp x9, #11
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x6, eq
+; GISEL-NEXT: csel x30, xzr, x28, eq
+; GISEL-NEXT: orr x30, x21, x30
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: orr x30, x24, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x30, xzr, x3, eq
+; GISEL-NEXT: csel x30, xzr, x17, eq
+; GISEL-NEXT: orr x30, x23, x30
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: orr x30, x19, x30
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: csel x1, x17, x1, eq
+; GISEL-NEXT: lsr x30, x10, x11
+; GISEL-NEXT: csel x1, x16, x1, eq
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: ldr x17, [sp, #16] ; 8-byte Reload
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: lsr x30, x10, x17
; GISEL-NEXT: csel x17, x10, x1, eq
; GISEL-NEXT: and x10, x8, #0x3f
-; GISEL-NEXT: lsl x10, x15, x10
; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: lsl x10, x4, x10
; GISEL-NEXT: csel x1, xzr, x30, eq
-; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: ldp x29, x30, [sp, #368] ; 16-byte Folded Reload
; GISEL-NEXT: orr x10, x10, x1
-; GISEL-NEXT: ldr x1, [sp, #336] ; 8-byte Reload
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: csel x12, xzr, x12, eq
+; GISEL-NEXT: orr x11, x0, x12
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x11, x1, x11
-; GISEL-NEXT: ldr x1, [sp, #312] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldp x12, x11, [sp, #248] ; 16-byte Folded Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x20, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x12, x11
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x11, x22, x11
-; GISEL-NEXT: ldp x29, x30, [sp, #432] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldp x11, x12, [sp, #232] ; 16-byte Folded Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x27, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x14, x11
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x11, x1, x11
-; GISEL-NEXT: ldr x1, [sp, #304] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldr x11, [sp, #264] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x5, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x12, x11
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x11, x1, x11
+; GISEL-NEXT: ldr x12, [sp, #80] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldr x11, [sp, #272] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x26, eq
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x12, x11
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x11, x23, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x0, eq
+; GISEL-NEXT: csel x11, xzr, x15, eq
+; GISEL-NEXT: orr x11, x27, x11
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x11, x16, x11
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #40] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: csel x11, xzr, x26, eq
+; GISEL-NEXT: orr x11, x13, x11
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x11, x14, x11
-; GISEL-NEXT: ldr x14, [sp, #272] ; 8-byte Reload
+; GISEL-NEXT: ldr x13, [sp, #136] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #296] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: csel x11, xzr, x22, eq
+; GISEL-NEXT: orr x11, x25, x11
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x11, x14, x11
-; GISEL-NEXT: ldr x14, [sp, #176] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x12, eq
+; GISEL-NEXT: csel x11, xzr, x20, eq
+; GISEL-NEXT: ldp x26, x25, [sp, #304] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x11, x24, x11
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x11, x25, x11
-; GISEL-NEXT: ldp x26, x25, [sp, #368] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x13, eq
+; GISEL-NEXT: csel x11, xzr, x7, eq
+; GISEL-NEXT: orr x11, x19, x11
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x11, x21, x11
-; GISEL-NEXT: ldp x22, x21, [sp, #400] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #264] ; 8-byte Reload
+; GISEL-NEXT: ldr x11, [sp, #208] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [x14]
-; GISEL-NEXT: ldp x12, x11, [sp, #248] ; 16-byte Folded Reload
-; GISEL-NEXT: stp x11, x12, [x14, #8]
-; GISEL-NEXT: csel x11, xzr, x4, eq
+; GISEL-NEXT: ldp x20, x19, [sp, #352] ; 16-byte Folded Reload
+; GISEL-NEXT: str x11, [x13]
+; GISEL-NEXT: ldp x12, x11, [sp, #192] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x11, x12, [x13, #8]
+; GISEL-NEXT: csel x11, xzr, x6, eq
+; GISEL-NEXT: orr x11, x5, x11
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: orr x11, x7, x11
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #240] ; 8-byte Reload
+; GISEL-NEXT: ldr x11, [sp, #184] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [x14, #24]
-; GISEL-NEXT: ldp x12, x11, [sp, #224] ; 16-byte Folded Reload
-; GISEL-NEXT: stp x11, x12, [x14, #32]
-; GISEL-NEXT: csel x11, xzr, x28, eq
-; GISEL-NEXT: cmp x9, #12
+; GISEL-NEXT: str x11, [x13, #24]
+; GISEL-NEXT: ldp x12, x11, [sp, #168] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x11, x12, [x13, #32]
+; GISEL-NEXT: csel x11, xzr, x3, eq
; GISEL-NEXT: orr x11, x2, x11
-; GISEL-NEXT: ldp x28, x27, [sp, #352] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x9, #12
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #216] ; 8-byte Reload
+; GISEL-NEXT: ldr x11, [sp, #160] ; 8-byte Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [x14, #48]
-; GISEL-NEXT: ldp x12, x11, [sp, #200] ; 16-byte Folded Reload
-; GISEL-NEXT: stp x11, x12, [x14, #56]
-; GISEL-NEXT: csel x11, xzr, x6, eq
+; GISEL-NEXT: str x11, [x13, #48]
+; GISEL-NEXT: ldp x12, x11, [sp, #144] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x11, x12, [x13, #56]
+; GISEL-NEXT: csel x11, xzr, x28, eq
+; GISEL-NEXT: orr x11, x21, x11
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: orr x11, x24, x11
-; GISEL-NEXT: ldr x12, [sp, #168] ; 8-byte Reload
; GISEL-NEXT: csel x10, x11, x10, eq
-; GISEL-NEXT: ldr x11, [sp, #192] ; 8-byte Reload
-; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldp x24, x23, [sp, #384] ; 16-byte Folded Reload
-; GISEL-NEXT: str x11, [x14, #72]
-; GISEL-NEXT: ldr x11, [sp, #184] ; 8-byte Reload
-; GISEL-NEXT: str x11, [x14, #80]
-; GISEL-NEXT: csel x11, xzr, x3, eq
+; GISEL-NEXT: ldr x11, [sp, #128] ; 8-byte Reload
+; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: ldp x22, x21, [sp, #336] ; 16-byte Folded Reload
+; GISEL-NEXT: str x11, [x13, #72]
+; GISEL-NEXT: ldp x12, x11, [sp, #112] ; 16-byte Folded Reload
+; GISEL-NEXT: ldp x28, x27, [sp, #288] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x11, x12, [x13, #80]
+; GISEL-NEXT: ldr x11, [sp, #88] ; 8-byte Reload
+; GISEL-NEXT: csel x11, xzr, x11, eq
+; GISEL-NEXT: orr x11, x23, x11
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: ldp x20, x19, [sp, #416] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x11, x10, eq
+; GISEL-NEXT: ldr x11, [sp, #104] ; 8-byte Reload
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: ldr x9, [sp, #160] ; 8-byte Reload
-; GISEL-NEXT: stp x12, x9, [x14, #88]
-; GISEL-NEXT: ldr x9, [sp, #328] ; 8-byte Reload
-; GISEL-NEXT: csel x9, x9, x10, eq
+; GISEL-NEXT: csel x9, x16, x10, eq
+; GISEL-NEXT: ldr x10, [sp, #96] ; 8-byte Reload
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: ldr x8, [sp, #152] ; 8-byte Reload
-; GISEL-NEXT: stp x8, x17, [x14, #104]
-; GISEL-NEXT: csel x8, x15, x9, eq
-; GISEL-NEXT: str x8, [x14, #120]
-; GISEL-NEXT: add sp, sp, #448
+; GISEL-NEXT: csel x8, x4, x9, eq
+; GISEL-NEXT: ldp x24, x23, [sp, #320] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x11, x10, [x13, #96]
+; GISEL-NEXT: stp x17, x8, [x13, #112]
+; GISEL-NEXT: add sp, sp, #384
; GISEL-NEXT: ret
entry:
%input_val = load i1024, ptr %input, align 128
@@ -2521,327 +2476,328 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: sub x15, x9, x14
; GISEL-NEXT: lsr x9, x8, #6
-; GISEL-NEXT: str x0, [sp, #288] ; 8-byte Spill
-; GISEL-NEXT: str x12, [sp, #160] ; 8-byte Spill
+; GISEL-NEXT: str x0, [sp, #280] ; 8-byte Spill
+; GISEL-NEXT: stp x12, x16, [sp, #152] ; 16-byte Folded Spill
; GISEL-NEXT: lsl x10, x16, x15
; GISEL-NEXT: lsr x11, x12, x14
; GISEL-NEXT: ldp x12, x13, [x1, #16]
; GISEL-NEXT: lsr x19, x16, x14
; GISEL-NEXT: csel x10, xzr, x10, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x16, [sp, #256] ; 8-byte Spill
+; GISEL-NEXT: ldp x5, x3, [x1, #64]
; GISEL-NEXT: orr x10, x11, x10
-; GISEL-NEXT: ldp x4, x2, [x1, #64]
-; GISEL-NEXT: lsl x0, x12, x15
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x10, x10, xzr, eq
+; GISEL-NEXT: lsl x28, x12, x15
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: str x12, [sp, #232] ; 8-byte Spill
; GISEL-NEXT: lsr x17, x12, x14
-; GISEL-NEXT: lsr x3, x13, x14
-; GISEL-NEXT: csel x11, xzr, x0, eq
-; GISEL-NEXT: str x0, [sp, #152] ; 8-byte Spill
; GISEL-NEXT: lsl x0, x13, x15
-; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x11, x19, x11
-; GISEL-NEXT: str x4, [sp, #208] ; 8-byte Spill
+; GISEL-NEXT: csel x11, xzr, x28, eq
; GISEL-NEXT: ldp x12, x16, [x1, #32]
+; GISEL-NEXT: orr x11, x19, x11
+; GISEL-NEXT: cmp x9, #1
+; GISEL-NEXT: stp x17, x0, [sp, #136] ; 16-byte Folded Spill
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x17, x0, [sp, #136] ; 16-byte Folded Spill
-; GISEL-NEXT: lsl x28, x2, x15
+; GISEL-NEXT: lsl x23, x3, x15
; GISEL-NEXT: csel x11, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: lsr x26, x4, x14
; GISEL-NEXT: lsl x0, x12, x15
-; GISEL-NEXT: orr x11, x17, x11
; GISEL-NEXT: stp x13, x12, [sp, #168] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x11, x17, x11
+; GISEL-NEXT: cmp x9, #2
+; GISEL-NEXT: lsr x13, x13, x14
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: lsr x17, x12, x14
; GISEL-NEXT: csel x11, xzr, x0, eq
-; GISEL-NEXT: str x0, [sp, #304] ; 8-byte Spill
+; GISEL-NEXT: stp x13, x0, [sp, #304] ; 16-byte Folded Spill
; GISEL-NEXT: lsl x0, x16, x15
+; GISEL-NEXT: orr x11, x13, x11
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x11, x3, x11
-; GISEL-NEXT: str x16, [sp, #184] ; 8-byte Spill
+; GISEL-NEXT: lsr x7, x16, x14
; GISEL-NEXT: ldp x13, x12, [x1, #48]
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x17, x0, [sp, #120] ; 16-byte Folded Spill
+; GISEL-NEXT: str x0, [sp, #128] ; 8-byte Spill
+; GISEL-NEXT: lsr x21, x5, x14
; GISEL-NEXT: csel x11, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: str x2, [sp, #216] ; 8-byte Spill
+; GISEL-NEXT: str x16, [sp, #184] ; 8-byte Spill
+; GISEL-NEXT: lsr x26, x3, x14
; GISEL-NEXT: lsl x0, x13, x15
; GISEL-NEXT: orr x11, x17, x11
-; GISEL-NEXT: lsr x17, x16, x14
+; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsl x7, x12, x15
+; GISEL-NEXT: lsl x20, x12, x15
; GISEL-NEXT: csel x11, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: stp x13, x12, [sp, #192] ; 16-byte Folded Spill
-; GISEL-NEXT: orr x11, x17, x11
; GISEL-NEXT: lsr x13, x13, x14
-; GISEL-NEXT: stp x17, x0, [sp, #104] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x11, x7, x11
+; GISEL-NEXT: cmp x9, #5
+; GISEL-NEXT: lsr x22, x12, x14
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsl x0, x4, x15
-; GISEL-NEXT: csel x11, xzr, x7, eq
-; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: lsr x22, x12, x14
+; GISEL-NEXT: stp x13, x0, [sp, #112] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x11, xzr, x20, eq
+; GISEL-NEXT: lsl x0, x5, x15
+; GISEL-NEXT: stp x5, x3, [sp, #208] ; 16-byte Folded Spill
; GISEL-NEXT: orr x11, x13, x11
-; GISEL-NEXT: str x13, [sp, #96] ; 8-byte Spill
+; GISEL-NEXT: cmp x9, #6
+; GISEL-NEXT: str x17, [sp, #296] ; 8-byte Spill
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x28, [sp, #16] ; 8-byte Spill
+; GISEL-NEXT: mov x5, x7
; GISEL-NEXT: csel x11, xzr, x0, eq
+; GISEL-NEXT: str x7, [sp, #16] ; 8-byte Spill
+; GISEL-NEXT: orr x16, x22, x11
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: str x3, [sp, #32] ; 8-byte Spill
-; GISEL-NEXT: orr x11, x22, x11
-; GISEL-NEXT: csel x16, x11, x10, eq
-; GISEL-NEXT: ldp x10, x4, [x1, #80]
+; GISEL-NEXT: stp x26, x23, [sp, #56] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x16, x16, x10, eq
+; GISEL-NEXT: ldp x11, x10, [x1, #80]
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x11, x2
-; GISEL-NEXT: csel x2, xzr, x28, eq
+; GISEL-NEXT: csel x2, xzr, x23, eq
+; GISEL-NEXT: orr x2, x21, x2
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: lsr x24, x11, x14
-; GISEL-NEXT: orr x2, x26, x2
-; GISEL-NEXT: lsl x23, x10, x15
-; GISEL-NEXT: lsl x12, x4, x15
+; GISEL-NEXT: lsl x12, x11, x15
; GISEL-NEXT: csel x16, x2, x16, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x10, [sp, #224] ; 8-byte Spill
-; GISEL-NEXT: csel x2, xzr, x23, eq
+; GISEL-NEXT: lsl x27, x10, x15
+; GISEL-NEXT: csel x2, xzr, x12, eq
+; GISEL-NEXT: str x11, [sp, #224] ; 8-byte Spill
+; GISEL-NEXT: lsr x4, x11, x14
+; GISEL-NEXT: orr x2, x26, x2
; GISEL-NEXT: cmp x9, #9
; GISEL-NEXT: ldr x11, [x1, #96]
-; GISEL-NEXT: orr x2, x24, x2
-; GISEL-NEXT: lsr x10, x10, x14
-; GISEL-NEXT: lsr x13, x4, x14
; GISEL-NEXT: csel x16, x2, x16, eq
; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: mov x3, x10
+; GISEL-NEXT: csel x2, xzr, x27, eq
+; GISEL-NEXT: stp x10, x11, [sp, #240] ; 16-byte Folded Spill
; GISEL-NEXT: lsl x25, x11, x15
-; GISEL-NEXT: csel x2, xzr, x12, eq
-; GISEL-NEXT: stp x10, x12, [sp, #80] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x2, x4, x2
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x2, x10, x2
+; GISEL-NEXT: lsr x13, x3, x14
; GISEL-NEXT: ldp x10, x30, [x1, #104]
; GISEL-NEXT: csel x16, x2, x16, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x27, x11, x14
+; GISEL-NEXT: str x12, [sp, #104] ; 8-byte Spill
+; GISEL-NEXT: lsr x6, x11, x14
; GISEL-NEXT: csel x2, xzr, x25, eq
-; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: stp x4, x11, [sp, #240] ; 16-byte Folded Spill
+; GISEL-NEXT: ldr x11, [x1, #120]
+; GISEL-NEXT: str x13, [sp, #96] ; 8-byte Spill
; GISEL-NEXT: orr x2, x13, x2
+; GISEL-NEXT: cmp x9, #11
; GISEL-NEXT: lsl x12, x10, x15
-; GISEL-NEXT: lsl x5, x30, x15
; GISEL-NEXT: csel x16, x2, x16, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x11, [x1, #120]
+; GISEL-NEXT: lsr x24, x10, x14
; GISEL-NEXT: csel x2, xzr, x12, eq
+; GISEL-NEXT: str x12, [sp, #288] ; 8-byte Spill
+; GISEL-NEXT: lsl x12, x30, x15
+; GISEL-NEXT: orr x3, x6, x2
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: lsr x21, x10, x14
-; GISEL-NEXT: orr x4, x27, x2
-; GISEL-NEXT: stp x10, x30, [sp, #264] ; 16-byte Folded Spill
-; GISEL-NEXT: mov x10, x11
-; GISEL-NEXT: csel x16, x4, x16, eq
+; GISEL-NEXT: stp x10, x30, [sp, #256] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x16, x3, x16, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x11, [sp, #280] ; 8-byte Spill
-; GISEL-NEXT: csel x1, xzr, x5, eq
-; GISEL-NEXT: cmp x9, #13
+; GISEL-NEXT: mov x10, x11
+; GISEL-NEXT: csel x1, xzr, x12, eq
+; GISEL-NEXT: str x11, [sp, #272] ; 8-byte Spill
; GISEL-NEXT: lsl x11, x11, x15
-; GISEL-NEXT: orr x1, x21, x1
-; GISEL-NEXT: lsr x20, x30, x14
-; GISEL-NEXT: lsr x6, x10, x14
+; GISEL-NEXT: orr x1, x24, x1
+; GISEL-NEXT: cmp x9, #13
+; GISEL-NEXT: mov x3, x12
+; GISEL-NEXT: str x12, [sp, #24] ; 8-byte Spill
; GISEL-NEXT: csel x1, x1, x16, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x10, [sp, #160] ; 8-byte Reload
+; GISEL-NEXT: lsr x12, x30, x14
; GISEL-NEXT: csel x30, xzr, x11, eq
+; GISEL-NEXT: lsr x2, x10, x14
+; GISEL-NEXT: ldr x10, [sp, #152] ; 8-byte Reload
+; GISEL-NEXT: ldp x16, x13, [sp, #304] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x30, x12, x30
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: str x13, [sp, #296] ; 8-byte Spill
-; GISEL-NEXT: orr x30, x20, x30
-; GISEL-NEXT: ldp x13, x4, [sp, #128] ; 16-byte Folded Reload
+; GISEL-NEXT: str x11, [sp, #88] ; 8-byte Spill
; GISEL-NEXT: csel x1, x30, x1, eq
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: str x12, [sp, #312] ; 8-byte Spill
-; GISEL-NEXT: csel x1, x6, x1, eq
+; GISEL-NEXT: stp x6, x12, [sp, #72] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x1, x2, x1, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: ldr x12, [sp, #304] ; 8-byte Reload
+; GISEL-NEXT: ldr x12, [sp, #296] ; 8-byte Reload
; GISEL-NEXT: csel x10, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x20, x11, [sp, #64] ; 16-byte Folded Spill
-; GISEL-NEXT: str x10, [sp, #160] ; 8-byte Spill
-; GISEL-NEXT: ldp x2, x10, [sp, #144] ; 16-byte Folded Reload
-; GISEL-NEXT: ldp x17, x11, [sp, #112] ; 16-byte Folded Reload
-; GISEL-NEXT: ldr x14, [sp, #104] ; 8-byte Reload
-; GISEL-NEXT: mov x30, x7
-; GISEL-NEXT: ldr x16, [sp, #80] ; 8-byte Reload
-; GISEL-NEXT: stp x5, x25, [sp, #48] ; 16-byte Folded Spill
-; GISEL-NEXT: csel x1, xzr, x10, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: ldr x10, [sp, #312] ; 8-byte Reload
+; GISEL-NEXT: stp x4, x27, [sp, #40] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x1, xzr, x28, eq
+; GISEL-NEXT: ldp x30, x28, [sp, #136] ; 16-byte Folded Reload
; GISEL-NEXT: orr x1, x19, x1
-; GISEL-NEXT: str x21, [sp, #40] ; 8-byte Spill
+; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: ldr x14, [sp, #288] ; 8-byte Reload
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x27, [sp, #24] ; 8-byte Spill
-; GISEL-NEXT: csel x19, xzr, x2, eq
+; GISEL-NEXT: str x10, [sp, #152] ; 8-byte Spill
+; GISEL-NEXT: csel x19, xzr, x28, eq
+; GISEL-NEXT: ldp x17, x11, [sp, #120] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x19, x30, x19
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x19, x4, x19
+; GISEL-NEXT: ldr x10, [sp, #160] ; 8-byte Reload
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: str x25, [sp, #8] ; 8-byte Spill
+; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: str x2, [sp, #32] ; 8-byte Spill
+; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x19, x3, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: csel x19, xzr, x11, eq
+; GISEL-NEXT: orr x19, x12, x19
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x19, x11, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x17, eq
+; GISEL-NEXT: orr x19, x7, x19
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x19, x14, x19
; GISEL-NEXT: csel x1, x19, x1, eq
+; GISEL-NEXT: ldp x15, x7, [sp, #104] ; 16-byte Folded Reload
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x7, eq
-; GISEL-NEXT: ldp x15, x7, [sp, #88] ; 16-byte Folded Reload
-; GISEL-NEXT: cmp x9, #5
+; GISEL-NEXT: csel x19, xzr, x20, eq
; GISEL-NEXT: orr x19, x7, x19
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: orr x19, x22, x19
+; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x28, eq
+; GISEL-NEXT: csel x19, xzr, x23, eq
+; GISEL-NEXT: mov x23, x21
+; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x19, x26, x19
+; GISEL-NEXT: mov x21, x25
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x23, eq
+; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: orr x19, x26, x19
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x19, x24, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: csel x19, xzr, x27, eq
+; GISEL-NEXT: ldr x27, [sp, #80] ; 8-byte Reload
+; GISEL-NEXT: orr x19, x4, x19
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: csel x1, x19, x1, eq
+; GISEL-NEXT: ldp x26, x4, [sp, #88] ; 16-byte Folded Reload
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x25, eq
-; GISEL-NEXT: ldr x25, [sp, #296] ; 8-byte Reload
+; GISEL-NEXT: mov x25, x7
+; GISEL-NEXT: orr x19, x4, x19
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x19, x25, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x10, eq
+; GISEL-NEXT: csel x19, xzr, x14, eq
+; GISEL-NEXT: orr x19, x6, x19
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: ldr x10, [sp, #256] ; 8-byte Reload
-; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: csel x19, xzr, x3, eq
+; GISEL-NEXT: ldr x3, [sp, #72] ; 8-byte Reload
+; GISEL-NEXT: orr x19, x24, x19
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: ldr x5, [sp, #72] ; 8-byte Reload
-; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: csel x19, xzr, x26, eq
+; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: orr x19, x20, x19
-; GISEL-NEXT: mov x20, x6
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: cmp x9, #14
-; GISEL-NEXT: csel x1, x6, x1, eq
+; GISEL-NEXT: csel x1, x2, x1, eq
; GISEL-NEXT: cmp x9, #15
-; GISEL-NEXT: ldr x6, [sp, #64] ; 8-byte Reload
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x10, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x1, xzr, x2, eq
+; GISEL-NEXT: csel x1, xzr, x28, eq
+; GISEL-NEXT: ldp x2, x28, [sp, #24] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x1, x30, x1
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x10, [sp, #256] ; 8-byte Spill
-; GISEL-NEXT: orr x1, x4, x1
-; GISEL-NEXT: ldp x2, x21, [sp, #48] ; 16-byte Folded Reload
+; GISEL-NEXT: str x10, [sp, #160] ; 8-byte Spill
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: ldr x10, [sp, #232] ; 8-byte Reload
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: mov x13, x20
+; GISEL-NEXT: mov x30, x0
+; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: mov x12, x30
-; GISEL-NEXT: orr x19, x3, x19
-; GISEL-NEXT: mov x4, x13
-; GISEL-NEXT: mov x3, x11
+; GISEL-NEXT: mov x16, x22
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: csel x19, xzr, x11, eq
+; GISEL-NEXT: orr x19, x12, x19
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: mov x13, x0
-; GISEL-NEXT: orr x19, x11, x19
-; GISEL-NEXT: mov x11, x14
+; GISEL-NEXT: mov x12, x17
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x17, eq
+; GISEL-NEXT: ldp x17, x6, [sp, #56] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x19, x5, x19
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x19, x14, x19
-; GISEL-NEXT: mov x14, x15
+; GISEL-NEXT: mov x5, x15
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x30, eq
-; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: mov x30, x7
+; GISEL-NEXT: csel x19, xzr, x20, eq
; GISEL-NEXT: orr x19, x7, x19
-; GISEL-NEXT: mov x7, x22
+; GISEL-NEXT: cmp x9, #4
+; GISEL-NEXT: mov x7, x23
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x0, eq
-; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x0, x11
+; GISEL-NEXT: ldr x0, [sp, #16] ; 8-byte Reload
; GISEL-NEXT: orr x19, x22, x19
-; GISEL-NEXT: mov x22, x28
+; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x28, eq
+; GISEL-NEXT: csel x19, xzr, x6, eq
+; GISEL-NEXT: orr x19, x23, x19
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: ldr x28, [sp, #40] ; 8-byte Reload
-; GISEL-NEXT: orr x19, x26, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x23, eq
+; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: ldp x23, x20, [sp, #40] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x19, x17, x19
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x19, x24, x19
+; GISEL-NEXT: mov x15, x25
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: csel x19, xzr, x20, eq
+; GISEL-NEXT: orr x19, x23, x19
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x21, eq
+; GISEL-NEXT: mov x21, x24
+; GISEL-NEXT: orr x19, x4, x19
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x19, x25, x19
-; GISEL-NEXT: ldr x25, [sp, #312] ; 8-byte Reload
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x25, eq
+; GISEL-NEXT: csel x19, xzr, x14, eq
+; GISEL-NEXT: mov x14, x15
+; GISEL-NEXT: orr x19, x3, x19
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x2, eq
+; GISEL-NEXT: orr x19, x24, x19
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: orr x19, x28, x19
+; GISEL-NEXT: ldr x24, [sp, #8] ; 8-byte Reload
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: csel x19, xzr, x26, eq
+; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: orr x19, x6, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: cmp x9, #13
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #14
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #15
@@ -2850,77 +2806,72 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x10, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: str x10, [sp, #232] ; 8-byte Spill
-; GISEL-NEXT: ldr x10, [sp, #304] ; 8-byte Reload
+; GISEL-NEXT: ldr x10, [sp, #312] ; 8-byte Reload
; GISEL-NEXT: csel x1, xzr, x10, eq
-; GISEL-NEXT: ldr x10, [sp, #32] ; 8-byte Reload
-; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: ldp x22, x10, [sp, #296] ; 16-byte Folded Reload
; GISEL-NEXT: orr x1, x10, x1
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: ldr x10, [sp, #168] ; 8-byte Reload
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x4, eq
+; GISEL-NEXT: csel x19, xzr, x11, eq
+; GISEL-NEXT: orr x19, x22, x19
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x19, x3, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x17, eq
+; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: orr x19, x0, x19
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x19, x11, x19
-; GISEL-NEXT: mov x11, x7
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: orr x19, x25, x19
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x19, x30, x19
+; GISEL-NEXT: mov x25, x16
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: csel x19, xzr, x30, eq
+; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x19, x7, x19
-; GISEL-NEXT: mov x7, x30
+; GISEL-NEXT: ldr x16, [sp, #288] ; 8-byte Reload
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x22, eq
+; GISEL-NEXT: csel x19, xzr, x6, eq
+; GISEL-NEXT: orr x19, x7, x19
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x22, x21
-; GISEL-NEXT: orr x19, x26, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x23, eq
+; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: orr x19, x17, x19
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x19, x24, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: csel x19, xzr, x20, eq
+; GISEL-NEXT: orr x19, x23, x19
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x19, x16, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x21, eq
-; GISEL-NEXT: ldr x21, [sp, #296] ; 8-byte Reload
+; GISEL-NEXT: csel x19, xzr, x24, eq
+; GISEL-NEXT: orr x19, x4, x19
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x25, eq
+; GISEL-NEXT: csel x19, xzr, x16, eq
+; GISEL-NEXT: orr x19, x3, x19
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: mov x25, x0
-; GISEL-NEXT: orr x19, x27, x19
-; GISEL-NEXT: mov x27, x28
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x2, eq
+; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x19, x28, x19
-; GISEL-NEXT: mov x28, x26
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: csel x19, xzr, x26, eq
+; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: orr x19, x6, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: cmp x9, #12
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #13
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #14
@@ -2930,78 +2881,69 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x10, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x1, xzr, x4, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x10, [sp, #304] ; 8-byte Spill
-; GISEL-NEXT: orr x1, x3, x1
-; GISEL-NEXT: mov x3, x12
+; GISEL-NEXT: csel x1, xzr, x11, eq
+; GISEL-NEXT: str x10, [sp, #312] ; 8-byte Spill
; GISEL-NEXT: ldr x10, [sp, #176] ; 8-byte Reload
+; GISEL-NEXT: orr x1, x22, x1
+; GISEL-NEXT: cmp x9, #0
+; GISEL-NEXT: mov x11, x12
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x4, x27
-; GISEL-NEXT: csel x19, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #1
+; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: mov x12, x13
; GISEL-NEXT: orr x19, x0, x19
-; GISEL-NEXT: mov x0, x13
+; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: mov x13, x25
+; GISEL-NEXT: orr x19, x15, x19
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: ldr x12, [sp, #16] ; 8-byte Reload
-; GISEL-NEXT: orr x19, x30, x19
-; GISEL-NEXT: mov x30, x23
+; GISEL-NEXT: mov x22, x13
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x13, eq
+; GISEL-NEXT: csel x19, xzr, x30, eq
+; GISEL-NEXT: orr x19, x25, x19
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: mov x13, x11
-; GISEL-NEXT: orr x19, x11, x19
-; GISEL-NEXT: mov x11, x0
+; GISEL-NEXT: mov x25, x4
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x12, eq
+; GISEL-NEXT: csel x19, xzr, x6, eq
+; GISEL-NEXT: orr x19, x7, x19
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x19, x26, x19
-; GISEL-NEXT: mov x26, x12
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x23, eq
+; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: orr x19, x17, x19
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: mov x23, x24
-; GISEL-NEXT: orr x19, x24, x19
-; GISEL-NEXT: ldr x24, [sp, #312] ; 8-byte Reload
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x15, eq
+; GISEL-NEXT: csel x19, xzr, x20, eq
+; GISEL-NEXT: orr x19, x23, x19
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: mov x15, x16
-; GISEL-NEXT: orr x19, x16, x19
-; GISEL-NEXT: mov x16, x22
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x22, eq
+; GISEL-NEXT: csel x19, xzr, x24, eq
+; GISEL-NEXT: orr x19, x4, x19
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: ldr x22, [sp, #24] ; 8-byte Reload
-; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x24, eq
+; GISEL-NEXT: csel x19, xzr, x16, eq
+; GISEL-NEXT: orr x19, x3, x19
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x19, x22, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x19, xzr, x2, eq
+; GISEL-NEXT: orr x19, x21, x19
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x19, x27, x19
-; GISEL-NEXT: mov x27, x7
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x19, xzr, x5, eq
+; GISEL-NEXT: csel x19, xzr, x26, eq
+; GISEL-NEXT: orr x19, x27, x19
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: orr x19, x6, x19
; GISEL-NEXT: csel x1, x19, x1, eq
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #12
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #13
@@ -3014,63 +2956,61 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x19, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: ldr x10, [sp, #184] ; 8-byte Reload
-; GISEL-NEXT: csel x1, xzr, x17, eq
+; GISEL-NEXT: csel x1, xzr, x11, eq
+; GISEL-NEXT: orr x1, x0, x1
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: mov x17, x3
-; GISEL-NEXT: orr x1, x25, x1
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x3, eq
+; GISEL-NEXT: csel x4, xzr, x12, eq
+; GISEL-NEXT: orr x4, x15, x4
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x3, x7, x3
-; GISEL-NEXT: mov x7, x30
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: mov x15, x25
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x0, eq
+; GISEL-NEXT: csel x4, xzr, x30, eq
+; GISEL-NEXT: orr x4, x13, x4
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x3, x13, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: mov x13, x17
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x12, eq
+; GISEL-NEXT: csel x4, xzr, x6, eq
+; GISEL-NEXT: orr x4, x7, x4
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: mov x12, x13
-; GISEL-NEXT: orr x3, x28, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x30, eq
+; GISEL-NEXT: csel x4, xzr, x5, eq
+; GISEL-NEXT: orr x4, x17, x4
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: mov x30, x24
-; GISEL-NEXT: orr x3, x23, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: csel x4, xzr, x20, eq
+; GISEL-NEXT: orr x4, x23, x4
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x3, x15, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x16, eq
+; GISEL-NEXT: csel x4, xzr, x24, eq
+; GISEL-NEXT: orr x4, x25, x4
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x3, x21, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: mov x25, x26
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x24, eq
+; GISEL-NEXT: csel x4, xzr, x16, eq
+; GISEL-NEXT: orr x4, x3, x4
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: mov x24, x22
-; GISEL-NEXT: orr x3, x22, x3
-; GISEL-NEXT: mov x22, x23
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x2, eq
+; GISEL-NEXT: csel x4, xzr, x2, eq
+; GISEL-NEXT: orr x4, x21, x4
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x3, x4, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: csel x4, xzr, x26, eq
+; GISEL-NEXT: orr x4, x27, x4
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: orr x3, x6, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: mov x4, x7
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #11
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #12
@@ -3084,55 +3024,58 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x10, x10, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x17, eq
-; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: str x10, [sp, #184] ; 8-byte Spill
-; GISEL-NEXT: orr x17, x27, x0
+; GISEL-NEXT: mov x1, x6
+; GISEL-NEXT: csel x0, xzr, x12, eq
+; GISEL-NEXT: str x10, [sp, #304] ; 8-byte Spill
; GISEL-NEXT: ldr x10, [sp, #192] ; 8-byte Reload
+; GISEL-NEXT: orr x17, x14, x0
+; GISEL-NEXT: cmp x9, #0
; GISEL-NEXT: csel x17, x17, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x11, eq
+; GISEL-NEXT: csel x0, xzr, x30, eq
+; GISEL-NEXT: orr x0, x22, x0
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x0, x13, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x26, eq
+; GISEL-NEXT: csel x0, xzr, x6, eq
+; GISEL-NEXT: mov x6, x13
+; GISEL-NEXT: orr x0, x7, x0
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x0, x28, x0
+; GISEL-NEXT: mov x7, x20
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x7, eq
+; GISEL-NEXT: csel x0, xzr, x5, eq
+; GISEL-NEXT: orr x0, x13, x0
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x0, x23, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x14, eq
+; GISEL-NEXT: csel x0, xzr, x20, eq
+; GISEL-NEXT: orr x0, x23, x0
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x0, x15, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x16, eq
+; GISEL-NEXT: csel x0, xzr, x24, eq
+; GISEL-NEXT: orr x0, x15, x0
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x0, x21, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x30, eq
+; GISEL-NEXT: csel x0, xzr, x16, eq
+; GISEL-NEXT: orr x0, x3, x0
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x0, x24, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x0, xzr, x2, eq
+; GISEL-NEXT: orr x0, x21, x0
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x0, x4, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x5, eq
+; GISEL-NEXT: csel x0, xzr, x25, eq
+; GISEL-NEXT: orr x0, x27, x0
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: orr x0, x6, x0
; GISEL-NEXT: csel x17, x0, x17, eq
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: mov x0, x7
-; GISEL-NEXT: csel x17, x20, x17, eq
+; GISEL-NEXT: mov x0, x5
+; GISEL-NEXT: csel x17, x28, x17, eq
; GISEL-NEXT: cmp x9, #10
; GISEL-NEXT: csel x17, xzr, x17, eq
; GISEL-NEXT: cmp x9, #11
@@ -3149,47 +3092,49 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x17, x10, x17, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: ldr x10, [sp, #200] ; 8-byte Reload
-; GISEL-NEXT: csel x13, xzr, x11, eq
+; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: ldp x29, x30, [sp, #400] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x12, x22, x13
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x12, x12, x13
; GISEL-NEXT: csel x12, x12, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x26, eq
+; GISEL-NEXT: csel x13, xzr, x1, eq
+; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x13, x28, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: mov x5, x6
+; GISEL-NEXT: orr x13, x6, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x22, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x24, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: orr x13, x3, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x27, x13
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: orr x13, x6, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: csel x12, x20, x12, eq
+; GISEL-NEXT: csel x12, x28, x12, eq
; GISEL-NEXT: cmp x9, #9
; GISEL-NEXT: csel x12, xzr, x12, eq
; GISEL-NEXT: cmp x9, #10
@@ -3207,45 +3152,44 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x12, x10, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x26, eq
+; GISEL-NEXT: csel x11, xzr, x1, eq
+; GISEL-NEXT: mov x1, x7
+; GISEL-NEXT: orr x10, x4, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x10, x28, x11
-; GISEL-NEXT: ldp x26, x25, [sp, #336] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x10, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x11, xzr, x0, eq
+; GISEL-NEXT: orr x11, x5, x11
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x11, x23, x11
-; GISEL-NEXT: ldp x28, x27, [sp, #320] ; 16-byte Folded Reload
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x14, eq
+; GISEL-NEXT: csel x11, xzr, x7, eq
+; GISEL-NEXT: orr x11, x23, x11
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x11, x15, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x16, eq
+; GISEL-NEXT: csel x11, xzr, x24, eq
+; GISEL-NEXT: orr x11, x15, x11
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x11, x21, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x30, eq
+; GISEL-NEXT: csel x11, xzr, x16, eq
+; GISEL-NEXT: orr x11, x3, x11
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x11, x24, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x11, xzr, x2, eq
+; GISEL-NEXT: orr x11, x21, x11
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x11, x4, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x11, xzr, x5, eq
+; GISEL-NEXT: csel x11, xzr, x25, eq
+; GISEL-NEXT: orr x11, x27, x11
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: orr x11, x6, x11
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: ldr x11, [sp, #208] ; 8-byte Reload
-; GISEL-NEXT: csel x10, x20, x10, eq
+; GISEL-NEXT: csel x10, x28, x10, eq
; GISEL-NEXT: cmp x9, #8
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #9
@@ -3266,37 +3210,37 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x10, x11, x10, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x11, xzr, x0, eq
+; GISEL-NEXT: orr x11, x5, x11
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x11, x23, x11
; GISEL-NEXT: csel x11, x11, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x1, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: csel x13, xzr, x24, eq
+; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: csel x13, xzr, x16, eq
+; GISEL-NEXT: orr x13, x3, x13
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x13, xzr, x2, eq
+; GISEL-NEXT: orr x13, x21, x13
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x27, x13
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: orr x13, x6, x13
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: ldr x13, [sp, #216] ; 8-byte Reload
-; GISEL-NEXT: csel x11, x20, x11, eq
+; GISEL-NEXT: csel x11, x28, x11, eq
; GISEL-NEXT: cmp x9, #7
; GISEL-NEXT: csel x11, xzr, x11, eq
; GISEL-NEXT: cmp x9, #8
@@ -3318,33 +3262,33 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x11, x13, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x1, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: csel x13, x13, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x16, eq
+; GISEL-NEXT: csel x0, xzr, x24, eq
+; GISEL-NEXT: orr x0, x15, x0
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x0, x21, x0
; GISEL-NEXT: csel x13, x0, x13, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x30, eq
+; GISEL-NEXT: csel x0, xzr, x16, eq
+; GISEL-NEXT: orr x0, x3, x0
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x0, x24, x0
; GISEL-NEXT: csel x13, x0, x13, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x0, xzr, x2, eq
+; GISEL-NEXT: orr x0, x21, x0
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x0, x4, x0
; GISEL-NEXT: csel x13, x0, x13, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x5, eq
+; GISEL-NEXT: csel x0, xzr, x25, eq
+; GISEL-NEXT: orr x0, x27, x0
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: orr x0, x6, x0
; GISEL-NEXT: csel x13, x0, x13, eq
; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: ldr x0, [sp, #224] ; 8-byte Reload
-; GISEL-NEXT: csel x13, x20, x13, eq
+; GISEL-NEXT: csel x13, x28, x13, eq
; GISEL-NEXT: cmp x9, #6
; GISEL-NEXT: csel x13, xzr, x13, eq
; GISEL-NEXT: cmp x9, #7
@@ -3368,30 +3312,29 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x13, x0, x13, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x16, eq
+; GISEL-NEXT: csel x0, xzr, x24, eq
+; GISEL-NEXT: ldp x24, x23, [sp, #352] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x0, x15, x0
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: ldr x16, [sp, #272] ; 8-byte Reload
-; GISEL-NEXT: orr x0, x21, x0
-; GISEL-NEXT: ldp x22, x21, [sp, #368] ; 16-byte Folded Reload
; GISEL-NEXT: csel x0, x0, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x1, xzr, x30, eq
+; GISEL-NEXT: csel x1, xzr, x16, eq
+; GISEL-NEXT: orr x1, x3, x1
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x1, x24, x1
; GISEL-NEXT: csel x0, x1, x0, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x2, eq
+; GISEL-NEXT: orr x1, x21, x1
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x1, x4, x1
; GISEL-NEXT: csel x0, x1, x0, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x1, xzr, x5, eq
+; GISEL-NEXT: csel x1, xzr, x25, eq
+; GISEL-NEXT: orr x1, x27, x1
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: orr x1, x6, x1
; GISEL-NEXT: csel x0, x1, x0, eq
; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: ldr x1, [sp, #240] ; 8-byte Reload
-; GISEL-NEXT: csel x0, x20, x0, eq
+; GISEL-NEXT: csel x0, x28, x0, eq
; GISEL-NEXT: cmp x9, #5
; GISEL-NEXT: csel x0, xzr, x0, eq
; GISEL-NEXT: cmp x9, #6
@@ -3417,25 +3360,24 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x0, x1, x0, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x1, xzr, x30, eq
+; GISEL-NEXT: csel x1, xzr, x16, eq
+; GISEL-NEXT: ldr x16, [sp, #264] ; 8-byte Reload
+; GISEL-NEXT: orr x1, x3, x1
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x1, x24, x1
-; GISEL-NEXT: ldp x29, x30, [sp, #400] ; 16-byte Folded Reload
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x2, eq
+; GISEL-NEXT: csel x4, xzr, x2, eq
+; GISEL-NEXT: orr x4, x21, x4
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x3, x4, x3
-; GISEL-NEXT: ldp x24, x23, [sp, #352] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: csel x4, xzr, x25, eq
+; GISEL-NEXT: orr x4, x27, x4
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: orr x3, x6, x3
-; GISEL-NEXT: csel x1, x3, x1, eq
+; GISEL-NEXT: csel x1, x4, x1, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: ldr x3, [sp, #248] ; 8-byte Reload
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: ldr x4, [sp, #248] ; 8-byte Reload
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #4
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #5
@@ -3461,21 +3403,21 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x3, x3, x1, eq
+; GISEL-NEXT: csel x4, x4, x1, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x2, eq
+; GISEL-NEXT: orr x1, x21, x1
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x1, x4, x1
-; GISEL-NEXT: ldr x4, [sp, #160] ; 8-byte Reload
; GISEL-NEXT: csel x1, x1, xzr, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x2, xzr, x5, eq
+; GISEL-NEXT: csel x2, xzr, x25, eq
+; GISEL-NEXT: ldp x22, x21, [sp, #368] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x2, x27, x2
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: orr x2, x6, x2
; GISEL-NEXT: csel x1, x2, x1, eq
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: ldr x2, [sp, #264] ; 8-byte Reload
-; GISEL-NEXT: csel x1, x20, x1, eq
+; GISEL-NEXT: ldr x2, [sp, #256] ; 8-byte Reload
+; GISEL-NEXT: csel x1, x28, x1, eq
; GISEL-NEXT: cmp x9, #3
; GISEL-NEXT: csel x1, xzr, x1, eq
; GISEL-NEXT: cmp x9, #4
@@ -3505,13 +3447,13 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x2, x2, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x1, [sp, #256] ; 8-byte Reload
-; GISEL-NEXT: csel x15, xzr, x5, eq
+; GISEL-NEXT: csel x15, xzr, x25, eq
+; GISEL-NEXT: ldp x3, x1, [sp, #152] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x15, x27, x15
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: orr x15, x6, x15
; GISEL-NEXT: csel x15, x15, xzr, eq
; GISEL-NEXT: cmp x9, #1
-; GISEL-NEXT: csel x15, x20, x15, eq
+; GISEL-NEXT: csel x15, x28, x15, eq
; GISEL-NEXT: cmp x9, #2
; GISEL-NEXT: csel x15, xzr, x15, eq
; GISEL-NEXT: cmp x9, #3
@@ -3543,52 +3485,53 @@ define void @test_lshr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x15, x16, x15, eq
; GISEL-NEXT: cmp x9, #0
-; GISEL-NEXT: ldr x16, [sp, #288] ; 8-byte Reload
-; GISEL-NEXT: csel x14, x20, xzr, eq
+; GISEL-NEXT: csel x14, x28, xzr, eq
; GISEL-NEXT: cmp x9, #1
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: ldr x16, [sp, #280] ; 8-byte Reload
; GISEL-NEXT: cmp x9, #2
-; GISEL-NEXT: stp x17, x12, [x16, #48]
; GISEL-NEXT: csel x14, xzr, x14, eq
; GISEL-NEXT: cmp x9, #3
-; GISEL-NEXT: stp x10, x11, [x16, #64]
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: stp x17, x12, [x16, #48]
; GISEL-NEXT: cmp x9, #4
-; GISEL-NEXT: stp x4, x1, [x16]
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: stp x10, x11, [x16, #64]
; GISEL-NEXT: cmp x9, #5
-; GISEL-NEXT: ldr x4, [sp, #232] ; 8-byte Reload
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: stp x3, x1, [x16]
; GISEL-NEXT: cmp x9, #6
-; GISEL-NEXT: ldr x1, [sp, #304] ; 8-byte Reload
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: ldr x3, [sp, #232] ; 8-byte Reload
; GISEL-NEXT: cmp x9, #7
-; GISEL-NEXT: stp x13, x0, [x16, #80]
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: stp x13, x0, [x16, #80]
; GISEL-NEXT: cmp x9, #8
-; GISEL-NEXT: stp x4, x1, [x16, #16]
; GISEL-NEXT: csel x14, xzr, x14, eq
+; GISEL-NEXT: stp x4, x2, [x16, #96]
; GISEL-NEXT: cmp x9, #9
-; GISEL-NEXT: ldr x1, [sp, #184] ; 8-byte Reload
; GISEL-NEXT: csel x12, xzr, x14, eq
; GISEL-NEXT: cmp x9, #10
-; GISEL-NEXT: stp x3, x2, [x16, #96]
; GISEL-NEXT: csel x10, xzr, x12, eq
; GISEL-NEXT: cmp x9, #11
-; GISEL-NEXT: stp x19, x1, [x16, #32]
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #12
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #13
; GISEL-NEXT: csel x10, xzr, x10, eq
+; GISEL-NEXT: ldp x1, x5, [sp, #304] ; 16-byte Folded Reload
; GISEL-NEXT: cmp x9, #14
; GISEL-NEXT: csel x10, xzr, x10, eq
; GISEL-NEXT: cmp x9, #15
; GISEL-NEXT: csel x9, xzr, x10, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: ldr x8, [sp, #280] ; 8-byte Reload
+; GISEL-NEXT: ldr x8, [sp, #272] ; 8-byte Reload
+; GISEL-NEXT: stp x19, x1, [x16, #32]
; GISEL-NEXT: ldp x20, x19, [sp, #384] ; 16-byte Folded Reload
+; GISEL-NEXT: ldp x26, x25, [sp, #336] ; 16-byte Folded Reload
; GISEL-NEXT: csel x8, x8, x9, eq
+; GISEL-NEXT: ldp x28, x27, [sp, #320] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x3, x5, [x16, #16]
; GISEL-NEXT: stp x15, x8, [x16, #112]
; GISEL-NEXT: add sp, sp, #416
; GISEL-NEXT: ret
@@ -3735,14 +3678,14 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
;
; GISEL-LABEL: test_ashr_i1024:
; GISEL: ; %bb.0: ; %entry
-; GISEL-NEXT: sub sp, sp, #432
-; GISEL-NEXT: stp x28, x27, [sp, #336] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x26, x25, [sp, #352] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x24, x23, [sp, #368] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x22, x21, [sp, #384] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x20, x19, [sp, #400] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x29, x30, [sp, #416] ; 16-byte Folded Spill
-; GISEL-NEXT: .cfi_def_cfa_offset 432
+; GISEL-NEXT: sub sp, sp, #448
+; GISEL-NEXT: stp x28, x27, [sp, #352] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x26, x25, [sp, #368] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x24, x23, [sp, #384] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x22, x21, [sp, #400] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x20, x19, [sp, #416] ; 16-byte Folded Spill
+; GISEL-NEXT: stp x29, x30, [sp, #432] ; 16-byte Folded Spill
+; GISEL-NEXT: .cfi_def_cfa_offset 448
; GISEL-NEXT: .cfi_offset w30, -8
; GISEL-NEXT: .cfi_offset w29, -16
; GISEL-NEXT: .cfi_offset w19, -24
@@ -3755,437 +3698,432 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: .cfi_offset w26, -80
; GISEL-NEXT: .cfi_offset w27, -88
; GISEL-NEXT: .cfi_offset w28, -96
-; GISEL-NEXT: str x0, [sp, #256] ; 8-byte Spill
+; GISEL-NEXT: str x0, [sp, #272] ; 8-byte Spill
; GISEL-NEXT: mov w8, w2
; GISEL-NEXT: mov w9, #64 ; =0x40
-; GISEL-NEXT: ldp x7, x0, [x1]
+; GISEL-NEXT: ldp x27, x0, [x1]
; GISEL-NEXT: and x15, x8, #0x3f
; GISEL-NEXT: sub x14, x9, x15
; GISEL-NEXT: ldr x28, [x1, #120]
; GISEL-NEXT: lsr x10, x8, #6
-; GISEL-NEXT: ldp x16, x17, [x1, #16]
+; GISEL-NEXT: ldp x17, x16, [x1, #16]
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: lsl x9, x0, x14
-; GISEL-NEXT: lsr x12, x7, x15
+; GISEL-NEXT: lsr x12, x27, x15
; GISEL-NEXT: asr x11, x28, #63
-; GISEL-NEXT: lsr x20, x0, x15
-; GISEL-NEXT: str x0, [sp, #224] ; 8-byte Spill
-; GISEL-NEXT: lsl x27, x28, x14
+; GISEL-NEXT: lsr x3, x0, x15
+; GISEL-NEXT: str x0, [sp, #152] ; 8-byte Spill
; GISEL-NEXT: csel x9, xzr, x9, eq
-; GISEL-NEXT: lsl x19, x16, x14
-; GISEL-NEXT: cmp x10, #0
+; GISEL-NEXT: lsl x13, x17, x14
+; GISEL-NEXT: str x17, [sp, #224] ; 8-byte Spill
; GISEL-NEXT: orr x9, x12, x9
-; GISEL-NEXT: str x16, [sp, #200] ; 8-byte Spill
-; GISEL-NEXT: lsr x2, x16, x15
+; GISEL-NEXT: cmp x10, #0
+; GISEL-NEXT: lsr x25, x17, x15
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsl x30, x17, x14
-; GISEL-NEXT: csel x12, xzr, x19, eq
+; GISEL-NEXT: str x13, [sp, #136] ; 8-byte Spill
+; GISEL-NEXT: csel x12, xzr, x13, eq
+; GISEL-NEXT: lsl x21, x16, x14
+; GISEL-NEXT: lsr x20, x16, x15
+; GISEL-NEXT: orr x12, x3, x12
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: lsr x25, x17, x15
-; GISEL-NEXT: orr x12, x20, x12
-; GISEL-NEXT: ldp x13, x16, [x1, #32]
+; GISEL-NEXT: str x16, [sp, #200] ; 8-byte Spill
+; GISEL-NEXT: ldp x13, x17, [x1, #32]
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x17, [sp, #176] ; 8-byte Spill
-; GISEL-NEXT: csel x12, xzr, x30, eq
+; GISEL-NEXT: str x28, [sp, #264] ; 8-byte Spill
+; GISEL-NEXT: csel x12, xzr, x21, eq
+; GISEL-NEXT: str x25, [sp, #64] ; 8-byte Spill
+; GISEL-NEXT: lsl x7, x13, x14
+; GISEL-NEXT: orr x12, x25, x12
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: str x2, [sp, #80] ; 8-byte Spill
-; GISEL-NEXT: lsl x24, x13, x14
-; GISEL-NEXT: orr x12, x2, x12
-; GISEL-NEXT: str x13, [sp, #160] ; 8-byte Spill
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x21, x13, x15
-; GISEL-NEXT: csel x12, xzr, x24, eq
-; GISEL-NEXT: lsl x17, x16, x14
+; GISEL-NEXT: stp x13, x17, [sp, #160] ; 16-byte Folded Spill
+; GISEL-NEXT: csel x12, xzr, x7, eq
+; GISEL-NEXT: lsr x6, x13, x15
+; GISEL-NEXT: lsl x0, x17, x14
+; GISEL-NEXT: orr x12, x20, x12
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x12, x25, x12
-; GISEL-NEXT: ldp x13, x0, [x1, #48]
+; GISEL-NEXT: lsr x17, x17, x15
+; GISEL-NEXT: ldp x16, x13, [x1, #48]
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x17, [sp, #120] ; 8-byte Spill
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: str x0, [sp, #344] ; 8-byte Spill
+; GISEL-NEXT: csel x12, xzr, x0, eq
+; GISEL-NEXT: stp x20, x7, [sp, #24] ; 16-byte Folded Spill
+; GISEL-NEXT: lsl x0, x16, x14
+; GISEL-NEXT: orr x12, x6, x12
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: str x16, [sp, #136] ; 8-byte Spill
-; GISEL-NEXT: lsl x17, x13, x14
-; GISEL-NEXT: orr x12, x21, x12
-; GISEL-NEXT: lsr x16, x16, x15
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x13, x0, [sp, #144] ; 16-byte Folded Spill
-; GISEL-NEXT: csel x12, xzr, x17, eq
-; GISEL-NEXT: str x16, [sp, #112] ; 8-byte Spill
-; GISEL-NEXT: lsr x6, x13, x15
-; GISEL-NEXT: orr x12, x16, x12
-; GISEL-NEXT: ldp x16, x13, [x1, #64]
-; GISEL-NEXT: str x17, [sp, #304] ; 8-byte Spill
+; GISEL-NEXT: lsl x2, x13, x14
+; GISEL-NEXT: csel x12, xzr, x0, eq
+; GISEL-NEXT: stp x16, x13, [sp, #176] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x12, x17, x12
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: lsl x17, x0, x14
+; GISEL-NEXT: stp x17, x0, [sp, #328] ; 16-byte Folded Spill
+; GISEL-NEXT: mov x0, x13
; GISEL-NEXT: csel x9, x12, x9, eq
+; GISEL-NEXT: lsr x13, x16, x15
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x28, [sp, #248] ; 8-byte Spill
-; GISEL-NEXT: csel x12, xzr, x17, eq
-; GISEL-NEXT: lsl x2, x16, x14
+; GISEL-NEXT: str x2, [sp, #320] ; 8-byte Spill
+; GISEL-NEXT: lsr x16, x0, x15
+; GISEL-NEXT: csel x12, xzr, x2, eq
+; GISEL-NEXT: str x13, [sp, #128] ; 8-byte Spill
+; GISEL-NEXT: orr x12, x13, x12
+; GISEL-NEXT: ldp x17, x13, [x1, #64]
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x12, x6, x12
-; GISEL-NEXT: str x16, [sp, #168] ; 8-byte Spill
-; GISEL-NEXT: lsl x3, x11, x14
-; GISEL-NEXT: stp x2, x17, [sp, #288] ; 16-byte Folded Spill
-; GISEL-NEXT: mov x17, x16
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x16, x0, x15
-; GISEL-NEXT: str x13, [sp, #184] ; 8-byte Spill
+; GISEL-NEXT: lsl x2, x17, x14
+; GISEL-NEXT: lsl x0, x13, x14
+; GISEL-NEXT: str x13, [sp, #208] ; 8-byte Spill
+; GISEL-NEXT: str x17, [sp, #192] ; 8-byte Spill
; GISEL-NEXT: csel x12, xzr, x2, eq
-; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: lsr x0, x17, x15
+; GISEL-NEXT: stp x16, x2, [sp, #112] ; 16-byte Folded Spill
; GISEL-NEXT: orr x12, x16, x12
-; GISEL-NEXT: str x30, [sp, #40] ; 8-byte Spill
-; GISEL-NEXT: csel x9, x12, x9, eq
-; GISEL-NEXT: lsl x12, x13, x14
-; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x0, [sp, #104] ; 8-byte Spill
-; GISEL-NEXT: stp x12, x16, [sp, #272] ; 16-byte Folded Spill
+; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: mov x16, x13
-; GISEL-NEXT: csel x17, xzr, x12, eq
; GISEL-NEXT: ldp x13, x5, [x1, #80]
+; GISEL-NEXT: csel x9, x12, x9, eq
+; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: lsr x12, x17, x15
+; GISEL-NEXT: csel x17, xzr, x0, eq
+; GISEL-NEXT: stp x12, x0, [sp, #304] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x17, x12, x17
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x17, x0, x17
-; GISEL-NEXT: stp x25, x24, [sp, #8] ; 16-byte Folded Spill
; GISEL-NEXT: csel x17, x17, x9, eq
+; GISEL-NEXT: lsl x0, x13, x14
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: lsr x9, x16, x15
-; GISEL-NEXT: lsl x0, x13, x14
-; GISEL-NEXT: str x13, [sp, #192] ; 8-byte Spill
-; GISEL-NEXT: lsl x23, x5, x14
-; GISEL-NEXT: lsr x12, x13, x15
+; GISEL-NEXT: str x13, [sp, #216] ; 8-byte Spill
+; GISEL-NEXT: lsl x26, x5, x14
; GISEL-NEXT: csel x4, xzr, x0, eq
-; GISEL-NEXT: stp x9, x0, [sp, #88] ; 16-byte Folded Spill
-; GISEL-NEXT: cmp x10, #9
+; GISEL-NEXT: lsr x30, x13, x15
+; GISEL-NEXT: str x0, [sp, #104] ; 8-byte Spill
; GISEL-NEXT: orr x4, x9, x4
-; GISEL-NEXT: ldp x9, x13, [x1, #96]
+; GISEL-NEXT: cmp x10, #9
+; GISEL-NEXT: str x9, [sp, #296] ; 8-byte Spill
+; GISEL-NEXT: ldp x12, x13, [x1, #96]
; GISEL-NEXT: csel x17, x4, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x23, [sp, #264] ; 8-byte Spill
-; GISEL-NEXT: csel x4, xzr, x23, eq
+; GISEL-NEXT: lsr x9, x5, x15
+; GISEL-NEXT: csel x4, xzr, x26, eq
+; GISEL-NEXT: orr x4, x30, x4
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: orr x4, x12, x4
-; GISEL-NEXT: lsl x16, x9, x14
-; GISEL-NEXT: stp x5, x9, [sp, #208] ; 16-byte Folded Spill
+; GISEL-NEXT: lsl x24, x12, x14
; GISEL-NEXT: csel x17, x4, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x16, x12, [sp, #64] ; 16-byte Folded Spill
-; GISEL-NEXT: mov x12, x9
-; GISEL-NEXT: lsr x9, x5, x15
-; GISEL-NEXT: csel x4, xzr, x16, eq
; GISEL-NEXT: lsl x16, x13, x14
-; GISEL-NEXT: cmp x10, #11
+; GISEL-NEXT: csel x4, xzr, x24, eq
+; GISEL-NEXT: lsr x23, x12, x15
+; GISEL-NEXT: lsr x19, x13, x15
; GISEL-NEXT: orr x4, x9, x4
-; GISEL-NEXT: lsr x12, x12, x15
-; GISEL-NEXT: ldr x5, [sp, #88] ; 8-byte Reload
-; GISEL-NEXT: stp x16, x9, [sp, #48] ; 16-byte Folded Spill
-; GISEL-NEXT: ldr x9, [x1, #112]
+; GISEL-NEXT: cmp x10, #11
+; GISEL-NEXT: stp x16, x9, [sp, #88] ; 16-byte Folded Spill
; GISEL-NEXT: csel x17, x4, x17, eq
+; GISEL-NEXT: ldr x9, [x1, #112]
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: csel x1, xzr, x16, eq
-; GISEL-NEXT: lsl x16, x9, x14
+; GISEL-NEXT: stp x5, x12, [sp, #232] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x1, x23, x1
; GISEL-NEXT: cmp x10, #12
-; GISEL-NEXT: orr x1, x12, x1
-; GISEL-NEXT: stp x13, x9, [sp, #232] ; 16-byte Folded Spill
-; GISEL-NEXT: stp x16, x12, [sp, #320] ; 16-byte Folded Spill
-; GISEL-NEXT: mov x12, x9
+; GISEL-NEXT: lsl x16, x9, x14
; GISEL-NEXT: csel x1, x1, x17, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x9, x13, x15
-; GISEL-NEXT: lsr x26, x12, x15
+; GISEL-NEXT: mov x12, x9
; GISEL-NEXT: csel x17, xzr, x16, eq
+; GISEL-NEXT: str x16, [sp, #288] ; 8-byte Spill
+; GISEL-NEXT: lsl x16, x28, x14
+; GISEL-NEXT: stp x13, x9, [sp, #248] ; 16-byte Folded Spill
+; GISEL-NEXT: orr x13, x19, x17
; GISEL-NEXT: cmp x10, #13
-; GISEL-NEXT: orr x13, x9, x17
-; GISEL-NEXT: str x9, [sp, #312] ; 8-byte Spill
-; GISEL-NEXT: mov x9, x28
; GISEL-NEXT: csel x13, x13, x1, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: lsr x22, x9, x15
-; GISEL-NEXT: csel x28, xzr, x27, eq
+; GISEL-NEXT: lsr x12, x12, x15
+; GISEL-NEXT: mov x9, x28
+; GISEL-NEXT: csel x28, xzr, x16, eq
+; GISEL-NEXT: lsl x14, x11, x14
+; GISEL-NEXT: orr x28, x12, x28
; GISEL-NEXT: cmp x10, #14
-; GISEL-NEXT: orr x28, x26, x28
-; GISEL-NEXT: ldp x0, x16, [sp, #112] ; 16-byte Folded Reload
+; GISEL-NEXT: stp x12, x16, [sp, #72] ; 16-byte Folded Spill
; GISEL-NEXT: csel x12, x28, x13, eq
+; GISEL-NEXT: lsr x22, x9, x15
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x22, x3, [sp, #24] ; 16-byte Folded Spill
-; GISEL-NEXT: csel x28, xzr, x3, eq
-; GISEL-NEXT: cmp x10, #15
+; GISEL-NEXT: csel x28, xzr, x14, eq
+; GISEL-NEXT: ldp x13, x0, [sp, #336] ; 16-byte Folded Reload
; GISEL-NEXT: orr x28, x22, x28
-; GISEL-NEXT: ldp x2, x13, [sp, #296] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x10, #15
+; GISEL-NEXT: ldr x1, [sp, #296] ; 8-byte Reload
; GISEL-NEXT: csel x9, x28, x12, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: mov x28, x24
-; GISEL-NEXT: csel x9, x7, x9, eq
-; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x7, [sp, #80] ; 8-byte Reload
-; GISEL-NEXT: str x9, [sp, #128] ; 8-byte Spill
-; GISEL-NEXT: csel x9, xzr, x19, eq
+; GISEL-NEXT: mov x28, x21
+; GISEL-NEXT: csel x9, x27, x9, eq
+; GISEL-NEXT: tst x8, #0x3f
+; GISEL-NEXT: mov x27, x20
+; GISEL-NEXT: str x9, [sp, #144] ; 8-byte Spill
+; GISEL-NEXT: ldr x9, [sp, #136] ; 8-byte Reload
+; GISEL-NEXT: mov x15, x14
+; GISEL-NEXT: ldp x2, x16, [sp, #320] ; 16-byte Folded Reload
+; GISEL-NEXT: str x14, [sp, #280] ; 8-byte Spill
+; GISEL-NEXT: csel x9, xzr, x9, eq
+; GISEL-NEXT: ldp x5, x12, [sp, #304] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x9, x3, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x20, x9
-; GISEL-NEXT: ldr x12, [sp, #272] ; 8-byte Reload
+; GISEL-NEXT: stp x24, x23, [sp, #40] ; 16-byte Folded Spill
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x30, eq
+; GISEL-NEXT: str x19, [sp, #56] ; 8-byte Spill
+; GISEL-NEXT: csel x3, xzr, x21, eq
+; GISEL-NEXT: ldp x4, x21, [sp, #104] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x3, x25, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: mov x30, x25
-; GISEL-NEXT: orr x20, x7, x20
-; GISEL-NEXT: ldp x4, x19, [sp, #96] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x25, x7
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x24, eq
+; GISEL-NEXT: str x22, [sp, #16] ; 8-byte Spill
+; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: mov x7, x6
+; GISEL-NEXT: orr x3, x20, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: mov x24, x6
-; GISEL-NEXT: orr x20, x25, x20
-; GISEL-NEXT: mov x25, x21
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x16, eq
+; GISEL-NEXT: csel x3, xzr, x0, eq
+; GISEL-NEXT: ldp x14, x17, [sp, #88] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x20, x21, x20
-; GISEL-NEXT: ldp x15, x14, [sp, #64] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
+; GISEL-NEXT: csel x3, xzr, x13, eq
+; GISEL-NEXT: ldp x20, x6, [sp, #120] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x20, x0, x20
-; GISEL-NEXT: ldp x1, x17, [sp, #48] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x2, eq
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x20, x6, x20
-; GISEL-NEXT: ldp x21, x6, [sp, #280] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x6, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x20, x21, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x12, eq
+; GISEL-NEXT: csel x3, xzr, x12, eq
+; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x20, x19, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x4, eq
+; GISEL-NEXT: csel x3, xzr, x4, eq
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x20, x5, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x26, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: ldr x23, [sp, #328] ; 8-byte Reload
-; GISEL-NEXT: orr x20, x14, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x15, eq
+; GISEL-NEXT: csel x3, xzr, x24, eq
+; GISEL-NEXT: ldr x24, [sp, #288] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x17, x3
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: orr x20, x17, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x1, eq
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x23, x3
; GISEL-NEXT: cmp x10, #11
-; GISEL-NEXT: orr x20, x23, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
-; GISEL-NEXT: ldp x23, x20, [sp, #312] ; 16-byte Folded Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x20, eq
+; GISEL-NEXT: csel x3, xzr, x24, eq
+; GISEL-NEXT: orr x3, x19, x3
+; GISEL-NEXT: ldp x23, x19, [sp, #72] ; 16-byte Folded Reload
; GISEL-NEXT: cmp x10, #12
-; GISEL-NEXT: orr x20, x23, x20
-; GISEL-NEXT: mov x23, x26
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x27, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: orr x3, x23, x3
; GISEL-NEXT: cmp x10, #13
-; GISEL-NEXT: orr x20, x26, x20
-; GISEL-NEXT: ldr x26, [sp, #264] ; 8-byte Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x15, eq
+; GISEL-NEXT: ldr x15, [sp, #152] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x22, x3
; GISEL-NEXT: cmp x10, #14
-; GISEL-NEXT: ldr x3, [sp, #224] ; 8-byte Reload
-; GISEL-NEXT: orr x20, x22, x20
-; GISEL-NEXT: mov x22, x23
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x9, x3, x9, eq
+; GISEL-NEXT: csel x9, x15, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x3, x16
-; GISEL-NEXT: str x9, [sp, #224] ; 8-byte Spill
-; GISEL-NEXT: ldr x9, [sp, #40] ; 8-byte Reload
-; GISEL-NEXT: csel x9, xzr, x9, eq
+; GISEL-NEXT: ldr x15, [sp, #64] ; 8-byte Reload
+; GISEL-NEXT: str x9, [sp, #152] ; 8-byte Spill
+; GISEL-NEXT: csel x9, xzr, x28, eq
+; GISEL-NEXT: orr x9, x15, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x7, x9
-; GISEL-NEXT: ldr x7, [sp, #312] ; 8-byte Reload
+; GISEL-NEXT: mov x15, x13
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x28, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: ldp x25, x28, [sp, #40] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x3, x27, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: mov x28, x21
-; GISEL-NEXT: orr x20, x30, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x27, x17
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x16, eq
+; GISEL-NEXT: csel x3, xzr, x0, eq
+; GISEL-NEXT: mov x0, x16
+; GISEL-NEXT: orr x3, x7, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: mov x16, x0
-; GISEL-NEXT: orr x20, x25, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
+; GISEL-NEXT: csel x3, xzr, x13, eq
+; GISEL-NEXT: mov x13, x5
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x20, x0, x20
-; GISEL-NEXT: mov x0, x19
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x16, x4
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x2, eq
+; GISEL-NEXT: ldr x2, [sp, #224] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: mov x2, x4
-; GISEL-NEXT: orr x20, x24, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x6, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: mov x6, x5
-; GISEL-NEXT: orr x20, x21, x20
-; GISEL-NEXT: mov x21, x25
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x12, eq
+; GISEL-NEXT: csel x3, xzr, x12, eq
+; GISEL-NEXT: mov x12, x1
+; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: ldr x12, [sp, #200] ; 8-byte Reload
-; GISEL-NEXT: orr x20, x19, x20
-; GISEL-NEXT: mov x19, x27
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x5, [sp, #56] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x4, eq
+; GISEL-NEXT: csel x3, xzr, x4, eq
+; GISEL-NEXT: mov x4, x7
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x20, x5, x20
-; GISEL-NEXT: ldp x30, x4, [sp, #320] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x1, x23
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: mov x5, x3
-; GISEL-NEXT: csel x20, xzr, x26, eq
+; GISEL-NEXT: csel x3, xzr, x26, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x20, x14, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x15, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: orr x3, x17, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: orr x20, x17, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x17, x19
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x1, eq
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: orr x20, x4, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x30, eq
+; GISEL-NEXT: csel x3, xzr, x24, eq
+; GISEL-NEXT: mov x24, x25
+; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: cmp x10, #11
-; GISEL-NEXT: orr x20, x7, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x27, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: ldr x19, [sp, #280] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x23, x3
; GISEL-NEXT: cmp x10, #12
-; GISEL-NEXT: orr x20, x23, x20
-; GISEL-NEXT: ldp x27, x23, [sp, #24] ; 16-byte Folded Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: orr x3, x22, x3
; GISEL-NEXT: cmp x10, #13
-; GISEL-NEXT: orr x20, x27, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x22, [sp, #344] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #14
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x9, x12, x9, eq
+; GISEL-NEXT: csel x9, x2, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: str x9, [sp, #200] ; 8-byte Spill
-; GISEL-NEXT: ldp x12, x9, [sp, #8] ; 16-byte Folded Reload
+; GISEL-NEXT: str x9, [sp, #224] ; 8-byte Spill
+; GISEL-NEXT: ldp x2, x9, [sp, #24] ; 16-byte Folded Reload
; GISEL-NEXT: csel x9, xzr, x9, eq
+; GISEL-NEXT: orr x9, x2, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x12, x9
-; GISEL-NEXT: ldr x12, [sp, #176] ; 8-byte Reload
+; GISEL-NEXT: mov x2, x30
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x22, eq
+; GISEL-NEXT: orr x3, x7, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x20, x25, x20
-; GISEL-NEXT: ldr x25, [sp, #272] ; 8-byte Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
-; GISEL-NEXT: ldp x3, x13, [sp, #288] ; 16-byte Folded Reload
-; GISEL-NEXT: orr x20, x16, x20
+; GISEL-NEXT: csel x3, xzr, x15, eq
+; GISEL-NEXT: ldp x7, x23, [sp, #312] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x3, x0, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
+; GISEL-NEXT: csel x3, xzr, x23, eq
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x20, x24, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x20, x28, x20
-; GISEL-NEXT: mov x28, x16
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x25, eq
+; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: orr x3, x13, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x20, x0, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x13, [sp, #16] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x16, eq
+; GISEL-NEXT: orr x3, x12, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x20, x6, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x12, [sp, #200] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x26, eq
+; GISEL-NEXT: csel x3, xzr, x26, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: mov x26, x14
-; GISEL-NEXT: orr x20, x14, x20
-; GISEL-NEXT: mov x14, x15
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x30, [sp, #304] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x15, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: ldr x25, [sp, #288] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x27, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: mov x15, x17
-; GISEL-NEXT: orr x20, x17, x20
-; GISEL-NEXT: mov x17, x1
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x1, eq
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: mov x1, x4
-; GISEL-NEXT: orr x20, x4, x20
-; GISEL-NEXT: mov x4, x30
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x30, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: ldr x30, [sp, #264] ; 8-byte Reload
-; GISEL-NEXT: orr x20, x7, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x19, eq
+; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #11
-; GISEL-NEXT: orr x20, x22, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: mov x19, x24
+; GISEL-NEXT: orr x3, x13, x3
; GISEL-NEXT: cmp x10, #12
-; GISEL-NEXT: orr x20, x27, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #13
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #14
@@ -4196,70 +4134,77 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
; GISEL-NEXT: ldr x12, [sp, #160] ; 8-byte Reload
-; GISEL-NEXT: str x9, [sp, #176] ; 8-byte Spill
-; GISEL-NEXT: csel x9, xzr, x5, eq
+; GISEL-NEXT: str x9, [sp, #200] ; 8-byte Spill
+; GISEL-NEXT: csel x9, xzr, x22, eq
+; GISEL-NEXT: mov x22, x16
+; GISEL-NEXT: orr x9, x4, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x21, x9
-; GISEL-NEXT: ldr x5, [sp, #304] ; 8-byte Reload
-; GISEL-NEXT: mov x21, x0
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x5, eq
+; GISEL-NEXT: csel x3, xzr, x15, eq
+; GISEL-NEXT: ldr x15, [sp, #144] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x0, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x20, x16, x20
-; GISEL-NEXT: mov x16, x24
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x0, x23
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
+; GISEL-NEXT: csel x3, xzr, x23, eq
+; GISEL-NEXT: mov x23, x28
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x20, x24, x20
-; GISEL-NEXT: ldr x24, [sp, #280] ; 8-byte Reload
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x20, x24, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x25, eq
+; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x20, x0, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x16, eq
+; GISEL-NEXT: ldr x16, [sp, #296] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x20, x6, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x30, eq
+; GISEL-NEXT: csel x3, xzr, x26, eq
+; GISEL-NEXT: orr x3, x2, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x20, x26, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x14, eq
+; GISEL-NEXT: csel x3, xzr, x24, eq
+; GISEL-NEXT: mov x24, x27
+; GISEL-NEXT: orr x3, x27, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x20, x15, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x27, x5
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x17, eq
+; GISEL-NEXT: mov x4, x27
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x20, x1, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x28, x13
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x4, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: orr x20, x7, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: ldr x5, [sp, #280] ; 8-byte Reload
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x19, eq
+; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: orr x20, x22, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: orr x3, x13, x3
; GISEL-NEXT: cmp x10, #11
-; GISEL-NEXT: orr x20, x27, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x13, x22
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #12
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #13
@@ -4271,67 +4216,66 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x12, [sp, #136] ; 8-byte Reload
-; GISEL-NEXT: str x9, [sp, #160] ; 8-byte Spill
-; GISEL-NEXT: csel x9, xzr, x5, eq
+; GISEL-NEXT: str x9, [sp, #344] ; 8-byte Spill
+; GISEL-NEXT: ldp x12, x9, [sp, #328] ; 16-byte Folded Reload
+; GISEL-NEXT: csel x9, xzr, x9, eq
+; GISEL-NEXT: orr x9, x12, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x28, x9
-; GISEL-NEXT: mov x28, x3
-; GISEL-NEXT: mov x5, x7
+; GISEL-NEXT: ldr x12, [sp, #168] ; 8-byte Reload
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x13, eq
+; GISEL-NEXT: csel x3, xzr, x0, eq
+; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x20, x16, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x20, x24, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x25, eq
+; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x20, x0, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x22, eq
+; GISEL-NEXT: mov x22, x26
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x20, x6, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x30, eq
+; GISEL-NEXT: csel x3, xzr, x26, eq
+; GISEL-NEXT: mov x26, x2
+; GISEL-NEXT: orr x3, x2, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x20, x26, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x14, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: orr x3, x24, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x20, x15, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x17, eq
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x23, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x20, x1, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x4, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: orr x3, x27, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x20, x7, x20
-; GISEL-NEXT: mov x7, x19
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: mov x27, x13
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x19, eq
+; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: mov x19, x22
-; GISEL-NEXT: orr x20, x22, x20
-; GISEL-NEXT: mov x22, x23
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x20, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: orr x20, x27, x20
-; GISEL-NEXT: csel x9, x20, x9, eq
+; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #11
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #12
@@ -4345,60 +4289,60 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x12, [sp, #144] ; 8-byte Reload
-; GISEL-NEXT: str x9, [sp, #304] ; 8-byte Spill
-; GISEL-NEXT: csel x9, xzr, x13, eq
+; GISEL-NEXT: ldr x12, [sp, #176] ; 8-byte Reload
+; GISEL-NEXT: str x9, [sp, #336] ; 8-byte Spill
+; GISEL-NEXT: csel x9, xzr, x0, eq
+; GISEL-NEXT: orr x9, x6, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x16, x9
-; GISEL-NEXT: mov x16, x0
+; GISEL-NEXT: mov x6, x7
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x3, eq
+; GISEL-NEXT: csel x3, xzr, x20, eq
+; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x3, x24, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: orr x3, x30, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x3, x21, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x2, eq
+; GISEL-NEXT: csel x3, xzr, x13, eq
+; GISEL-NEXT: mov x13, x16
+; GISEL-NEXT: orr x3, x16, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x3, x6, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x30, eq
+; GISEL-NEXT: csel x3, xzr, x22, eq
+; GISEL-NEXT: orr x3, x2, x3
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x3, x26, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: csel x3, xzr, x19, eq
+; GISEL-NEXT: orr x3, x24, x3
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x3, x15, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: csel x3, xzr, x14, eq
+; GISEL-NEXT: orr x3, x23, x3
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x4, eq
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: orr x3, x4, x3
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x3, x5, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x3, x19, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x23, eq
+; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: orr x3, x27, x3
; GISEL-NEXT: csel x9, x3, x9, eq
; GISEL-NEXT: cmp x10, #10
-; GISEL-NEXT: mov x3, x2
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #11
; GISEL-NEXT: csel x9, x11, x9, eq
@@ -4411,53 +4355,53 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x20, x12, x9, eq
+; GISEL-NEXT: csel x7, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x12, [sp, #152] ; 8-byte Reload
-; GISEL-NEXT: csel x9, xzr, x28, eq
+; GISEL-NEXT: ldr x12, [sp, #184] ; 8-byte Reload
+; GISEL-NEXT: csel x9, xzr, x20, eq
+; GISEL-NEXT: mov x20, x6
+; GISEL-NEXT: orr x9, x21, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x24, x9
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x25, eq
+; GISEL-NEXT: csel x0, xzr, x6, eq
+; GISEL-NEXT: orr x0, x30, x0
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x0, x21, x0
-; GISEL-NEXT: mov x21, x6
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x2, eq
+; GISEL-NEXT: csel x0, xzr, x27, eq
+; GISEL-NEXT: orr x0, x13, x0
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x0, x6, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x30, eq
+; GISEL-NEXT: csel x0, xzr, x22, eq
+; GISEL-NEXT: orr x0, x2, x0
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x0, x26, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x14, eq
+; GISEL-NEXT: csel x0, xzr, x19, eq
+; GISEL-NEXT: orr x0, x24, x0
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x0, x15, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x17, eq
+; GISEL-NEXT: csel x0, xzr, x14, eq
+; GISEL-NEXT: orr x0, x23, x0
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x0, x1, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x4, eq
+; GISEL-NEXT: csel x0, xzr, x25, eq
+; GISEL-NEXT: orr x0, x4, x0
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x0, x5, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x7, eq
+; GISEL-NEXT: csel x0, xzr, x17, eq
+; GISEL-NEXT: orr x0, x1, x0
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x0, x19, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x23, eq
+; GISEL-NEXT: csel x0, xzr, x5, eq
+; GISEL-NEXT: orr x0, x28, x0
; GISEL-NEXT: cmp x10, #8
-; GISEL-NEXT: orr x0, x27, x0
; GISEL-NEXT: csel x9, x0, x9, eq
; GISEL-NEXT: cmp x10, #9
; GISEL-NEXT: csel x9, x11, x9, eq
@@ -4474,48 +4418,48 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x2, x12, x9, eq
+; GISEL-NEXT: csel x6, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x12, [sp, #168] ; 8-byte Reload
-; GISEL-NEXT: csel x9, xzr, x25, eq
+; GISEL-NEXT: ldr x12, [sp, #192] ; 8-byte Reload
+; GISEL-NEXT: csel x9, xzr, x20, eq
+; GISEL-NEXT: orr x9, x30, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x16, x9
-; GISEL-NEXT: ldr x16, [sp, #208] ; 8-byte Reload
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x3, eq
+; GISEL-NEXT: csel x13, xzr, x27, eq
+; GISEL-NEXT: ldp x29, x30, [sp, #432] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x13, x16, x13
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x13, x6, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x30, eq
+; GISEL-NEXT: csel x13, xzr, x22, eq
+; GISEL-NEXT: orr x13, x2, x13
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x13, x26, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x19, eq
+; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x13, x15, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x13, x1, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x4, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x13, x5, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x1, x13
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: orr x13, x28, x13
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: orr x13, x27, x13
; GISEL-NEXT: csel x9, x13, x9, eq
; GISEL-NEXT: cmp x10, #8
; GISEL-NEXT: csel x9, x11, x9, eq
@@ -4534,44 +4478,45 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: csel x6, x12, x9, eq
+; GISEL-NEXT: csel x20, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x9, xzr, x3, eq
+; GISEL-NEXT: csel x9, xzr, x27, eq
+; GISEL-NEXT: orr x9, x16, x9
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x9, x21, x9
+; GISEL-NEXT: ldr x16, [sp, #232] ; 8-byte Reload
; GISEL-NEXT: csel x9, x9, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x30, eq
-; GISEL-NEXT: cmp x10, #1
+; GISEL-NEXT: csel x12, xzr, x22, eq
; GISEL-NEXT: orr x12, x26, x12
+; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: csel x12, xzr, x19, eq
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x12, x15, x12
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: orr x12, x23, x12
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x12, x1, x12
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x4, eq
+; GISEL-NEXT: csel x12, xzr, x25, eq
+; GISEL-NEXT: orr x12, x4, x12
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x12, x5, x12
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x7, eq
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x1, x12
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x12, x19, x12
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x23, eq
+; GISEL-NEXT: csel x12, xzr, x5, eq
+; GISEL-NEXT: orr x12, x28, x12
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: orr x12, x27, x12
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: ldr x12, [sp, #184] ; 8-byte Reload
+; GISEL-NEXT: ldr x12, [sp, #208] ; 8-byte Reload
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x10, #8
; GISEL-NEXT: csel x9, x11, x9, eq
@@ -4592,39 +4537,38 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x9, x12, x9, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x30, eq
-; GISEL-NEXT: cmp x10, #0
+; GISEL-NEXT: csel x12, xzr, x22, eq
+; GISEL-NEXT: ldp x22, x21, [sp, #400] ; 16-byte Folded Reload
; GISEL-NEXT: orr x12, x26, x12
-; GISEL-NEXT: ldp x29, x30, [sp, #416] ; 16-byte Folded Reload
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: csel x13, xzr, x19, eq
+; GISEL-NEXT: orr x13, x24, x13
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x13, x15, x13
-; GISEL-NEXT: ldp x26, x25, [sp, #352] ; 16-byte Folded Reload
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: csel x13, xzr, x14, eq
+; GISEL-NEXT: orr x13, x23, x13
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x13, x1, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x4, eq
+; GISEL-NEXT: csel x13, xzr, x25, eq
+; GISEL-NEXT: orr x13, x4, x13
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x13, x5, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x7, eq
+; GISEL-NEXT: csel x13, xzr, x17, eq
+; GISEL-NEXT: orr x13, x1, x13
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: orr x13, x19, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x13, xzr, x23, eq
+; GISEL-NEXT: csel x13, xzr, x5, eq
+; GISEL-NEXT: orr x13, x28, x13
; GISEL-NEXT: cmp x10, #5
-; GISEL-NEXT: orr x13, x27, x13
; GISEL-NEXT: csel x12, x13, x12, eq
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: ldr x13, [sp, #192] ; 8-byte Reload
+; GISEL-NEXT: ldr x13, [sp, #216] ; 8-byte Reload
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #7
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4647,54 +4591,39 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x13, x13, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: csel x12, xzr, x19, eq
+; GISEL-NEXT: orr x12, x24, x12
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: ldr x14, [sp, #256] ; 8-byte Reload
-; GISEL-NEXT: orr x12, x15, x12
-; GISEL-NEXT: ldr x15, [sp, #128] ; 8-byte Reload
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: stp x9, x13, [x14, #72]
-; GISEL-NEXT: csel x0, xzr, x17, eq
+; GISEL-NEXT: csel x0, xzr, x14, eq
+; GISEL-NEXT: orr x0, x23, x0
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: str x15, [x14]
-; GISEL-NEXT: orr x0, x1, x0
-; GISEL-NEXT: ldr x15, [sp, #224] ; 8-byte Reload
-; GISEL-NEXT: stp x2, x6, [x14, #56]
; GISEL-NEXT: csel x12, x0, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x4, eq
+; GISEL-NEXT: csel x0, xzr, x25, eq
+; GISEL-NEXT: orr x0, x4, x0
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: str x15, [x14, #8]
-; GISEL-NEXT: orr x0, x5, x0
-; GISEL-NEXT: ldr x15, [sp, #200] ; 8-byte Reload
; GISEL-NEXT: csel x12, x0, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x7, eq
+; GISEL-NEXT: csel x0, xzr, x17, eq
+; GISEL-NEXT: orr x0, x1, x0
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: str x15, [x14, #16]
-; GISEL-NEXT: orr x0, x19, x0
-; GISEL-NEXT: ldr x15, [sp, #176] ; 8-byte Reload
; GISEL-NEXT: csel x12, x0, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x0, xzr, x23, eq
+; GISEL-NEXT: csel x0, xzr, x5, eq
+; GISEL-NEXT: orr x0, x28, x0
; GISEL-NEXT: cmp x10, #4
-; GISEL-NEXT: str x15, [x14, #24]
-; GISEL-NEXT: orr x0, x27, x0
-; GISEL-NEXT: ldr x15, [sp, #160] ; 8-byte Reload
; GISEL-NEXT: csel x12, x0, x12, eq
; GISEL-NEXT: cmp x10, #5
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #6
-; GISEL-NEXT: str x15, [x14, #32]
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #7
-; GISEL-NEXT: ldr x15, [sp, #304] ; 8-byte Reload
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #8
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #9
-; GISEL-NEXT: stp x15, x20, [x14, #40]
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #10
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4711,40 +4640,53 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x0, x16, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x16, [sp, #216] ; 8-byte Reload
-; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: ldr x16, [sp, #240] ; 8-byte Reload
+; GISEL-NEXT: csel x12, xzr, x14, eq
+; GISEL-NEXT: ldr x14, [sp, #272] ; 8-byte Reload
+; GISEL-NEXT: orr x12, x23, x12
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x12, x1, x12
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x4, eq
+; GISEL-NEXT: str x15, [x14]
+; GISEL-NEXT: csel x3, xzr, x25, eq
+; GISEL-NEXT: ldr x15, [sp, #152] ; 8-byte Reload
+; GISEL-NEXT: stp x9, x13, [x14, #72]
+; GISEL-NEXT: orr x3, x4, x3
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x3, x5, x3
+; GISEL-NEXT: stp x6, x20, [x14, #56]
; GISEL-NEXT: csel x12, x3, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x7, eq
+; GISEL-NEXT: str x15, [x14, #8]
+; GISEL-NEXT: csel x3, xzr, x17, eq
+; GISEL-NEXT: ldr x15, [sp, #224] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x1, x3
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x3, x19, x3
; GISEL-NEXT: csel x12, x3, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x3, xzr, x23, eq
+; GISEL-NEXT: str x15, [x14, #16]
+; GISEL-NEXT: csel x3, xzr, x5, eq
+; GISEL-NEXT: ldr x15, [sp, #200] ; 8-byte Reload
+; GISEL-NEXT: orr x3, x28, x3
; GISEL-NEXT: cmp x10, #3
-; GISEL-NEXT: orr x3, x27, x3
-; GISEL-NEXT: ldp x24, x23, [sp, #368] ; 16-byte Folded Reload
; GISEL-NEXT: csel x12, x3, x12, eq
; GISEL-NEXT: cmp x10, #4
+; GISEL-NEXT: str x15, [x14, #24]
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #5
+; GISEL-NEXT: ldr x15, [sp, #344] ; 8-byte Reload
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #6
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #7
+; GISEL-NEXT: str x15, [x14, #32]
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #8
+; GISEL-NEXT: ldr x15, [sp, #336] ; 8-byte Reload
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #9
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #10
+; GISEL-NEXT: stp x15, x7, [x14, #40]
; GISEL-NEXT: csel x12, x11, x12, eq
; GISEL-NEXT: cmp x10, #11
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4759,21 +4701,24 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x3, x16, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x16, [sp, #232] ; 8-byte Reload
-; GISEL-NEXT: csel x12, xzr, x4, eq
+; GISEL-NEXT: ldr x16, [sp, #248] ; 8-byte Reload
+; GISEL-NEXT: csel x12, xzr, x25, eq
+; GISEL-NEXT: ldp x20, x19, [sp, #416] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x12, x4, x12
; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: stp x0, x3, [x14, #88]
-; GISEL-NEXT: orr x12, x5, x12
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x4, xzr, x7, eq
+; GISEL-NEXT: csel x4, xzr, x17, eq
+; GISEL-NEXT: ldp x24, x23, [sp, #384] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x4, x1, x4
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x4, x19, x4
; GISEL-NEXT: csel x12, x4, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x4, xzr, x22, eq
+; GISEL-NEXT: csel x4, xzr, x5, eq
+; GISEL-NEXT: ldp x26, x25, [sp, #368] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x4, x28, x4
; GISEL-NEXT: cmp x10, #2
-; GISEL-NEXT: orr x4, x27, x4
; GISEL-NEXT: csel x12, x4, x12, eq
; GISEL-NEXT: cmp x10, #3
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4804,16 +4749,15 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x4, x16, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: ldr x16, [sp, #240] ; 8-byte Reload
-; GISEL-NEXT: csel x12, xzr, x7, eq
+; GISEL-NEXT: ldr x16, [sp, #256] ; 8-byte Reload
+; GISEL-NEXT: csel x12, xzr, x17, eq
+; GISEL-NEXT: orr x12, x1, x12
; GISEL-NEXT: cmp x10, #0
-; GISEL-NEXT: orr x12, x19, x12
-; GISEL-NEXT: ldp x20, x19, [sp, #400] ; 16-byte Folded Reload
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x17, xzr, x22, eq
+; GISEL-NEXT: csel x17, xzr, x5, eq
+; GISEL-NEXT: orr x17, x28, x17
; GISEL-NEXT: cmp x10, #1
-; GISEL-NEXT: orr x17, x27, x17
; GISEL-NEXT: csel x12, x17, x12, eq
; GISEL-NEXT: cmp x10, #2
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4846,11 +4790,10 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x8, #0
; GISEL-NEXT: csel x17, x16, x12, eq
; GISEL-NEXT: tst x8, #0x3f
-; GISEL-NEXT: csel x12, xzr, x22, eq
-; GISEL-NEXT: cmp x10, #0
+; GISEL-NEXT: csel x12, xzr, x5, eq
; GISEL-NEXT: stp x4, x17, [x14, #104]
-; GISEL-NEXT: orr x12, x27, x12
-; GISEL-NEXT: ldp x22, x21, [sp, #384] ; 16-byte Folded Reload
+; GISEL-NEXT: orr x12, x28, x12
+; GISEL-NEXT: cmp x10, #0
; GISEL-NEXT: csel x12, x12, x11, eq
; GISEL-NEXT: cmp x10, #1
; GISEL-NEXT: csel x12, x11, x12, eq
@@ -4883,11 +4826,11 @@ define void @test_ashr_i1024(ptr %result, ptr %input, i32 %shift) {
; GISEL-NEXT: cmp x10, #15
; GISEL-NEXT: csel x9, x11, x9, eq
; GISEL-NEXT: cmp x8, #0
-; GISEL-NEXT: ldr x8, [sp, #248] ; 8-byte Reload
-; GISEL-NEXT: ldp x28, x27, [sp, #336] ; 16-byte Folded Reload
+; GISEL-NEXT: ldr x8, [sp, #264] ; 8-byte Reload
+; GISEL-NEXT: ldp x28, x27, [sp, #352] ; 16-byte Folded Reload
; GISEL-NEXT: csel x8, x8, x9, eq
; GISEL-NEXT: str x8, [x14, #120]
-; GISEL-NEXT: add sp, sp, #432
+; GISEL-NEXT: add sp, sp, #448
; GISEL-NEXT: ret
entry:
%input_val = load i1024, ptr %input, align 128
diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
index d13556fa880b9..58f28fd2243e3 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
@@ -1215,9 +1215,9 @@ define i8 @uminv_v4i8(<4 x i8> %a) {
; CHECK-GI-NEXT: umov w11, v0.h[3]
; CHECK-GI-NEXT: and w12, w8, #0xff
; CHECK-GI-NEXT: cmp w12, w9, uxtb
-; CHECK-GI-NEXT: and w12, w10, #0xff
; CHECK-GI-NEXT: csel w8, w8, w9, lo
-; CHECK-GI-NEXT: cmp w12, w11, uxtb
+; CHECK-GI-NEXT: and w9, w10, #0xff
+; CHECK-GI-NEXT: cmp w9, w11, uxtb
; CHECK-GI-NEXT: csel w9, w10, w11, lo
; CHECK-GI-NEXT: and w10, w8, #0xff
; CHECK-GI-NEXT: cmp w10, w9, uxtb
@@ -1621,9 +1621,9 @@ define i8 @umaxv_v4i8(<4 x i8> %a) {
; CHECK-GI-NEXT: umov w11, v0.h[3]
; CHECK-GI-NEXT: and w12, w8, #0xff
; CHECK-GI-NEXT: cmp w12, w9, uxtb
-; CHECK-GI-NEXT: and w12, w10, #0xff
; CHECK-GI-NEXT: csel w8, w8, w9, hi
-; CHECK-GI-NEXT: cmp w12, w11, uxtb
+; CHECK-GI-NEXT: and w9, w10, #0xff
+; CHECK-GI-NEXT: cmp w9, w11, uxtb
; CHECK-GI-NEXT: csel w9, w10, w11, hi
; CHECK-GI-NEXT: and w10, w8, #0xff
; CHECK-GI-NEXT: cmp w10, w9, uxtb
diff --git a/llvm/test/CodeGen/AArch64/active_lane_mask.ll b/llvm/test/CodeGen/AArch64/active_lane_mask.ll
index f0d7532cb7047..faf215242bea7 100644
--- a/llvm/test/CodeGen/AArch64/active_lane_mask.ll
+++ b/llvm/test/CodeGen/AArch64/active_lane_mask.ll
@@ -159,8 +159,8 @@ define <vscale x 32 x i1> @lane_mask_nxv32i1_i8(i8 %index, i8 %TC) {
; CHECK-NEXT: and w11, w1, #0xff
; CHECK-NEXT: cmp w8, #255
; CHECK-NEXT: csel w8, w8, w10, lo
-; CHECK-NEXT: whilelo p0.b, w9, w11
; CHECK-NEXT: whilelo p1.b, w8, w11
+; CHECK-NEXT: whilelo p0.b, w9, w11
; CHECK-NEXT: ret
%active.lane.mask = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i8(i8 %index, i8 %TC)
ret <vscale x 32 x i1> %active.lane.mask
diff --git a/llvm/test/CodeGen/AArch64/addsub.ll b/llvm/test/CodeGen/AArch64/addsub.ll
index b8e5884866476..add959a6a5f75 100644
--- a/llvm/test/CodeGen/AArch64/addsub.ll
+++ b/llvm/test/CodeGen/AArch64/addsub.ll
@@ -511,20 +511,20 @@ define i1 @reject_non_eqne_csinc(i32 %0) {
define i32 @accept_csel(i32 %0) {
; CHECK-SD-LABEL: accept_csel:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub w9, w0, #273, lsl #12 // =1118208
; CHECK-SD-NEXT: mov w8, #17 // =0x11
+; CHECK-SD-NEXT: sub w9, w0, #273, lsl #12 // =1118208
+; CHECK-SD-NEXT: mov w10, #11 // =0xb
; CHECK-SD-NEXT: cmp w9, #273
-; CHECK-SD-NEXT: mov w9, #11 // =0xb
-; CHECK-SD-NEXT: csel w0, w9, w8, eq
+; CHECK-SD-NEXT: csel w0, w10, w8, eq
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: accept_csel:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub w8, w0, #273, lsl #12 // =1118208
-; CHECK-GI-NEXT: mov w9, #17 // =0x11
-; CHECK-GI-NEXT: mov w10, #11 // =0xb
-; CHECK-GI-NEXT: cmp w8, #273
-; CHECK-GI-NEXT: csel w0, w10, w9, eq
+; CHECK-GI-NEXT: mov w8, #17 // =0x11
+; CHECK-GI-NEXT: mov w9, #11 // =0xb
+; CHECK-GI-NEXT: sub w10, w0, #273, lsl #12 // =1118208
+; CHECK-GI-NEXT: cmp w10, #273
+; CHECK-GI-NEXT: csel w0, w9, w8, eq
; CHECK-GI-NEXT: ret
%2 = icmp eq i32 %0, 1118481
%3 = select i1 %2, i32 11, i32 17
@@ -532,25 +532,15 @@ define i32 @accept_csel(i32 %0) {
}
define i32 @reject_non_eqne_csel(i32 %0) {
-; CHECK-SD-LABEL: reject_non_eqne_csel:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mov w8, #4369 // =0x1111
-; CHECK-SD-NEXT: mov w9, #11 // =0xb
-; CHECK-SD-NEXT: movk w8, #17, lsl #16
-; CHECK-SD-NEXT: cmp w0, w8
-; CHECK-SD-NEXT: mov w8, #17 // =0x11
-; CHECK-SD-NEXT: csel w0, w9, w8, lo
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: reject_non_eqne_csel:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #4369 // =0x1111
-; CHECK-GI-NEXT: mov w9, #17 // =0x11
-; CHECK-GI-NEXT: mov w10, #11 // =0xb
-; CHECK-GI-NEXT: movk w8, #17, lsl #16
-; CHECK-GI-NEXT: cmp w0, w8
-; CHECK-GI-NEXT: csel w0, w10, w9, lo
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: reject_non_eqne_csel:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4369 // =0x1111
+; CHECK-NEXT: mov w9, #17 // =0x11
+; CHECK-NEXT: mov w10, #11 // =0xb
+; CHECK-NEXT: movk w8, #17, lsl #16
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csel w0, w10, w9, lo
+; CHECK-NEXT: ret
%2 = icmp ult i32 %0, 1118481
%3 = select i1 %2, i32 11, i32 17
ret i32 %3
@@ -598,45 +588,25 @@ define void @reject_non_eqne_branch(i32 %0) {
}
define i32 @reject_multiple_usages(i32 %0) {
-; CHECK-SD-LABEL: reject_multiple_usages:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mov w8, #4369 // =0x1111
-; CHECK-SD-NEXT: mov w9, #3 // =0x3
-; CHECK-SD-NEXT: mov w10, #17 // =0x11
-; CHECK-SD-NEXT: movk w8, #17, lsl #16
-; CHECK-SD-NEXT: mov w11, #12 // =0xc
-; CHECK-SD-NEXT: cmp w0, w8
-; CHECK-SD-NEXT: mov w8, #9 // =0x9
-; CHECK-SD-NEXT: csel w8, w8, w9, eq
-; CHECK-SD-NEXT: csel w9, w11, w10, hi
-; CHECK-SD-NEXT: mov w10, #53312 // =0xd040
-; CHECK-SD-NEXT: movk w10, #2, lsl #16
-; CHECK-SD-NEXT: add w8, w8, w9
-; CHECK-SD-NEXT: mov w9, #26304 // =0x66c0
-; CHECK-SD-NEXT: cmp w0, w10
-; CHECK-SD-NEXT: movk w9, #1433, lsl #16
-; CHECK-SD-NEXT: csel w0, w8, w9, hi
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: reject_multiple_usages:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #4369 // =0x1111
-; CHECK-GI-NEXT: mov w9, #3 // =0x3
-; CHECK-GI-NEXT: mov w10, #9 // =0x9
-; CHECK-GI-NEXT: movk w8, #17, lsl #16
-; CHECK-GI-NEXT: mov w11, #12 // =0xc
-; CHECK-GI-NEXT: cmp w0, w8
-; CHECK-GI-NEXT: mov w8, #17 // =0x11
-; CHECK-GI-NEXT: csel w9, w10, w9, eq
-; CHECK-GI-NEXT: csel w8, w11, w8, hi
-; CHECK-GI-NEXT: mov w10, #53312 // =0xd040
-; CHECK-GI-NEXT: movk w10, #2, lsl #16
-; CHECK-GI-NEXT: add w8, w9, w8
-; CHECK-GI-NEXT: mov w9, #26304 // =0x66c0
-; CHECK-GI-NEXT: movk w9, #1433, lsl #16
-; CHECK-GI-NEXT: cmp w0, w10
-; CHECK-GI-NEXT: csel w0, w8, w9, hi
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: reject_multiple_usages:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4369 // =0x1111
+; CHECK-NEXT: mov w9, #3 // =0x3
+; CHECK-NEXT: mov w10, #9 // =0x9
+; CHECK-NEXT: movk w8, #17, lsl #16
+; CHECK-NEXT: mov w11, #17 // =0x11
+; CHECK-NEXT: mov w12, #12 // =0xc
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csel w8, w10, w9, eq
+; CHECK-NEXT: mov w10, #26304 // =0x66c0
+; CHECK-NEXT: csel w9, w12, w11, hi
+; CHECK-NEXT: movk w10, #1433, lsl #16
+; CHECK-NEXT: add w8, w8, w9
+; CHECK-NEXT: mov w9, #53312 // =0xd040
+; CHECK-NEXT: movk w9, #2, lsl #16
+; CHECK-NEXT: cmp w0, w9
+; CHECK-NEXT: csel w0, w8, w10, hi
+; CHECK-NEXT: ret
%2 = icmp eq i32 %0, 1118481
%3 = icmp ugt i32 %0, 1118481
%4 = select i1 %2, i32 9, i32 3
diff --git a/llvm/test/CodeGen/AArch64/andandshift.ll b/llvm/test/CodeGen/AArch64/andandshift.ll
index 00990ef4f5db9..b694b9f66222d 100644
--- a/llvm/test/CodeGen/AArch64/andandshift.ll
+++ b/llvm/test/CodeGen/AArch64/andandshift.ll
@@ -20,10 +20,10 @@ entry:
define i32 @test2(i8 %a) {
; CHECK-LABEL: test2:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: and w8, w0, #0xff
-; CHECK-NEXT: ubfx w9, w0, #3, #5
-; CHECK-NEXT: cmp w8, #47
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: ubfx w8, w0, #3, #5
+; CHECK-NEXT: and w9, w0, #0xff
+; CHECK-NEXT: cmp w9, #47
+; CHECK-NEXT: csel w0, w8, w9, hi
; CHECK-NEXT: ret
entry:
%conv = zext i8 %a to i32
diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index ecdcbfe226e40..d3687361ecb0e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -585,8 +585,8 @@ define i32 @selor32(i32 %num, i32 %x) {
; CHECK-GI-LABEL: selor32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w0, #0xff00
-; CHECK-GI-NEXT: cmp w1, #0
; CHECK-GI-NEXT: orr w9, w8, #0x1
+; CHECK-GI-NEXT: cmp w1, #0
; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
entry:
@@ -601,8 +601,8 @@ define i32 @selor32_2(i32 %num, i32 %x) {
; CHECK-LABEL: selor32_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff00
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: orr w9, w8, #0x2
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, w9, w8, ne
; CHECK-NEXT: ret
entry:
@@ -624,8 +624,8 @@ define i64 @selor64(i64 %num, i64 %x) {
; CHECK-GI-LABEL: selor64:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and x8, x0, #0xff00
-; CHECK-GI-NEXT: cmp x1, #0
; CHECK-GI-NEXT: orr x9, x8, #0x1
+; CHECK-GI-NEXT: cmp x1, #0
; CHECK-GI-NEXT: csel x0, x9, x8, ne
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 5208ea0cdc424..bf122436ab983 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -249,31 +249,18 @@ define i1 @test_setcc3(fp128 %lhs, fp128 %rhs) {
; olt == !uge, which LLVM optimizes this to.
define i32 @test_br_cc(fp128 %lhs, fp128 %rhs) {
-; CHECK-SD-LABEL: test_br_cc:
-; CHECK-SD: // %bb.0: // %common.ret
-; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SD-NEXT: .cfi_offset w30, -16
-; CHECK-SD-NEXT: bl __lttf2
-; CHECK-SD-NEXT: mov w8, #29 // =0x1d
-; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: mov w9, #42 // =0x2a
-; CHECK-SD-NEXT: csel w0, w9, w8, mi
-; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_br_cc:
-; CHECK-GI: // %bb.0: // %common.ret
-; CHECK-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
-; CHECK-GI-NEXT: .cfi_offset w30, -16
-; CHECK-GI-NEXT: bl __lttf2
-; CHECK-GI-NEXT: mov w8, #29 // =0x1d
-; CHECK-GI-NEXT: mov w9, #42 // =0x2a
-; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: csel w0, w9, w8, mi
-; CHECK-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_br_cc:
+; CHECK: // %bb.0: // %common.ret
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl __lttf2
+; CHECK-NEXT: mov w8, #29 // =0x1d
+; CHECK-NEXT: mov w9, #42 // =0x2a
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: csel w0, w9, w8, mi
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%cond = fcmp olt fp128 %lhs, %rhs
br i1 %cond, label %iftrue, label %iffalse
diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
index bcc29bdce1fc3..498507eb084c0 100644
--- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
@@ -14070,8 +14070,8 @@ define i32 @load_single_extract_variable_index_i32(ptr %A, i32 %idx) {
define i32 @load_single_extract_variable_index_v3i32_small_align(ptr %A, i32 %idx) {
; CHECK-LABEL: load_single_extract_variable_index_v3i32_small_align:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: mov w8, #2 ; =0x2
+; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
@@ -14084,8 +14084,8 @@ define i32 @load_single_extract_variable_index_v3i32_small_align(ptr %A, i32 %id
define i32 @load_single_extract_variable_index_v3i32_default_align(ptr %A, i32 %idx) {
; CHECK-LABEL: load_single_extract_variable_index_v3i32_default_align:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: mov w8, #2 ; =0x2
+; CHECK-NEXT: mov w9, w1
; CHECK-NEXT: cmp x9, #2
; CHECK-NEXT: csel x8, x9, x8, lo
; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
diff --git a/llvm/test/CodeGen/AArch64/arm64-xaluo.ll b/llvm/test/CodeGen/AArch64/arm64-xaluo.ll
index bf24d1d62525c..5e03056b4614f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-xaluo.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-xaluo.ll
@@ -1347,11 +1347,11 @@ define i8 @uaddo.selectboth.i8(i8 %a, i8 %b) {
;
; CHECK-GI-LABEL: uaddo.selectboth.i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and w9, w1, #0xff
-; CHECK-GI-NEXT: mov w8, #10 // =0xa
-; CHECK-GI-NEXT: add w9, w9, w0, uxtb
-; CHECK-GI-NEXT: cmp w9, w9, uxtb
-; CHECK-GI-NEXT: csel w0, w9, w8, ne
+; CHECK-GI-NEXT: and w8, w1, #0xff
+; CHECK-GI-NEXT: mov w9, #10 // =0xa
+; CHECK-GI-NEXT: add w8, w8, w0, uxtb
+; CHECK-GI-NEXT: cmp w8, w8, uxtb
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
;
; CHECK-FI-LABEL: uaddo.selectboth.i8:
@@ -1611,11 +1611,11 @@ define i8 @usubo.selectboth.i8(i8 %a, i8 %b) {
;
; CHECK-GI-LABEL: usubo.selectboth.i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and w9, w0, #0xff
-; CHECK-GI-NEXT: mov w8, #10 // =0xa
-; CHECK-GI-NEXT: sub w9, w9, w1, uxtb
-; CHECK-GI-NEXT: cmp w9, w9, uxtb
-; CHECK-GI-NEXT: csel w0, w9, w8, ne
+; CHECK-GI-NEXT: and w8, w0, #0xff
+; CHECK-GI-NEXT: mov w9, #10 // =0xa
+; CHECK-GI-NEXT: sub w8, w8, w1, uxtb
+; CHECK-GI-NEXT: cmp w8, w8, uxtb
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
;
; CHECK-FI-LABEL: usubo.selectboth.i8:
@@ -1841,12 +1841,12 @@ define i8 @umulo.selectboth.i8(i8 %a, i8 %b) {
;
; CHECK-GI-LABEL: umulo.selectboth.i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and w9, w0, #0xff
-; CHECK-GI-NEXT: and w10, w1, #0xff
-; CHECK-GI-NEXT: mov w8, #10 // =0xa
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: cmp w9, w9, uxtb
-; CHECK-GI-NEXT: csel w0, w9, w8, ne
+; CHECK-GI-NEXT: and w8, w0, #0xff
+; CHECK-GI-NEXT: and w9, w1, #0xff
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #10 // =0xa
+; CHECK-GI-NEXT: cmp w8, w8, uxtb
+; CHECK-GI-NEXT: csel w0, w8, w9, ne
; CHECK-GI-NEXT: ret
;
; CHECK-FI-LABEL: umulo.selectboth.i8:
@@ -1991,12 +1991,12 @@ define i32 @umulo.selectboth.i32(i32 %a, i32 %b) {
;
; CHECK-GI-LABEL: umulo.selectboth.i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: umull x9, w0, w1
-; CHECK-GI-NEXT: mov w8, #10 // =0xa
-; CHECK-GI-NEXT: mul w10, w0, w1
-; CHECK-GI-NEXT: lsr x9, x9, #32
-; CHECK-GI-NEXT: cmp w9, #0
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: umull x8, w0, w1
+; CHECK-GI-NEXT: mov w10, #10 // =0xa
+; CHECK-GI-NEXT: mul w9, w0, w1
+; CHECK-GI-NEXT: lsr x8, x8, #32
+; CHECK-GI-NEXT: cmp w8, #0
+; CHECK-GI-NEXT: csel w0, w9, w10, ne
; CHECK-GI-NEXT: ret
;
; CHECK-FI-LABEL: umulo.selectboth.i32:
@@ -2051,29 +2051,29 @@ entry:
define i64 @umulo.selectboth.i64(i64 %a, i64 %b) {
; CHECK-SD-LABEL: umulo.selectboth.i64:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mul x8, x0, x1
+; CHECK-SD-NEXT: mov w10, #10 // =0xa
; CHECK-SD-NEXT: umulh x9, x0, x1
-; CHECK-SD-NEXT: mov w8, #10 // =0xa
-; CHECK-SD-NEXT: mul x10, x0, x1
; CHECK-SD-NEXT: cmp xzr, x9
-; CHECK-SD-NEXT: csel x0, x10, x8, ne
+; CHECK-SD-NEXT: csel x0, x8, x10, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: umulo.selectboth.i64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: umulh x9, x0, x1
-; CHECK-GI-NEXT: mov w8, #10 // =0xa
-; CHECK-GI-NEXT: mul x10, x0, x1
-; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: csel x0, x10, x8, ne
+; CHECK-GI-NEXT: umulh x8, x0, x1
+; CHECK-GI-NEXT: mov w10, #10 // =0xa
+; CHECK-GI-NEXT: mul x9, x0, x1
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: csel x0, x9, x10, ne
; CHECK-GI-NEXT: ret
;
; CHECK-FI-LABEL: umulo.selectboth.i64:
; CHECK-FI: // %bb.0: // %entry
+; CHECK-FI-NEXT: mul x8, x0, x1
+; CHECK-FI-NEXT: mov x10, #10 // =0xa
; CHECK-FI-NEXT: umulh x9, x0, x1
-; CHECK-FI-NEXT: mov x8, #10 // =0xa
-; CHECK-FI-NEXT: mul x10, x0, x1
; CHECK-FI-NEXT: cmp xzr, x9
-; CHECK-FI-NEXT: csel x0, x10, x8, ne
+; CHECK-FI-NEXT: csel x0, x8, x10, ne
; CHECK-FI-NEXT: ret
entry:
%m = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
index 9cd31ca7cc99f..ac0f2b7fcc62b 100644
--- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
@@ -1577,11 +1577,11 @@ define i8 @test_fptosi_sat_i8(bfloat %a) {
; CHECK-LABEL: test_fptosi_sat_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: mov w8, #127 // =0x7f
+; CHECK-NEXT: mov w9, #127 // =0x7f
; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: cmp w9, #127
-; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: cmp w8, #127
+; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: csel w0, w8, w9, gt
@@ -1633,11 +1633,11 @@ define i8 @test_fptoui_sat_i8(bfloat %a) {
; CHECK-LABEL: test_fptoui_sat_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
-; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: mov w9, #255 // =0xff
; CHECK-NEXT: shll v0.4s, v0.4h, #16
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: cmp w9, #255
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%i = call i8 @llvm.fptoui.sat.i8.bf16(bfloat %a)
ret i8 %i
@@ -1708,10 +1708,10 @@ define bfloat @test_uitofp_i64(i64 %a) #0 {
; CHECK-CVT-LABEL: test_uitofp_i64:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: lsr x9, x0, #53
+; CHECK-CVT-NEXT: and x10, x0, #0xfffffffffffff000
; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff
; CHECK-CVT-NEXT: cmp x9, #0
-; CHECK-CVT-NEXT: and x9, x0, #0xfffffffffffff000
-; CHECK-CVT-NEXT: csel x9, x9, x0, ne
+; CHECK-CVT-NEXT: csel x9, x10, x0, ne
; CHECK-CVT-NEXT: ucvtf d0, x9
; CHECK-CVT-NEXT: cset w9, ne
; CHECK-CVT-NEXT: tst x0, #0xfff
@@ -1778,13 +1778,13 @@ define bfloat @test_sitofp_i64(i64 %a) #0 {
; CHECK-CVT-LABEL: test_sitofp_i64:
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: cmp x0, #0
-; CHECK-CVT-NEXT: and x11, x0, #0x8000000000000000
; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff
; CHECK-CVT-NEXT: cneg x9, x0, mi
; CHECK-CVT-NEXT: lsr x10, x9, #53
+; CHECK-CVT-NEXT: and x11, x9, #0xfffffffffffff000
; CHECK-CVT-NEXT: cmp x10, #0
-; CHECK-CVT-NEXT: and x10, x9, #0xfffffffffffff000
-; CHECK-CVT-NEXT: csel x10, x10, x9, ne
+; CHECK-CVT-NEXT: csel x10, x11, x9, ne
+; CHECK-CVT-NEXT: and x11, x0, #0x8000000000000000
; CHECK-CVT-NEXT: scvtf d0, x10
; CHECK-CVT-NEXT: cset w10, ne
; CHECK-CVT-NEXT: tst x9, #0xfff
@@ -1812,8 +1812,8 @@ define bfloat @test_sitofp_i64(i64 %a) #0 {
; CHECK-BF16-NEXT: cmp x9, #0
; CHECK-BF16-NEXT: csel x9, x10, x8, ne
; CHECK-BF16-NEXT: and x10, x0, #0x8000000000000000
-; CHECK-BF16-NEXT: cset w11, ne
; CHECK-BF16-NEXT: scvtf d0, x9
+; CHECK-BF16-NEXT: cset w11, ne
; CHECK-BF16-NEXT: tst x8, #0xfff
; CHECK-BF16-NEXT: fmov x9, d0
; CHECK-BF16-NEXT: orr x8, x9, x10
diff --git a/llvm/test/CodeGen/AArch64/bitcnt-i256.ll b/llvm/test/CodeGen/AArch64/bitcnt-i256.ll
index 3376f44a0e68f..27714060397f5 100644
--- a/llvm/test/CodeGen/AArch64/bitcnt-i256.ll
+++ b/llvm/test/CodeGen/AArch64/bitcnt-i256.ll
@@ -118,65 +118,65 @@ define i256 @ctlz_i256(i256 %a) nounwind {
;
; NEON-LABEL: ctlz_i256:
; NEON: // %bb.0:
-; NEON-NEXT: clz x8, x2
-; NEON-NEXT: clz x9, x3
+; NEON-NEXT: clz x9, x2
+; NEON-NEXT: clz x11, x0
+; NEON-NEXT: clz x8, x3
+; NEON-NEXT: clz x10, x1
+; NEON-NEXT: add x9, x9, #64
+; NEON-NEXT: add x11, x11, #64
; NEON-NEXT: cmp x3, #0
-; NEON-NEXT: add x8, x8, #64
-; NEON-NEXT: clz x10, x0
-; NEON-NEXT: orr x11, x2, x3
-; NEON-NEXT: csel x8, x9, x8, ne
-; NEON-NEXT: clz x9, x1
-; NEON-NEXT: add x10, x10, #64
+; NEON-NEXT: csel x8, x8, x9, ne
; NEON-NEXT: cmp x1, #0
+; NEON-NEXT: csel x9, x10, x11, ne
+; NEON-NEXT: orr x10, x2, x3
+; NEON-NEXT: add x9, x9, #128
+; NEON-NEXT: cmp x10, #0
; NEON-NEXT: mov x1, xzr
+; NEON-NEXT: csel x0, x8, x9, ne
; NEON-NEXT: mov x2, xzr
-; NEON-NEXT: csel x9, x9, x10, ne
-; NEON-NEXT: cmp x11, #0
; NEON-NEXT: mov x3, xzr
-; NEON-NEXT: add x9, x9, #128
-; NEON-NEXT: csel x0, x8, x9, ne
; NEON-NEXT: ret
;
; SVE-LABEL: ctlz_i256:
; SVE: // %bb.0:
-; SVE-NEXT: clz x8, x2
-; SVE-NEXT: clz x9, x3
+; SVE-NEXT: clz x9, x2
+; SVE-NEXT: clz x11, x0
+; SVE-NEXT: clz x8, x3
+; SVE-NEXT: clz x10, x1
+; SVE-NEXT: add x9, x9, #64
+; SVE-NEXT: add x11, x11, #64
; SVE-NEXT: cmp x3, #0
-; SVE-NEXT: add x8, x8, #64
-; SVE-NEXT: clz x10, x0
-; SVE-NEXT: orr x11, x2, x3
-; SVE-NEXT: csel x8, x9, x8, ne
-; SVE-NEXT: clz x9, x1
-; SVE-NEXT: add x10, x10, #64
+; SVE-NEXT: csel x8, x8, x9, ne
; SVE-NEXT: cmp x1, #0
+; SVE-NEXT: csel x9, x10, x11, ne
+; SVE-NEXT: orr x10, x2, x3
+; SVE-NEXT: add x9, x9, #128
+; SVE-NEXT: cmp x10, #0
; SVE-NEXT: mov x1, xzr
+; SVE-NEXT: csel x0, x8, x9, ne
; SVE-NEXT: mov x2, xzr
-; SVE-NEXT: csel x9, x9, x10, ne
-; SVE-NEXT: cmp x11, #0
; SVE-NEXT: mov x3, xzr
-; SVE-NEXT: add x9, x9, #128
-; SVE-NEXT: csel x0, x8, x9, ne
; SVE-NEXT: ret
;
; CSSC-LABEL: ctlz_i256:
; CSSC: // %bb.0:
-; CSSC-NEXT: clz x8, x2
-; CSSC-NEXT: clz x9, x3
+; CSSC-NEXT: clz x9, x2
+; CSSC-NEXT: clz x11, x0
+; CSSC-NEXT: clz x8, x3
+; CSSC-NEXT: clz x10, x1
+; CSSC-NEXT: add x9, x9, #64
+; CSSC-NEXT: add x11, x11, #64
; CSSC-NEXT: cmp x3, #0
-; CSSC-NEXT: add x8, x8, #64
-; CSSC-NEXT: clz x10, x0
-; CSSC-NEXT: orr x11, x2, x3
-; CSSC-NEXT: csel x8, x9, x8, ne
-; CSSC-NEXT: clz x9, x1
-; CSSC-NEXT: add x10, x10, #64
+; CSSC-NEXT: csel x8, x8, x9, ne
; CSSC-NEXT: cmp x1, #0
+; CSSC-NEXT: csel x9, x10, x11, ne
+; CSSC-NEXT: orr x10, x2, x3
+; CSSC-NEXT: add x9, x9, #128
+; CSSC-NEXT: cmp x10, #0
; CSSC-NEXT: mov x1, xzr
+; CSSC-NEXT: csel x0, x8, x9, ne
; CSSC-NEXT: mov x2, xzr
-; CSSC-NEXT: csel x9, x9, x10, ne
-; CSSC-NEXT: cmp x11, #0
; CSSC-NEXT: mov x3, xzr
-; CSSC-NEXT: add x9, x9, #128
-; CSSC-NEXT: csel x0, x8, x9, ne
; CSSC-NEXT: ret
%r = call i256 @llvm.ctlz.i256(i256 %a, i1 false)
ret i256 %r
@@ -188,73 +188,73 @@ define i256 @cttz_i256(i256 %a) nounwind {
;
; NEON-LABEL: cttz_i256:
; NEON: // %bb.0:
-; NEON-NEXT: rbit x8, x1
-; NEON-NEXT: rbit x9, x0
-; NEON-NEXT: rbit x10, x3
-; NEON-NEXT: cmp x0, #0
-; NEON-NEXT: rbit x11, x2
+; NEON-NEXT: rbit x9, x1
+; NEON-NEXT: rbit x11, x3
+; NEON-NEXT: rbit x8, x0
+; NEON-NEXT: rbit x10, x2
; NEON-NEXT: mov x3, xzr
-; NEON-NEXT: clz x8, x8
; NEON-NEXT: clz x9, x9
-; NEON-NEXT: add x8, x8, #64
-; NEON-NEXT: csel x8, x9, x8, ne
-; NEON-NEXT: clz x9, x10
-; NEON-NEXT: clz x10, x11
+; NEON-NEXT: clz x11, x11
+; NEON-NEXT: clz x8, x8
+; NEON-NEXT: clz x10, x10
; NEON-NEXT: add x9, x9, #64
+; NEON-NEXT: add x11, x11, #64
+; NEON-NEXT: cmp x0, #0
+; NEON-NEXT: csel x8, x8, x9, ne
; NEON-NEXT: cmp x2, #0
-; NEON-NEXT: orr x11, x0, x1
-; NEON-NEXT: csel x9, x10, x9, ne
-; NEON-NEXT: cmp x11, #0
-; NEON-NEXT: mov x1, xzr
+; NEON-NEXT: csel x9, x10, x11, ne
+; NEON-NEXT: orr x10, x0, x1
; NEON-NEXT: add x9, x9, #128
-; NEON-NEXT: mov x2, xzr
+; NEON-NEXT: cmp x10, #0
+; NEON-NEXT: mov x1, xzr
; NEON-NEXT: csel x0, x8, x9, ne
+; NEON-NEXT: mov x2, xzr
; NEON-NEXT: ret
;
; SVE-LABEL: cttz_i256:
; SVE: // %bb.0:
-; SVE-NEXT: rbit x8, x1
-; SVE-NEXT: rbit x9, x0
-; SVE-NEXT: rbit x10, x3
-; SVE-NEXT: cmp x0, #0
-; SVE-NEXT: rbit x11, x2
+; SVE-NEXT: rbit x9, x1
+; SVE-NEXT: rbit x11, x3
+; SVE-NEXT: rbit x8, x0
+; SVE-NEXT: rbit x10, x2
; SVE-NEXT: mov x3, xzr
-; SVE-NEXT: clz x8, x8
; SVE-NEXT: clz x9, x9
-; SVE-NEXT: add x8, x8, #64
-; SVE-NEXT: csel x8, x9, x8, ne
-; SVE-NEXT: clz x9, x10
-; SVE-NEXT: clz x10, x11
+; SVE-NEXT: clz x11, x11
+; SVE-NEXT: clz x8, x8
+; SVE-NEXT: clz x10, x10
; SVE-NEXT: add x9, x9, #64
+; SVE-NEXT: add x11, x11, #64
+; SVE-NEXT: cmp x0, #0
+; SVE-NEXT: csel x8, x8, x9, ne
; SVE-NEXT: cmp x2, #0
-; SVE-NEXT: orr x11, x0, x1
-; SVE-NEXT: csel x9, x10, x9, ne
-; SVE-NEXT: cmp x11, #0
-; SVE-NEXT: mov x1, xzr
+; SVE-NEXT: csel x9, x10, x11, ne
+; SVE-NEXT: orr x10, x0, x1
; SVE-NEXT: add x9, x9, #128
-; SVE-NEXT: mov x2, xzr
+; SVE-NEXT: cmp x10, #0
+; SVE-NEXT: mov x1, xzr
; SVE-NEXT: csel x0, x8, x9, ne
+; SVE-NEXT: mov x2, xzr
; SVE-NEXT: ret
;
; CSSC-LABEL: cttz_i256:
; CSSC: // %bb.0:
; CSSC-NEXT: ctz x8, x1
+; CSSC-NEXT: ctz x11, x3
; CSSC-NEXT: ctz x9, x0
-; CSSC-NEXT: cmp x0, #0
+; CSSC-NEXT: ctz x10, x2
; CSSC-NEXT: add x8, x8, #64
-; CSSC-NEXT: ctz x10, x3
-; CSSC-NEXT: orr x11, x0, x1
+; CSSC-NEXT: add x11, x11, #64
+; CSSC-NEXT: cmp x0, #0
; CSSC-NEXT: csel x8, x9, x8, ne
-; CSSC-NEXT: ctz x9, x2
-; CSSC-NEXT: add x10, x10, #64
-; CSSC-NEXT: cmp x2, #0
-; CSSC-NEXT: mov x1, xzr
-; CSSC-NEXT: mov x2, xzr
-; CSSC-NEXT: csel x9, x9, x10, ne
-; CSSC-NEXT: cmp x11, #0
; CSSC-NEXT: mov x3, xzr
+; CSSC-NEXT: cmp x2, #0
+; CSSC-NEXT: csel x9, x10, x11, ne
+; CSSC-NEXT: orr x10, x0, x1
; CSSC-NEXT: add x9, x9, #128
+; CSSC-NEXT: cmp x10, #0
+; CSSC-NEXT: mov x1, xzr
; CSSC-NEXT: csel x0, x8, x9, ne
+; CSSC-NEXT: mov x2, xzr
; CSSC-NEXT: ret
%r = call i256 @llvm.cttz.i256(i256 %a, i1 false)
ret i256 %r
diff --git a/llvm/test/CodeGen/AArch64/bool-vector-bitcast-compare.ll b/llvm/test/CodeGen/AArch64/bool-vector-bitcast-compare.ll
index ea279be26114e..fd38a8a98245a 100644
--- a/llvm/test/CodeGen/AArch64/bool-vector-bitcast-compare.ll
+++ b/llvm/test/CodeGen/AArch64/bool-vector-bitcast-compare.ll
@@ -6,11 +6,11 @@ define i64 @match_any_byte(<8 x i8> %haystack, i8 %needle) {
; CHECK: // %bb.0: // %bb1
; CHECK-NEXT: dup v1.8b, w0
; CHECK-NEXT: mov w8, #999 // =0x3e7
+; CHECK-NEXT: mov w10, #777 // =0x309
; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: mov w9, #777 // =0x309
-; CHECK-NEXT: csel x0, x9, x8, ne
+; CHECK-NEXT: csel x0, x10, x8, ne
; CHECK-NEXT: ret
bb1:
%0 = insertelement <8 x i8> poison, i8 %needle, i64 0
@@ -66,12 +66,12 @@ define i64 @match_any_byte_16(<16 x i8> %haystack, i8 %needle) {
; CHECK: // %bb.0: // %bb1
; CHECK-NEXT: dup v1.16b, w0
; CHECK-NEXT: mov w8, #999 // =0x3e7
+; CHECK-NEXT: mov w10, #777 // =0x309
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: mov w9, #777 // =0x309
-; CHECK-NEXT: csel x0, x9, x8, ne
+; CHECK-NEXT: csel x0, x10, x8, ne
; CHECK-NEXT: ret
bb1:
%0 = insertelement <16 x i8> poison, i8 %needle, i64 0
@@ -176,12 +176,12 @@ define i64 @match_any_byte_4(<4 x i8> %haystack, i8 %needle) {
; CHECK-NEXT: dup v1.4h, w0
; CHECK-NEXT: bic v0.4h, #255, lsl #8
; CHECK-NEXT: mov w8, #999 // =0x3e7
+; CHECK-NEXT: mov w10, #777 // =0x309
; CHECK-NEXT: bic v1.4h, #255, lsl #8
; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: mov w9, #777 // =0x309
-; CHECK-NEXT: csel x0, x9, x8, ne
+; CHECK-NEXT: csel x0, x10, x8, ne
; CHECK-NEXT: ret
bb1:
%0 = insertelement <4 x i8> poison, i8 %needle, i64 0
diff --git a/llvm/test/CodeGen/AArch64/branch-relax-alignment.ll b/llvm/test/CodeGen/AArch64/branch-relax-alignment.ll
index bafe432bbfbdb..43cf5b22070ba 100644
--- a/llvm/test/CodeGen/AArch64/branch-relax-alignment.ll
+++ b/llvm/test/CodeGen/AArch64/branch-relax-alignment.ll
@@ -8,10 +8,10 @@ define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 {
; CHECK-LABEL: invert_bcc_block_align_higher_func:
; CHECK: ; %bb.0: ; %common.ret
; CHECK-NEXT: mov w8, #9 ; =0x9
-; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: mov w9, #42 ; =0x2a
-; CHECK-NEXT: cset w0, ne
+; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: csel w8, w9, w8, eq
+; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: ret
%1 = icmp eq i32 %x, %y
diff --git a/llvm/test/CodeGen/AArch64/csel-cmp-cse.ll b/llvm/test/CodeGen/AArch64/csel-cmp-cse.ll
index 07b32ef0830c2..5aa276835764a 100644
--- a/llvm/test/CodeGen/AArch64/csel-cmp-cse.ll
+++ b/llvm/test/CodeGen/AArch64/csel-cmp-cse.ll
@@ -638,10 +638,10 @@ define i32 @test_eq0_multi_use_cmp_i32(i32 %x0, i32 %x1) {
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: sub w8, w8, #1
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w19, wzr, w8, eq
+; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: bl use_i1
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
@@ -670,8 +670,8 @@ define i32 @test_eq0_multi_use_add_i32(i32 %x0, i32 %x1) {
; CHECK-NEXT: bl use_i32
; CHECK-NEXT: sub w8, w20, #1
; CHECK-NEXT: cmp w19, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: csel w0, wzr, w8, eq
+; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret
%cmp = icmp eq i32 %x1, 0
@@ -687,8 +687,8 @@ define i32 @test_eq1_sub_add_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_eq1_sub_add_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #1
; CHECK-NEXT: sub w8, w8, #2
+; CHECK-NEXT: cmp w1, #1
; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i32 %x1, 1
@@ -704,8 +704,8 @@ define i32 @test_ugtsmax_sub_add_i32(i32 %x0, i32 %x1) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
; CHECK-NEXT: add w9, w0, w1
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: add w8, w9, w8
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, wzr, w8, mi
; CHECK-NEXT: ret
%cmp = icmp ugt i32 %x1, 2147483647
@@ -720,8 +720,8 @@ define i32 @test_eq_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_eq_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: sub w8, w8, #2
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i32 %x1, 0
@@ -736,8 +736,8 @@ define i32 @test_ne_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_ne_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: sub w8, w8, #2
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, w8, wzr, ne
; CHECK-NEXT: ret
%cmp = icmp ne i32 %x1, 0
@@ -752,8 +752,8 @@ define i32 @test_ult7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_ult7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: sub w8, w8, #8
+; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csel w0, wzr, w8, lo
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x1, 7
@@ -768,8 +768,8 @@ define i32 @test_ule7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_ule7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #8
; CHECK-NEXT: sub w8, w8, #6
+; CHECK-NEXT: cmp w1, #8
; CHECK-NEXT: csel w0, wzr, w8, lo
; CHECK-NEXT: ret
%cmp = icmp ule i32 %x1, 7
@@ -784,8 +784,8 @@ define i32 @test_ugt7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_ugt7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: sub w8, w8, #6
+; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csel w0, wzr, w8, hi
; CHECK-NEXT: ret
%cmp = icmp ugt i32 %x1, 7
@@ -800,8 +800,8 @@ define i32 @test_uge7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_uge7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #6
; CHECK-NEXT: sub w8, w8, #8
+; CHECK-NEXT: cmp w1, #6
; CHECK-NEXT: csel w0, wzr, w8, hi
; CHECK-NEXT: ret
%cmp = icmp uge i32 %x1, 7
@@ -816,8 +816,8 @@ define i32 @test_slt7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_slt7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: sub w8, w8, #8
+; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csel w0, wzr, w8, lt
; CHECK-NEXT: ret
%cmp = icmp slt i32 %x1, 7
@@ -832,8 +832,8 @@ define i32 @test_sle7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_sle7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #8
; CHECK-NEXT: sub w8, w8, #6
+; CHECK-NEXT: cmp w1, #8
; CHECK-NEXT: csel w0, wzr, w8, lt
; CHECK-NEXT: ret
%cmp = icmp sle i32 %x1, 7
@@ -848,8 +848,8 @@ define i32 @test_sgt7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_sgt7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: sub w8, w8, #6
+; CHECK-NEXT: cmp w1, #7
; CHECK-NEXT: csel w0, wzr, w8, gt
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %x1, 7
@@ -864,8 +864,8 @@ define i32 @test_sge7_const_mismatch_i32(i32 %x0, i32 %x1) {
; CHECK-LABEL: test_sge7_const_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, #6
; CHECK-NEXT: sub w8, w8, #8
+; CHECK-NEXT: cmp w1, #6
; CHECK-NEXT: csel w0, wzr, w8, gt
; CHECK-NEXT: ret
%cmp = icmp sge i32 %x1, 7
@@ -880,8 +880,8 @@ define i32 @test_unrelated_add_i32(i32 %x0, i32 %x1, i32 %x2) {
; CHECK-LABEL: test_unrelated_add_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w2
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: sub w8, w8, #1
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i32 %x1, 0
@@ -911,11 +911,11 @@ define i16 @test_eq0_sub_add_i16(i16 %x0, i16 %x1) {
define i8 @test_eq_nonconst_sub_add_i8(i8 %x0, i8 %x1, i8 %x2) {
; CHECK-LABEL: test_eq_nonconst_sub_add_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: and w8, w1, #0xff
-; CHECK-NEXT: add w9, w0, w1
-; CHECK-NEXT: sub w9, w9, w2
-; CHECK-NEXT: cmp w8, w2, uxtb
-; CHECK-NEXT: csel w0, wzr, w9, eq
+; CHECK-NEXT: add w8, w0, w1
+; CHECK-NEXT: and w9, w1, #0xff
+; CHECK-NEXT: sub w8, w8, w2
+; CHECK-NEXT: cmp w9, w2, uxtb
+; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i8 %x1, %x2
%add = add nuw i8 %x0, %x1
@@ -1089,8 +1089,8 @@ define i32 @test_ult_nonconst_op_mismatch_i32(i32 %x0, i32 %x1, i32 %x2) {
; CHECK-LABEL: test_ult_nonconst_op_mismatch_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, w2
; CHECK-NEXT: add w8, w8, w2
+; CHECK-NEXT: cmp w1, w2
; CHECK-NEXT: csel w0, wzr, w8, lo
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x1, %x2
@@ -1105,8 +1105,8 @@ define i32 @test_ult_nonconst_unrelated_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3)
; CHECK-LABEL: test_ult_nonconst_unrelated_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w1, w2
; CHECK-NEXT: sub w8, w8, w3
+; CHECK-NEXT: cmp w1, w2
; CHECK-NEXT: csel w0, wzr, w8, lo
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x1, %x2
@@ -1121,8 +1121,8 @@ define i32 @test_ult_nonconst_unrelated_2_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3
; CHECK-LABEL: test_ult_nonconst_unrelated_2_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: cmp w2, w1
; CHECK-NEXT: sub w8, w8, w3
+; CHECK-NEXT: cmp w2, w1
; CHECK-NEXT: csel w0, wzr, w8, lo
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x2, %x1
diff --git a/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
index 7d2c7854baf3d..5078a2c52bc4e 100644
--- a/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
+++ b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
@@ -95,8 +95,8 @@ define i32 @ugt_i32(i32 %x) {
define i32 @uge_i32(i32 %x) {
; CHECK-LABEL: uge_i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: lsr w9, w0, #21
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
+; CHECK-NEXT: lsr w9, w0, #21
; CHECK-NEXT: sub w8, w8, w0
; CHECK-NEXT: cmp w9, #2046
; CHECK-NEXT: csel w0, w0, w8, hi
@@ -177,8 +177,8 @@ define i64 @sge_i64(i64 %x) {
; CHECK-LABEL: sge_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: cmp x0, #99
; CHECK-NEXT: sub x8, x8, x0
+; CHECK-NEXT: cmp x0, #99
; CHECK-NEXT: csel x0, x0, x8, gt
; CHECK-NEXT: ret
%cmp = icmp sge i64 %x, 100
@@ -204,8 +204,8 @@ define i64 @sle_i64(i64 %x) {
; CHECK-LABEL: sle_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: sub x8, x8, x0
+; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: csel x0, x0, x8, lt
; CHECK-NEXT: ret
%cmp = icmp sle i64 %x, 100
@@ -231,8 +231,8 @@ define i64 @uge_i64(i64 %x) {
; CHECK-LABEL: uge_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: cmp x0, #99
; CHECK-NEXT: sub x8, x8, x0
+; CHECK-NEXT: cmp x0, #99
; CHECK-NEXT: csel x0, x0, x8, hi
; CHECK-NEXT: ret
%cmp = icmp uge i64 %x, 100
@@ -258,8 +258,8 @@ define i64 @ule_i64(i64 %x) {
; CHECK-LABEL: ule_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #100 // =0x64
-; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: sub x8, x8, x0
+; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: csel x0, x0, x8, lo
; CHECK-NEXT: ret
%cmp = icmp ule i64 %x, 100
@@ -274,8 +274,8 @@ define i64 @both(i64 %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #100 // =0x64
; CHECK-NEXT: sub x9, x0, #100
-; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: sub x8, x8, x0
+; CHECK-NEXT: cmp x0, #101
; CHECK-NEXT: csel x0, x8, x9, lo
; CHECK-NEXT: ret
%cmp = icmp ule i64 %x, 100
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index 968fd6d7c9813..aa348c97fb91e 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -414,18 +414,18 @@ entry:
define <2 x i128> @v2i128(<2 x i128> %d) {
; CHECK-SD-LABEL: v2i128:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: clz x8, x0
-; CHECK-SD-NEXT: clz x9, x1
+; CHECK-SD-NEXT: clz x9, x0
+; CHECK-SD-NEXT: clz x11, x2
+; CHECK-SD-NEXT: clz x8, x1
+; CHECK-SD-NEXT: clz x10, x3
+; CHECK-SD-NEXT: add x9, x9, #64
+; CHECK-SD-NEXT: add x11, x11, #64
; CHECK-SD-NEXT: cmp x1, #0
-; CHECK-SD-NEXT: add x8, x8, #64
-; CHECK-SD-NEXT: clz x10, x2
+; CHECK-SD-NEXT: csel x0, x8, x9, ne
; CHECK-SD-NEXT: mov x1, xzr
-; CHECK-SD-NEXT: csel x0, x9, x8, ne
-; CHECK-SD-NEXT: clz x8, x3
-; CHECK-SD-NEXT: add x9, x10, #64
; CHECK-SD-NEXT: cmp x3, #0
+; CHECK-SD-NEXT: csel x2, x10, x11, ne
; CHECK-SD-NEXT: mov x3, xzr
-; CHECK-SD-NEXT: csel x2, x8, x9, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i128:
@@ -442,8 +442,8 @@ define <2 x i128> @v2i128(<2 x i128> %d) {
; CHECK-GI-NEXT: csel x1, x10, xzr, eq
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x10, x3
; CHECK-GI-NEXT: adc x8, xzr, xzr
+; CHECK-GI-NEXT: clz x10, x3
; CHECK-GI-NEXT: cmp x3, #0
; CHECK-GI-NEXT: csel x2, x9, x10, eq
; CHECK-GI-NEXT: csel x3, x8, xzr, eq
@@ -458,48 +458,48 @@ define <3 x i128> @v3i128(<3 x i128> %d) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: clz x8, x0
; CHECK-SD-NEXT: clz x9, x1
-; CHECK-SD-NEXT: cmp x1, #0
-; CHECK-SD-NEXT: add x8, x8, #64
; CHECK-SD-NEXT: clz x10, x2
-; CHECK-SD-NEXT: mov x1, xzr
+; CHECK-SD-NEXT: add x8, x8, #64
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: clz x11, x5
; CHECK-SD-NEXT: csel x0, x9, x8, ne
-; CHECK-SD-NEXT: clz x8, x3
; CHECK-SD-NEXT: add x9, x10, #64
+; CHECK-SD-NEXT: clz x10, x4
+; CHECK-SD-NEXT: clz x8, x3
+; CHECK-SD-NEXT: add x10, x10, #64
; CHECK-SD-NEXT: cmp x3, #0
-; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: csel x2, x8, x9, ne
-; CHECK-SD-NEXT: clz x8, x4
-; CHECK-SD-NEXT: clz x9, x5
-; CHECK-SD-NEXT: add x8, x8, #64
; CHECK-SD-NEXT: cmp x5, #0
+; CHECK-SD-NEXT: csel x4, x11, x10, ne
+; CHECK-SD-NEXT: mov x1, xzr
+; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: mov x5, xzr
-; CHECK-SD-NEXT: csel x4, x9, x8, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v3i128:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov w8, wzr
; CHECK-GI-NEXT: clz x9, x0
-; CHECK-GI-NEXT: clz x11, x1
+; CHECK-GI-NEXT: clz x10, x1
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: adc x10, xzr, xzr
+; CHECK-GI-NEXT: adc x11, xzr, xzr
; CHECK-GI-NEXT: cmp x1, #0
-; CHECK-GI-NEXT: csel x0, x9, x11, eq
+; CHECK-GI-NEXT: csel x0, x9, x10, eq
+; CHECK-GI-NEXT: csel x1, x11, xzr, eq
; CHECK-GI-NEXT: clz x9, x2
-; CHECK-GI-NEXT: csel x1, x10, xzr, eq
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x11, x3
; CHECK-GI-NEXT: adc x10, xzr, xzr
+; CHECK-GI-NEXT: clz x11, x3
; CHECK-GI-NEXT: cmp x3, #0
; CHECK-GI-NEXT: csel x2, x9, x11, eq
; CHECK-GI-NEXT: clz x9, x4
; CHECK-GI-NEXT: csel x3, x10, xzr, eq
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x10, x5
; CHECK-GI-NEXT: adc x8, xzr, xzr
+; CHECK-GI-NEXT: clz x10, x5
; CHECK-GI-NEXT: cmp x5, #0
; CHECK-GI-NEXT: csel x4, x9, x10, eq
; CHECK-GI-NEXT: csel x5, x8, xzr, eq
@@ -513,26 +513,26 @@ define <4 x i128> @v4i128(<4 x i128> %d) {
; CHECK-SD-LABEL: v4i128:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: clz x9, x0
-; CHECK-SD-NEXT: clz x8, x2
; CHECK-SD-NEXT: clz x10, x1
+; CHECK-SD-NEXT: clz x8, x3
; CHECK-SD-NEXT: add x9, x9, #64
; CHECK-SD-NEXT: cmp x1, #0
-; CHECK-SD-NEXT: add x8, x8, #64
+; CHECK-SD-NEXT: mov x1, xzr
; CHECK-SD-NEXT: csel x0, x10, x9, ne
-; CHECK-SD-NEXT: clz x9, x3
+; CHECK-SD-NEXT: clz x9, x2
+; CHECK-SD-NEXT: clz x10, x4
+; CHECK-SD-NEXT: add x9, x9, #64
; CHECK-SD-NEXT: cmp x3, #0
-; CHECK-SD-NEXT: csel x2, x9, x8, ne
-; CHECK-SD-NEXT: clz x8, x4
-; CHECK-SD-NEXT: clz x9, x5
-; CHECK-SD-NEXT: add x8, x8, #64
+; CHECK-SD-NEXT: mov x3, xzr
+; CHECK-SD-NEXT: csel x2, x8, x9, ne
+; CHECK-SD-NEXT: clz x8, x5
+; CHECK-SD-NEXT: add x9, x10, #64
; CHECK-SD-NEXT: cmp x5, #0
-; CHECK-SD-NEXT: mov x1, xzr
-; CHECK-SD-NEXT: csel x4, x9, x8, ne
+; CHECK-SD-NEXT: csel x4, x8, x9, ne
; CHECK-SD-NEXT: clz x8, x6
; CHECK-SD-NEXT: clz x9, x7
; CHECK-SD-NEXT: add x8, x8, #64
; CHECK-SD-NEXT: cmp x7, #0
-; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: csel x6, x9, x8, ne
; CHECK-SD-NEXT: mov x5, xzr
; CHECK-SD-NEXT: mov x7, xzr
@@ -542,37 +542,37 @@ define <4 x i128> @v4i128(<4 x i128> %d) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov w8, wzr
; CHECK-GI-NEXT: clz x9, x0
-; CHECK-GI-NEXT: clz x11, x1
+; CHECK-GI-NEXT: clz x10, x1
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: adc x10, xzr, xzr
+; CHECK-GI-NEXT: adc x11, xzr, xzr
; CHECK-GI-NEXT: cmp x1, #0
-; CHECK-GI-NEXT: csel x0, x9, x11, eq
+; CHECK-GI-NEXT: csel x0, x9, x10, eq
+; CHECK-GI-NEXT: csel x1, x11, xzr, eq
; CHECK-GI-NEXT: clz x9, x2
-; CHECK-GI-NEXT: csel x1, x10, xzr, eq
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x11, x3
; CHECK-GI-NEXT: adc x10, xzr, xzr
+; CHECK-GI-NEXT: clz x11, x3
; CHECK-GI-NEXT: cmp x3, #0
; CHECK-GI-NEXT: csel x2, x9, x11, eq
; CHECK-GI-NEXT: clz x9, x4
; CHECK-GI-NEXT: csel x3, x10, xzr, eq
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x11, x5
; CHECK-GI-NEXT: adc x10, xzr, xzr
+; CHECK-GI-NEXT: clz x11, x5
; CHECK-GI-NEXT: cmp x5, #0
; CHECK-GI-NEXT: csel x4, x9, x11, eq
-; CHECK-GI-NEXT: clz x9, x6
; CHECK-GI-NEXT: csel x5, x10, xzr, eq
+; CHECK-GI-NEXT: clz x9, x6
; CHECK-GI-NEXT: cmp w8, #1
; CHECK-GI-NEXT: add x9, x9, #64
-; CHECK-GI-NEXT: clz x10, x7
-; CHECK-GI-NEXT: adc x8, xzr, xzr
+; CHECK-GI-NEXT: clz x8, x7
+; CHECK-GI-NEXT: adc x10, xzr, xzr
; CHECK-GI-NEXT: cmp x7, #0
-; CHECK-GI-NEXT: csel x6, x9, x10, eq
-; CHECK-GI-NEXT: csel x7, x8, xzr, eq
+; CHECK-GI-NEXT: csel x6, x9, x8, eq
+; CHECK-GI-NEXT: csel x7, x10, xzr, eq
; CHECK-GI-NEXT: ret
entry:
%s = call <4 x i128> @llvm.ctlz(<4 x i128> %d, i1 false)
diff --git a/llvm/test/CodeGen/AArch64/cttz-of-bool-vector-bitcast.ll b/llvm/test/CodeGen/AArch64/cttz-of-bool-vector-bitcast.ll
index f7186dbd2cc7c..eb5e148f82377 100644
--- a/llvm/test/CodeGen/AArch64/cttz-of-bool-vector-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/cttz-of-bool-vector-bitcast.ll
@@ -589,11 +589,11 @@ define i32 @cttz_v32i8(<32 x i8> %v) {
; CHECK-LE-NEXT: mov x8, v0.d[1]
; CHECK-LE-NEXT: fmov x9, d0
; CHECK-LE-NEXT: rbit x10, x9
-; CHECK-LE-NEXT: cmp x9, #0
; CHECK-LE-NEXT: rbit x8, x8
; CHECK-LE-NEXT: clz x10, x10
; CHECK-LE-NEXT: clz x8, x8
; CHECK-LE-NEXT: add x8, x8, #64
+; CHECK-LE-NEXT: cmp x9, #0
; CHECK-LE-NEXT: csel x8, x10, x8, ne
; CHECK-LE-NEXT: lsr x0, x8, #2
; CHECK-LE-NEXT: // kill: def $w0 killed $w0 killed $x0
@@ -613,9 +613,9 @@ define i32 @cttz_v32i8(<32 x i8> %v) {
; CHECK-BE-NEXT: mov x8, v0.d[1]
; CHECK-BE-NEXT: fmov x9, d0
; CHECK-BE-NEXT: clz x10, x9
-; CHECK-BE-NEXT: cmp x9, #0
; CHECK-BE-NEXT: clz x8, x8
; CHECK-BE-NEXT: add x8, x8, #64
+; CHECK-BE-NEXT: cmp x9, #0
; CHECK-BE-NEXT: csel x8, x10, x8, ne
; CHECK-BE-NEXT: lsr x0, x8, #2
; CHECK-BE-NEXT: // kill: def $w0 killed $w0 killed $x0
@@ -640,11 +640,11 @@ define i32 @cttz_v32i16(<32 x i16> %v) {
; CHECK-LE-NEXT: mov x8, v0.d[1]
; CHECK-LE-NEXT: fmov x9, d0
; CHECK-LE-NEXT: rbit x10, x9
-; CHECK-LE-NEXT: cmp x9, #0
; CHECK-LE-NEXT: rbit x8, x8
; CHECK-LE-NEXT: clz x10, x10
; CHECK-LE-NEXT: clz x8, x8
; CHECK-LE-NEXT: add x8, x8, #64
+; CHECK-LE-NEXT: cmp x9, #0
; CHECK-LE-NEXT: csel x8, x10, x8, ne
; CHECK-LE-NEXT: lsr x0, x8, #2
; CHECK-LE-NEXT: // kill: def $w0 killed $w0 killed $x0
@@ -672,9 +672,9 @@ define i32 @cttz_v32i16(<32 x i16> %v) {
; CHECK-BE-NEXT: mov x8, v0.d[1]
; CHECK-BE-NEXT: fmov x9, d0
; CHECK-BE-NEXT: clz x10, x9
-; CHECK-BE-NEXT: cmp x9, #0
; CHECK-BE-NEXT: clz x8, x8
; CHECK-BE-NEXT: add x8, x8, #64
+; CHECK-BE-NEXT: cmp x9, #0
; CHECK-BE-NEXT: csel x8, x10, x8, ne
; CHECK-BE-NEXT: lsr x0, x8, #2
; CHECK-BE-NEXT: // kill: def $w0 killed $w0 killed $x0
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index a7cb028537088..185503f186e08 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -549,21 +549,21 @@ define <2 x i128> @v2i128(<2 x i128> %d) {
; CHECK-SD-LABEL: v2i128:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: rbit x8, x1
+; CHECK-SD-NEXT: rbit x11, x3
; CHECK-SD-NEXT: rbit x9, x0
-; CHECK-SD-NEXT: rbit x10, x3
-; CHECK-SD-NEXT: rbit x11, x2
-; CHECK-SD-NEXT: cmp x0, #0
+; CHECK-SD-NEXT: rbit x10, x2
; CHECK-SD-NEXT: mov x1, xzr
+; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: clz x8, x8
+; CHECK-SD-NEXT: clz x11, x11
; CHECK-SD-NEXT: clz x9, x9
; CHECK-SD-NEXT: clz x10, x10
; CHECK-SD-NEXT: add x8, x8, #64
-; CHECK-SD-NEXT: mov x3, xzr
+; CHECK-SD-NEXT: add x11, x11, #64
+; CHECK-SD-NEXT: cmp x0, #0
; CHECK-SD-NEXT: csel x0, x9, x8, ne
-; CHECK-SD-NEXT: clz x8, x11
-; CHECK-SD-NEXT: add x9, x10, #64
; CHECK-SD-NEXT: cmp x2, #0
-; CHECK-SD-NEXT: csel x2, x8, x9, ne
+; CHECK-SD-NEXT: csel x2, x10, x11, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i128:
@@ -601,27 +601,27 @@ define <3 x i128> @v3i128(<3 x i128> %d) {
; CHECK-SD-NEXT: rbit x8, x1
; CHECK-SD-NEXT: rbit x9, x0
; CHECK-SD-NEXT: rbit x11, x3
-; CHECK-SD-NEXT: rbit x10, x2
-; CHECK-SD-NEXT: cmp x0, #0
; CHECK-SD-NEXT: rbit x12, x5
+; CHECK-SD-NEXT: rbit x10, x2
+; CHECK-SD-NEXT: mov x1, xzr
; CHECK-SD-NEXT: clz x8, x8
; CHECK-SD-NEXT: clz x9, x9
-; CHECK-SD-NEXT: clz x11, x11
+; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: add x8, x8, #64
+; CHECK-SD-NEXT: cmp x0, #0
; CHECK-SD-NEXT: clz x10, x10
-; CHECK-SD-NEXT: mov x1, xzr
; CHECK-SD-NEXT: csel x0, x9, x8, ne
-; CHECK-SD-NEXT: add x8, x11, #64
+; CHECK-SD-NEXT: rbit x8, x4
+; CHECK-SD-NEXT: clz x9, x11
+; CHECK-SD-NEXT: clz x11, x12
+; CHECK-SD-NEXT: add x9, x9, #64
; CHECK-SD-NEXT: cmp x2, #0
-; CHECK-SD-NEXT: rbit x9, x4
-; CHECK-SD-NEXT: csel x2, x10, x8, ne
-; CHECK-SD-NEXT: clz x8, x12
-; CHECK-SD-NEXT: add x8, x8, #64
+; CHECK-SD-NEXT: csel x2, x10, x9, ne
+; CHECK-SD-NEXT: clz x8, x8
+; CHECK-SD-NEXT: add x11, x11, #64
; CHECK-SD-NEXT: cmp x4, #0
-; CHECK-SD-NEXT: mov x3, xzr
-; CHECK-SD-NEXT: clz x9, x9
+; CHECK-SD-NEXT: csel x4, x8, x11, ne
; CHECK-SD-NEXT: mov x5, xzr
-; CHECK-SD-NEXT: csel x4, x9, x8, ne
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v3i128:
@@ -666,38 +666,38 @@ entry:
define <4 x i128> @v4i128(<4 x i128> %d) {
; CHECK-SD-LABEL: v4i128:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: rbit x9, x1
-; CHECK-SD-NEXT: rbit x10, x0
-; CHECK-SD-NEXT: rbit x8, x3
-; CHECK-SD-NEXT: rbit x11, x2
-; CHECK-SD-NEXT: cmp x0, #0
+; CHECK-SD-NEXT: rbit x10, x1
+; CHECK-SD-NEXT: rbit x9, x0
+; CHECK-SD-NEXT: rbit x11, x3
+; CHECK-SD-NEXT: rbit x8, x2
; CHECK-SD-NEXT: mov x1, xzr
-; CHECK-SD-NEXT: clz x9, x9
+; CHECK-SD-NEXT: mov x3, xzr
; CHECK-SD-NEXT: clz x10, x10
+; CHECK-SD-NEXT: clz x9, x9
+; CHECK-SD-NEXT: add x10, x10, #64
+; CHECK-SD-NEXT: cmp x0, #0
; CHECK-SD-NEXT: clz x8, x8
-; CHECK-SD-NEXT: add x9, x9, #64
-; CHECK-SD-NEXT: add x8, x8, #64
-; CHECK-SD-NEXT: mov x3, xzr
-; CHECK-SD-NEXT: csel x0, x10, x9, ne
+; CHECK-SD-NEXT: csel x0, x9, x10, ne
; CHECK-SD-NEXT: clz x9, x11
-; CHECK-SD-NEXT: rbit x10, x4
-; CHECK-SD-NEXT: rbit x11, x5
+; CHECK-SD-NEXT: rbit x10, x5
+; CHECK-SD-NEXT: add x9, x9, #64
+; CHECK-SD-NEXT: rbit x11, x4
; CHECK-SD-NEXT: cmp x2, #0
-; CHECK-SD-NEXT: mov x5, xzr
-; CHECK-SD-NEXT: csel x2, x9, x8, ne
+; CHECK-SD-NEXT: csel x2, x8, x9, ne
; CHECK-SD-NEXT: clz x8, x10
-; CHECK-SD-NEXT: rbit x10, x7
-; CHECK-SD-NEXT: clz x9, x11
-; CHECK-SD-NEXT: cmp x4, #0
+; CHECK-SD-NEXT: rbit x9, x7
+; CHECK-SD-NEXT: clz x10, x11
+; CHECK-SD-NEXT: add x8, x8, #64
; CHECK-SD-NEXT: rbit x11, x6
-; CHECK-SD-NEXT: add x9, x9, #64
-; CHECK-SD-NEXT: mov x7, xzr
-; CHECK-SD-NEXT: csel x4, x8, x9, ne
-; CHECK-SD-NEXT: clz x8, x10
+; CHECK-SD-NEXT: cmp x4, #0
+; CHECK-SD-NEXT: csel x4, x10, x8, ne
+; CHECK-SD-NEXT: clz x8, x9
; CHECK-SD-NEXT: clz x9, x11
; CHECK-SD-NEXT: add x8, x8, #64
; CHECK-SD-NEXT: cmp x6, #0
; CHECK-SD-NEXT: csel x6, x9, x8, ne
+; CHECK-SD-NEXT: mov x5, xzr
+; CHECK-SD-NEXT: mov x7, xzr
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v4i128:
diff --git a/llvm/test/CodeGen/AArch64/dag-combine-select.ll b/llvm/test/CodeGen/AArch64/dag-combine-select.ll
index 02b007704994a..c4618eb29dc78 100644
--- a/llvm/test/CodeGen/AArch64/dag-combine-select.ll
+++ b/llvm/test/CodeGen/AArch64/dag-combine-select.ll
@@ -35,8 +35,8 @@ define void @test1(i32 %bitset, i32 %val0, i32 %val1) {
; CHECK-SD-LABEL: test1:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: cmp w0, #7
-; CHECK-SD-NEXT: adrp x9, out
; CHECK-SD-NEXT: csel w8, w1, w2, eq
+; CHECK-SD-NEXT: adrp x9, out
; CHECK-SD-NEXT: cmp w8, #13
; CHECK-SD-NEXT: csel w8, w1, w2, lo
; CHECK-SD-NEXT: cmp w0, #42
diff --git a/llvm/test/CodeGen/AArch64/div-i256.ll b/llvm/test/CodeGen/AArch64/div-i256.ll
index 5f8d362c85bb2..65b61a44e9c8f 100644
--- a/llvm/test/CodeGen/AArch64/div-i256.ll
+++ b/llvm/test/CodeGen/AArch64/div-i256.ll
@@ -9,46 +9,46 @@ define i256 @udiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: orr x10, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: orr x9, x1, x3
-; CHECK-NEXT: clz x11, x5
+; CHECK-NEXT: clz x11, x4
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: orr x8, x10, x9
; CHECK-NEXT: clz x10, x7
; CHECK-NEXT: ccmp x8, #0, #4, ne
; CHECK-NEXT: clz x8, x6
-; CHECK-NEXT: clz x12, x1
+; CHECK-NEXT: clz x12, x5
; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: add x8, x8, #64
+; CHECK-NEXT: add x11, x11, #64
; CHECK-NEXT: cmp x7, #0
; CHECK-NEXT: csel x8, x10, x8, ne
-; CHECK-NEXT: clz x10, x4
+; CHECK-NEXT: clz x13, x1
; CHECK-NEXT: cmp x5, #0
-; CHECK-NEXT: add x10, x10, #64
-; CHECK-NEXT: csel x10, x11, x10, ne
+; CHECK-NEXT: csel x10, x12, x11, ne
; CHECK-NEXT: orr x11, x6, x7
; CHECK-NEXT: add x10, x10, #128
; CHECK-NEXT: cmp x11, #0
-; CHECK-NEXT: clz x11, x3
+; CHECK-NEXT: clz x12, x0
; CHECK-NEXT: csel x8, x8, x10, ne
; CHECK-NEXT: clz x10, x2
-; CHECK-NEXT: cmp x3, #0
+; CHECK-NEXT: clz x11, x3
; CHECK-NEXT: add x10, x10, #64
+; CHECK-NEXT: add x12, x12, #64
+; CHECK-NEXT: cmp x3, #0
; CHECK-NEXT: csel x10, x11, x10, ne
-; CHECK-NEXT: clz x11, x0
; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: add x11, x11, #64
-; CHECK-NEXT: csel x11, x12, x11, ne
-; CHECK-NEXT: orr x12, x2, x3
+; CHECK-NEXT: csel x11, x13, x12, ne
; CHECK-NEXT: add x11, x11, #128
+; CHECK-NEXT: orr x12, x2, x3
; CHECK-NEXT: cmp x12, #0
; CHECK-NEXT: csel x10, x10, x11, ne
; CHECK-NEXT: subs x15, x8, x10
; CHECK-NEXT: mov w8, #255 // =0xff
-; CHECK-NEXT: ngcs x13, xzr
; CHECK-NEXT: ngcs x14, xzr
+; CHECK-NEXT: ngcs x13, xzr
; CHECK-NEXT: ngc x12, xzr
; CHECK-NEXT: cmp x8, x15
-; CHECK-NEXT: ngcs xzr, x13
; CHECK-NEXT: ngcs xzr, x14
+; CHECK-NEXT: ngcs xzr, x13
; CHECK-NEXT: ngcs xzr, x12
; CHECK-NEXT: csinc w16, w9, wzr, hs
; CHECK-NEXT: cmp w16, #0
@@ -59,8 +59,8 @@ define i256 @udiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: tbnz w16, #0, .LBB0_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x16, x15, #0xff
-; CHECK-NEXT: orr x17, x13, x12
-; CHECK-NEXT: orr x16, x16, x14
+; CHECK-NEXT: orr x17, x14, x12
+; CHECK-NEXT: orr x16, x16, x13
; CHECK-NEXT: orr x16, x16, x17
; CHECK-NEXT: cbz x16, .LBB0_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -73,39 +73,39 @@ define i256 @udiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: stp x3, x27, [sp, #120] // 8-byte Folded Spill
; CHECK-NEXT: lsr x8, x11, #3
; CHECK-NEXT: stp x26, x25, [sp, #144] // 16-byte Folded Spill
-; CHECK-NEXT: and x18, x11, #0x3f
; CHECK-NEXT: stp x24, x23, [sp, #160] // 16-byte Folded Spill
-; CHECK-NEXT: eor x18, x18, #0x3f
; CHECK-NEXT: and x8, x8, #0x18
; CHECK-NEXT: stp x22, x21, [sp, #176] // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #192] // 16-byte Folded Spill
; CHECK-NEXT: sub x16, x9, x8
; CHECK-NEXT: adds x8, x15, #1
; CHECK-NEXT: stp x0, x1, [sp, #96]
-; CHECK-NEXT: adcs x9, x13, xzr
+; CHECK-NEXT: adcs x9, x14, xzr
; CHECK-NEXT: mvn w19, w11
; CHECK-NEXT: str x2, [sp, #112]
-; CHECK-NEXT: adcs x10, x14, xzr
+; CHECK-NEXT: adcs x10, x13, xzr
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: ldp x15, x17, [x16, #8]
-; CHECK-NEXT: ldr x13, [x16, #24]
-; CHECK-NEXT: ldr x16, [x16]
+; CHECK-NEXT: ldp x15, x18, [x16, #8]
+; CHECK-NEXT: ldr x13, [x16]
+; CHECK-NEXT: ldr x17, [x16, #24]
+; CHECK-NEXT: and x16, x11, #0x3f
+; CHECK-NEXT: lsr x21, x13, #1
+; CHECK-NEXT: eor x16, x16, #0x3f
; CHECK-NEXT: lsr x14, x15, #1
-; CHECK-NEXT: lsr x20, x17, #1
-; CHECK-NEXT: lsr x21, x16, #1
-; CHECK-NEXT: lsl x17, x17, x11
+; CHECK-NEXT: lsr x20, x18, #1
+; CHECK-NEXT: lsl x18, x18, x11
; CHECK-NEXT: lsr x19, x14, x19
; CHECK-NEXT: adcs x14, x12, xzr
-; CHECK-NEXT: lsl x12, x13, x11
-; CHECK-NEXT: lsr x13, x20, x18
+; CHECK-NEXT: lsl x12, x17, x11
+; CHECK-NEXT: lsr x17, x20, x16
; CHECK-NEXT: lsl x20, x15, x11
-; CHECK-NEXT: lsr x18, x21, x18
-; CHECK-NEXT: lsl x11, x16, x11
+; CHECK-NEXT: lsr x16, x21, x16
+; CHECK-NEXT: lsl x11, x13, x11
; CHECK-NEXT: cset w21, hs
+; CHECK-NEXT: orr x13, x18, x19
+; CHECK-NEXT: orr x15, x12, x17
+; CHECK-NEXT: orr x12, x20, x16
; CHECK-NEXT: mov x16, xzr
-; CHECK-NEXT: orr x15, x12, x13
-; CHECK-NEXT: orr x13, x17, x19
-; CHECK-NEXT: orr x12, x20, x18
; CHECK-NEXT: tbnz w21, #0, .LBB0_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
; CHECK-NEXT: lsr x20, x8, #3
@@ -202,82 +202,82 @@ define i256 @udiv256(i256 %a, i256 %b) nounwind {
define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: sdiv256:
; CHECK: // %bb.0: // %_udiv-special-cases
-; CHECK-NEXT: asr x12, x3, #63
+; CHECK-NEXT: asr x11, x3, #63
; CHECK-NEXT: asr x13, x7, #63
-; CHECK-NEXT: eor x8, x0, x12
-; CHECK-NEXT: eor x9, x1, x12
-; CHECK-NEXT: eor x10, x4, x13
-; CHECK-NEXT: subs x14, x8, x12
-; CHECK-NEXT: eor x8, x2, x12
-; CHECK-NEXT: eor x11, x5, x13
-; CHECK-NEXT: sbcs x15, x9, x12
-; CHECK-NEXT: eor x9, x3, x12
-; CHECK-NEXT: clz x16, x14
-; CHECK-NEXT: sbcs x18, x8, x12
-; CHECK-NEXT: clz x17, x15
-; CHECK-NEXT: add x16, x16, #64
-; CHECK-NEXT: sbc x0, x9, x12
-; CHECK-NEXT: subs x8, x10, x13
+; CHECK-NEXT: eor x8, x0, x11
+; CHECK-NEXT: eor x10, x1, x11
+; CHECK-NEXT: eor x9, x3, x11
+; CHECK-NEXT: subs x14, x8, x11
+; CHECK-NEXT: eor x8, x2, x11
+; CHECK-NEXT: eor x15, x4, x13
+; CHECK-NEXT: sbcs x17, x10, x11
+; CHECK-NEXT: eor x16, x5, x13
; CHECK-NEXT: eor x10, x6, x13
-; CHECK-NEXT: sbcs x9, x11, x13
-; CHECK-NEXT: eor x11, x7, x13
-; CHECK-NEXT: orr x1, x14, x18
+; CHECK-NEXT: sbcs x18, x8, x11
+; CHECK-NEXT: eor x12, x7, x13
+; CHECK-NEXT: clz x1, x17
+; CHECK-NEXT: sbc x0, x9, x11
+; CHECK-NEXT: subs x8, x15, x13
+; CHECK-NEXT: clz x15, x14
+; CHECK-NEXT: sbcs x9, x16, x13
+; CHECK-NEXT: orr x16, x14, x18
+; CHECK-NEXT: orr x3, x17, x0
; CHECK-NEXT: sbcs x10, x10, x13
-; CHECK-NEXT: orr x4, x15, x0
-; CHECK-NEXT: clz x5, x8
-; CHECK-NEXT: sbc x11, x11, x13
-; CHECK-NEXT: orr x2, x8, x10
-; CHECK-NEXT: orr x1, x1, x4
-; CHECK-NEXT: orr x3, x9, x11
-; CHECK-NEXT: add x5, x5, #64
-; CHECK-NEXT: orr x6, x10, x11
-; CHECK-NEXT: orr x2, x2, x3
-; CHECK-NEXT: clz x3, x10
-; CHECK-NEXT: eor x12, x13, x12
-; CHECK-NEXT: cmp x2, #0
-; CHECK-NEXT: add x3, x3, #64
-; CHECK-NEXT: clz x2, x9
-; CHECK-NEXT: ccmp x1, #0, #4, ne
-; CHECK-NEXT: clz x1, x11
-; CHECK-NEXT: cset w4, eq
-; CHECK-NEXT: cmp x11, #0
-; CHECK-NEXT: csel x1, x1, x3, ne
+; CHECK-NEXT: orr x16, x16, x3
+; CHECK-NEXT: clz x4, x8
+; CHECK-NEXT: sbc x12, x12, x13
+; CHECK-NEXT: orr x5, x8, x10
+; CHECK-NEXT: clz x3, x9
+; CHECK-NEXT: orr x6, x9, x12
+; CHECK-NEXT: add x4, x4, #64
+; CHECK-NEXT: clz x2, x18
+; CHECK-NEXT: orr x5, x5, x6
+; CHECK-NEXT: clz x6, x10
+; CHECK-NEXT: add x15, x15, #64
+; CHECK-NEXT: cmp x5, #0
+; CHECK-NEXT: add x5, x6, #64
+; CHECK-NEXT: clz x6, x12
+; CHECK-NEXT: ccmp x16, #0, #4, ne
+; CHECK-NEXT: add x2, x2, #64
+; CHECK-NEXT: eor x11, x13, x11
+; CHECK-NEXT: cset w7, eq
+; CHECK-NEXT: cmp x12, #0
+; CHECK-NEXT: csel x16, x6, x5, ne
+; CHECK-NEXT: orr x5, x10, x12
; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: clz x3, x18
-; CHECK-NEXT: csel x2, x2, x5, ne
-; CHECK-NEXT: cmp x6, #0
-; CHECK-NEXT: add x3, x3, #64
-; CHECK-NEXT: add x2, x2, #128
-; CHECK-NEXT: clz x5, x0
-; CHECK-NEXT: csel x1, x1, x2, ne
+; CHECK-NEXT: csel x3, x3, x4, ne
+; CHECK-NEXT: add x3, x3, #128
+; CHECK-NEXT: cmp x5, #0
+; CHECK-NEXT: clz x4, x0
+; CHECK-NEXT: csel x16, x16, x3, ne
; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: csel x2, x5, x3, ne
-; CHECK-NEXT: cmp x15, #0
-; CHECK-NEXT: orr x3, x18, x0
-; CHECK-NEXT: csel x16, x17, x16, ne
-; CHECK-NEXT: cmp x3, #0
+; CHECK-NEXT: csel x2, x4, x2, ne
+; CHECK-NEXT: cmp x17, #0
+; CHECK-NEXT: csel x15, x1, x15, ne
+; CHECK-NEXT: orr x1, x18, x0
+; CHECK-NEXT: add x15, x15, #128
+; CHECK-NEXT: cmp x1, #0
; CHECK-NEXT: mov w3, #255 // =0xff
-; CHECK-NEXT: add x16, x16, #128
-; CHECK-NEXT: csel x16, x2, x16, ne
-; CHECK-NEXT: subs x2, x1, x16
+; CHECK-NEXT: csel x15, x2, x15, ne
+; CHECK-NEXT: subs x2, x16, x15
+; CHECK-NEXT: ngcs x15, xzr
; CHECK-NEXT: ngcs x16, xzr
-; CHECK-NEXT: ngcs x17, xzr
; CHECK-NEXT: ngc x1, xzr
; CHECK-NEXT: cmp x3, x2
+; CHECK-NEXT: ngcs xzr, x15
; CHECK-NEXT: ngcs xzr, x16
-; CHECK-NEXT: ngcs xzr, x17
; CHECK-NEXT: ngcs xzr, x1
-; CHECK-NEXT: csinc w5, w4, wzr, hs
+; CHECK-NEXT: csinc w5, w7, wzr, hs
; CHECK-NEXT: cmp w5, #0
; CHECK-NEXT: csel x13, xzr, x0, ne
; CHECK-NEXT: csel x4, xzr, x18, ne
-; CHECK-NEXT: csel x7, xzr, x15, ne
+; CHECK-NEXT: csel x7, xzr, x17, ne
; CHECK-NEXT: csel x3, xzr, x14, ne
; CHECK-NEXT: tbnz w5, #0, .LBB1_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
; CHECK-NEXT: eor x5, x2, #0xff
-; CHECK-NEXT: orr x6, x16, x1
-; CHECK-NEXT: orr x5, x5, x17
+; CHECK-NEXT: orr x6, x15, x1
+; CHECK-NEXT: orr x5, x5, x16
; CHECK-NEXT: orr x5, x5, x6
; CHECK-NEXT: cbz x5, .LBB1_6
; CHECK-NEXT: // %bb.2: // %udiv-bb1
@@ -296,14 +296,14 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: stp x20, x19, [sp, #192] // 16-byte Folded Spill
; CHECK-NEXT: sub x4, x4, x13
; CHECK-NEXT: adds x13, x2, #1
-; CHECK-NEXT: stp x14, x15, [sp, #96]
+; CHECK-NEXT: stp x14, x17, [sp, #96]
; CHECK-NEXT: and x19, x3, #0x3f
-; CHECK-NEXT: adcs x16, x16, xzr
+; CHECK-NEXT: adcs x15, x15, xzr
; CHECK-NEXT: stp x18, x0, [sp, #112]
; CHECK-NEXT: mvn w20, w3
; CHECK-NEXT: eor x19, x19, #0x3f
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: adcs x17, x17, xzr
+; CHECK-NEXT: adcs x16, x16, xzr
; CHECK-NEXT: ldp x2, x6, [x4, #8]
; CHECK-NEXT: ldr x7, [x4]
; CHECK-NEXT: ldr x5, [x4, #24]
@@ -326,37 +326,37 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: tbnz w22, #0, .LBB1_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
; CHECK-NEXT: lsr x21, x13, #3
-; CHECK-NEXT: stp x14, x15, [sp]
-; CHECK-NEXT: mov x15, sp
+; CHECK-NEXT: stp x14, x17, [sp]
+; CHECK-NEXT: mov x17, sp
; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
; CHECK-NEXT: and x14, x21, #0x18
; CHECK-NEXT: stp x18, x0, [sp, #16]
; CHECK-NEXT: and x0, x13, #0x3f
-; CHECK-NEXT: add x14, x15, x14
+; CHECK-NEXT: add x14, x17, x14
; CHECK-NEXT: mvn w21, w13
; CHECK-NEXT: eor x0, x0, #0x3f
-; CHECK-NEXT: ldp x15, x18, [x14, #16]
+; CHECK-NEXT: ldp x17, x18, [x14, #16]
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: ldp x24, x22, [x14]
-; CHECK-NEXT: lsl x14, x15, #1
+; CHECK-NEXT: lsl x14, x17, #1
; CHECK-NEXT: lsl x23, x18, #1
-; CHECK-NEXT: lsr x25, x15, x13
-; CHECK-NEXT: lsl x15, x22, #1
+; CHECK-NEXT: lsr x25, x17, x13
+; CHECK-NEXT: lsl x17, x22, #1
; CHECK-NEXT: lsr x27, x22, x13
; CHECK-NEXT: lsr x28, x24, x13
; CHECK-NEXT: lsl x26, x14, x21
; CHECK-NEXT: subs x14, x8, #1
; CHECK-NEXT: lsl x23, x23, x0
-; CHECK-NEXT: lsl x0, x15, x0
-; CHECK-NEXT: sbcs x15, x9, xzr
+; CHECK-NEXT: lsl x0, x17, x0
+; CHECK-NEXT: sbcs x17, x9, xzr
; CHECK-NEXT: lsr x22, x18, x13
; CHECK-NEXT: sbcs x18, x10, xzr
; CHECK-NEXT: orr x21, x23, x25
; CHECK-NEXT: orr x24, x27, x26
; CHECK-NEXT: orr x23, x0, x28
-; CHECK-NEXT: sbc x0, x11, xzr
+; CHECK-NEXT: sbc x0, x12, xzr
; CHECK-NEXT: .LBB1_4: // %udiv-do-while
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: extr x25, x23, x5, #63
@@ -366,7 +366,7 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: extr x5, x5, x3, #63
; CHECK-NEXT: extr x3, x3, x2, #63
; CHECK-NEXT: cmp x14, x25
-; CHECK-NEXT: sbcs xzr, x15, x26
+; CHECK-NEXT: sbcs xzr, x17, x26
; CHECK-NEXT: orr x3, x20, x3
; CHECK-NEXT: orr x5, x7, x5
; CHECK-NEXT: sbcs xzr, x18, x27
@@ -376,21 +376,21 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: and x21, x28, x8
; CHECK-NEXT: subs x23, x25, x21
; CHECK-NEXT: and x21, x28, x9
-; CHECK-NEXT: and x25, x28, x11
+; CHECK-NEXT: and x25, x28, x12
; CHECK-NEXT: sbcs x24, x26, x21
; CHECK-NEXT: and x21, x28, x10
; CHECK-NEXT: sbcs x21, x27, x21
; CHECK-NEXT: sbc x22, x22, x25
; CHECK-NEXT: subs x13, x13, #1
; CHECK-NEXT: extr x25, x2, x1, #63
-; CHECK-NEXT: sbcs x16, x16, xzr
+; CHECK-NEXT: sbcs x15, x15, xzr
; CHECK-NEXT: orr x1, x6, x1, lsl #1
; CHECK-NEXT: and x6, x28, #0x1
-; CHECK-NEXT: sbcs x17, x17, xzr
+; CHECK-NEXT: sbcs x16, x16, xzr
; CHECK-NEXT: orr x2, x19, x25
; CHECK-NEXT: sbc x4, x4, xzr
-; CHECK-NEXT: orr x20, x13, x17
-; CHECK-NEXT: orr x19, x16, x4
+; CHECK-NEXT: orr x20, x13, x16
+; CHECK-NEXT: orr x19, x15, x4
; CHECK-NEXT: orr x25, x20, x19
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
@@ -407,14 +407,14 @@ define i256 @sdiv256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: ldp x28, x27, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #208
; CHECK-NEXT: .LBB1_6: // %udiv-end
-; CHECK-NEXT: eor x8, x3, x12
-; CHECK-NEXT: eor x9, x7, x12
-; CHECK-NEXT: subs x0, x8, x12
-; CHECK-NEXT: eor x8, x4, x12
-; CHECK-NEXT: sbcs x1, x9, x12
-; CHECK-NEXT: eor x9, x13, x12
-; CHECK-NEXT: sbcs x2, x8, x12
-; CHECK-NEXT: sbc x3, x9, x12
+; CHECK-NEXT: eor x8, x3, x11
+; CHECK-NEXT: eor x9, x7, x11
+; CHECK-NEXT: subs x0, x8, x11
+; CHECK-NEXT: eor x8, x4, x11
+; CHECK-NEXT: sbcs x1, x9, x11
+; CHECK-NEXT: eor x9, x13, x11
+; CHECK-NEXT: sbcs x2, x8, x11
+; CHECK-NEXT: sbc x3, x9, x11
; CHECK-NEXT: ret
%r = sdiv i256 %a, %b
ret i256 %r
@@ -428,36 +428,36 @@ define i256 @urem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: orr x10, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: orr x9, x1, x3
-; CHECK-NEXT: clz x11, x1
+; CHECK-NEXT: clz x11, x5
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: orr x8, x10, x9
-; CHECK-NEXT: clz x9, x7
+; CHECK-NEXT: clz x10, x4
; CHECK-NEXT: ccmp x8, #0, #4, ne
; CHECK-NEXT: clz x8, x6
-; CHECK-NEXT: clz x10, x5
+; CHECK-NEXT: clz x9, x7
; CHECK-NEXT: cset w13, eq
; CHECK-NEXT: add x8, x8, #64
+; CHECK-NEXT: add x10, x10, #64
; CHECK-NEXT: cmp x7, #0
; CHECK-NEXT: csel x8, x9, x8, ne
-; CHECK-NEXT: clz x9, x4
+; CHECK-NEXT: clz x12, x1
; CHECK-NEXT: cmp x5, #0
-; CHECK-NEXT: add x9, x9, #64
-; CHECK-NEXT: csel x9, x10, x9, ne
+; CHECK-NEXT: csel x9, x11, x10, ne
; CHECK-NEXT: orr x10, x6, x7
; CHECK-NEXT: add x9, x9, #128
; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: clz x10, x3
+; CHECK-NEXT: clz x11, x0
; CHECK-NEXT: csel x8, x8, x9, ne
; CHECK-NEXT: clz x9, x2
-; CHECK-NEXT: cmp x3, #0
+; CHECK-NEXT: clz x10, x3
; CHECK-NEXT: add x9, x9, #64
+; CHECK-NEXT: add x11, x11, #64
+; CHECK-NEXT: cmp x3, #0
; CHECK-NEXT: csel x9, x10, x9, ne
-; CHECK-NEXT: clz x10, x0
; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: add x10, x10, #64
-; CHECK-NEXT: csel x10, x11, x10, ne
-; CHECK-NEXT: orr x11, x2, x3
+; CHECK-NEXT: csel x10, x12, x11, ne
; CHECK-NEXT: add x10, x10, #128
+; CHECK-NEXT: orr x11, x2, x3
; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: csel x9, x9, x10, ne
; CHECK-NEXT: subs x12, x8, x9
@@ -659,64 +659,64 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: asr x16, x7, #63
; CHECK-NEXT: stp x24, x23, [sp, #192] // 16-byte Folded Spill
; CHECK-NEXT: eor x9, x0, x8
-; CHECK-NEXT: eor x10, x1, x8
-; CHECK-NEXT: eor x11, x2, x8
+; CHECK-NEXT: eor x11, x1, x8
+; CHECK-NEXT: eor x12, x2, x8
; CHECK-NEXT: subs x22, x9, x8
-; CHECK-NEXT: eor x13, x3, x8
-; CHECK-NEXT: eor x14, x4, x16
-; CHECK-NEXT: sbcs x23, x10, x8
-; CHECK-NEXT: eor x15, x5, x16
-; CHECK-NEXT: eor x17, x6, x16
-; CHECK-NEXT: sbcs x12, x11, x8
-; CHECK-NEXT: eor x18, x7, x16
-; CHECK-NEXT: clz x0, x23
-; CHECK-NEXT: sbc x11, x13, x8
-; CHECK-NEXT: subs x13, x14, x16
-; CHECK-NEXT: stp x29, x30, [sp, #144] // 16-byte Folded Spill
-; CHECK-NEXT: sbcs x14, x15, x16
-; CHECK-NEXT: orr x3, x23, x11
-; CHECK-NEXT: clz x4, x13
-; CHECK-NEXT: sbcs x15, x17, x16
-; CHECK-NEXT: add x4, x4, #64
-; CHECK-NEXT: clz x17, x22
-; CHECK-NEXT: sbc x16, x18, x16
-; CHECK-NEXT: orr x1, x13, x15
-; CHECK-NEXT: orr x18, x22, x12
-; CHECK-NEXT: orr x2, x14, x16
-; CHECK-NEXT: orr x18, x18, x3
-; CHECK-NEXT: orr x5, x15, x16
-; CHECK-NEXT: orr x1, x1, x2
-; CHECK-NEXT: clz x2, x15
+; CHECK-NEXT: eor x10, x3, x8
+; CHECK-NEXT: eor x13, x4, x16
+; CHECK-NEXT: sbcs x23, x11, x8
+; CHECK-NEXT: eor x14, x5, x16
+; CHECK-NEXT: eor x15, x6, x16
+; CHECK-NEXT: sbcs x12, x12, x8
+; CHECK-NEXT: eor x17, x7, x16
+; CHECK-NEXT: clz x18, x22
+; CHECK-NEXT: sbc x10, x10, x8
+; CHECK-NEXT: subs x13, x13, x16
+; CHECK-NEXT: orr x1, x22, x12
+; CHECK-NEXT: sbcs x14, x14, x16
+; CHECK-NEXT: orr x3, x23, x10
+; CHECK-NEXT: clz x2, x12
+; CHECK-NEXT: sbcs x15, x15, x16
+; CHECK-NEXT: orr x1, x1, x3
+; CHECK-NEXT: clz x3, x14
+; CHECK-NEXT: sbc x16, x17, x16
+; CHECK-NEXT: orr x4, x13, x15
+; CHECK-NEXT: clz x17, x13
+; CHECK-NEXT: orr x5, x14, x16
; CHECK-NEXT: add x17, x17, #64
-; CHECK-NEXT: cmp x1, #0
+; CHECK-NEXT: clz x0, x23
+; CHECK-NEXT: orr x4, x4, x5
+; CHECK-NEXT: clz x5, x15
+; CHECK-NEXT: add x18, x18, #64
+; CHECK-NEXT: cmp x4, #0
+; CHECK-NEXT: add x4, x5, #64
+; CHECK-NEXT: clz x5, x16
+; CHECK-NEXT: ccmp x1, #0, #4, ne
+; CHECK-NEXT: orr x1, x15, x16
; CHECK-NEXT: add x2, x2, #64
-; CHECK-NEXT: clz x1, x14
-; CHECK-NEXT: ccmp x18, #0, #4, ne
-; CHECK-NEXT: clz x18, x16
-; CHECK-NEXT: stp x28, x27, [sp, #160] // 16-byte Folded Spill
-; CHECK-NEXT: cset w3, eq
+; CHECK-NEXT: cset w6, eq
; CHECK-NEXT: cmp x16, #0
-; CHECK-NEXT: stp x26, x25, [sp, #176] // 16-byte Folded Spill
-; CHECK-NEXT: csel x18, x18, x2, ne
+; CHECK-NEXT: csel x4, x5, x4, ne
; CHECK-NEXT: cmp x14, #0
-; CHECK-NEXT: clz x2, x12
-; CHECK-NEXT: csel x1, x1, x4, ne
-; CHECK-NEXT: cmp x5, #0
-; CHECK-NEXT: add x2, x2, #64
-; CHECK-NEXT: add x1, x1, #128
-; CHECK-NEXT: clz x4, x11
-; CHECK-NEXT: stp x20, x19, [sp, #224] // 16-byte Folded Spill
-; CHECK-NEXT: csel x18, x18, x1, ne
-; CHECK-NEXT: cmp x11, #0
-; CHECK-NEXT: csel x1, x4, x2, ne
-; CHECK-NEXT: cmp x23, #0
-; CHECK-NEXT: orr x2, x12, x11
-; CHECK-NEXT: csel x17, x0, x17, ne
-; CHECK-NEXT: cmp x2, #0
+; CHECK-NEXT: csel x17, x3, x17, ne
+; CHECK-NEXT: stp x29, x30, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT: add x17, x17, #128
-; CHECK-NEXT: csel x17, x1, x17, ne
-; CHECK-NEXT: subs x2, x18, x17
+; CHECK-NEXT: cmp x1, #0
+; CHECK-NEXT: clz x1, x10
+; CHECK-NEXT: csel x17, x4, x17, ne
+; CHECK-NEXT: cmp x10, #0
+; CHECK-NEXT: csel x1, x1, x2, ne
+; CHECK-NEXT: cmp x23, #0
+; CHECK-NEXT: csel x18, x0, x18, ne
+; CHECK-NEXT: orr x0, x12, x10
+; CHECK-NEXT: add x18, x18, #128
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: stp x28, x27, [sp, #160] // 16-byte Folded Spill
+; CHECK-NEXT: csel x18, x1, x18, ne
+; CHECK-NEXT: stp x26, x25, [sp, #176] // 16-byte Folded Spill
+; CHECK-NEXT: subs x2, x17, x18
; CHECK-NEXT: mov w17, #255 // =0xff
+; CHECK-NEXT: stp x20, x19, [sp, #224] // 16-byte Folded Spill
; CHECK-NEXT: ngcs x18, xzr
; CHECK-NEXT: ngcs x0, xzr
; CHECK-NEXT: ngc x1, xzr
@@ -724,9 +724,9 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: ngcs xzr, x18
; CHECK-NEXT: ngcs xzr, x0
; CHECK-NEXT: ngcs xzr, x1
-; CHECK-NEXT: csinc w5, w3, wzr, hs
+; CHECK-NEXT: csinc w5, w6, wzr, hs
; CHECK-NEXT: cmp w5, #0
-; CHECK-NEXT: csel x3, xzr, x11, ne
+; CHECK-NEXT: csel x3, xzr, x10, ne
; CHECK-NEXT: csel x7, xzr, x12, ne
; CHECK-NEXT: csel x4, xzr, x23, ne
; CHECK-NEXT: csel x17, xzr, x22, ne
@@ -744,32 +744,32 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: sub x9, x9, x2
; CHECK-NEXT: add x17, x17, #32
; CHECK-NEXT: stp x22, x23, [sp, #112]
-; CHECK-NEXT: lsr x10, x9, #3
-; CHECK-NEXT: stp x12, x11, [sp, #128]
+; CHECK-NEXT: lsr x11, x9, #3
+; CHECK-NEXT: stp x12, x10, [sp, #128]
; CHECK-NEXT: and x6, x9, #0x3f
; CHECK-NEXT: mvn w7, w9
; CHECK-NEXT: eor x6, x6, #0x3f
-; CHECK-NEXT: and x10, x10, #0x18
+; CHECK-NEXT: and x11, x11, #0x18
; CHECK-NEXT: stp q0, q0, [sp, #80]
-; CHECK-NEXT: sub x10, x17, x10
+; CHECK-NEXT: sub x11, x17, x11
; CHECK-NEXT: adds x17, x2, #1
-; CHECK-NEXT: ldp x2, x5, [x10, #8]
-; CHECK-NEXT: ldr x3, [x10, #24]
-; CHECK-NEXT: ldr x10, [x10]
+; CHECK-NEXT: ldp x2, x5, [x11, #8]
+; CHECK-NEXT: ldr x3, [x11, #24]
+; CHECK-NEXT: ldr x11, [x11]
; CHECK-NEXT: adcs x18, x18, xzr
; CHECK-NEXT: stp x23, x22, [sp] // 16-byte Folded Spill
; CHECK-NEXT: adcs x0, x0, xzr
; CHECK-NEXT: lsl x3, x3, x9
; CHECK-NEXT: lsr x4, x2, #1
; CHECK-NEXT: lsr x19, x5, #1
-; CHECK-NEXT: lsr x20, x10, #1
+; CHECK-NEXT: lsr x20, x11, #1
; CHECK-NEXT: lsl x21, x5, x9
; CHECK-NEXT: lsl x2, x2, x9
; CHECK-NEXT: lsr x7, x4, x7
; CHECK-NEXT: lsr x19, x19, x6
; CHECK-NEXT: lsr x6, x20, x6
; CHECK-NEXT: adcs x4, x1, xzr
-; CHECK-NEXT: lsl x1, x10, x9
+; CHECK-NEXT: lsl x1, x11, x9
; CHECK-NEXT: cset w20, hs
; CHECK-NEXT: orr x5, x3, x19
; CHECK-NEXT: orr x3, x21, x7
@@ -778,21 +778,21 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: tbnz w20, #0, .LBB3_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
; CHECK-NEXT: lsr x9, x17, #3
-; CHECK-NEXT: add x10, sp, #16
+; CHECK-NEXT: add x11, sp, #16
; CHECK-NEXT: stp q0, q0, [sp, #48]
; CHECK-NEXT: stp x22, x23, [sp, #16]
; CHECK-NEXT: and x22, x17, #0x3f
; CHECK-NEXT: mvn w23, w17
; CHECK-NEXT: and x9, x9, #0x18
-; CHECK-NEXT: stp x12, x11, [sp, #32]
+; CHECK-NEXT: stp x12, x10, [sp, #32]
; CHECK-NEXT: eor x22, x22, #0x3f
-; CHECK-NEXT: add x9, x10, x9
+; CHECK-NEXT: add x9, x11, x9
; CHECK-NEXT: mov x19, xzr
; CHECK-NEXT: mov x20, xzr
-; CHECK-NEXT: ldp x21, x10, [x9, #16]
+; CHECK-NEXT: ldp x21, x11, [x9, #16]
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: ldp x9, x24, [x9]
-; CHECK-NEXT: lsl x25, x10, #1
+; CHECK-NEXT: lsl x25, x11, #1
; CHECK-NEXT: lsl x26, x21, #1
; CHECK-NEXT: lsr x27, x21, x17
; CHECK-NEXT: lsl x28, x24, #1
@@ -803,7 +803,7 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: lsr x9, x9, x17
; CHECK-NEXT: lsl x30, x28, x22
; CHECK-NEXT: sbcs x22, x14, xzr
-; CHECK-NEXT: lsr x26, x10, x17
+; CHECK-NEXT: lsr x26, x11, x17
; CHECK-NEXT: sbcs x23, x15, xzr
; CHECK-NEXT: orr x25, x25, x27
; CHECK-NEXT: orr x28, x24, x29
@@ -825,20 +825,20 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: mov x20, xzr
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: sbc x25, x24, x26
-; CHECK-NEXT: asr x10, x25, #63
-; CHECK-NEXT: and x25, x10, x13
+; CHECK-NEXT: asr x11, x25, #63
+; CHECK-NEXT: and x25, x11, x13
; CHECK-NEXT: subs x27, x29, x25
-; CHECK-NEXT: and x25, x10, x14
+; CHECK-NEXT: and x25, x11, x14
; CHECK-NEXT: sbcs x28, x30, x25
-; CHECK-NEXT: and x25, x10, x15
+; CHECK-NEXT: and x25, x11, x15
; CHECK-NEXT: sbcs x25, x9, x25
-; CHECK-NEXT: and x9, x10, x16
+; CHECK-NEXT: and x9, x11, x16
; CHECK-NEXT: sbc x26, x26, x9
; CHECK-NEXT: subs x17, x17, #1
; CHECK-NEXT: extr x9, x2, x1, #63
; CHECK-NEXT: sbcs x18, x18, xzr
; CHECK-NEXT: orr x1, x6, x1, lsl #1
-; CHECK-NEXT: and x6, x10, #0x1
+; CHECK-NEXT: and x6, x11, #0x1
; CHECK-NEXT: sbcs x0, x0, xzr
; CHECK-NEXT: orr x2, x19, x9
; CHECK-NEXT: sbc x4, x4, xzr
@@ -854,29 +854,29 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: extr x3, x5, x3, #63
; CHECK-NEXT: orr x17, x6, x1, lsl #1
; CHECK-NEXT: .LBB3_6: // %udiv-end
-; CHECK-NEXT: umulh x10, x17, x15
+; CHECK-NEXT: umulh x11, x17, x15
; CHECK-NEXT: ldp x20, x19, [sp, #224] // 16-byte Folded Reload
; CHECK-NEXT: ldp x26, x25, [sp, #176] // 16-byte Folded Reload
; CHECK-NEXT: umulh x9, x7, x13
; CHECK-NEXT: ldp x28, x27, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #144] // 16-byte Folded Reload
-; CHECK-NEXT: madd x10, x17, x16, x10
+; CHECK-NEXT: madd x11, x17, x16, x11
; CHECK-NEXT: madd x9, x7, x14, x9
-; CHECK-NEXT: madd x10, x4, x15, x10
+; CHECK-NEXT: madd x11, x4, x15, x11
; CHECK-NEXT: mul x15, x17, x15
; CHECK-NEXT: mul x16, x7, x13
; CHECK-NEXT: madd x9, x3, x13, x9
; CHECK-NEXT: umulh x0, x13, x17
; CHECK-NEXT: adds x15, x16, x15
; CHECK-NEXT: mul x1, x14, x17
-; CHECK-NEXT: adc x9, x9, x10
+; CHECK-NEXT: adc x9, x9, x11
; CHECK-NEXT: umulh x18, x14, x17
; CHECK-NEXT: mul x3, x13, x4
-; CHECK-NEXT: adds x10, x1, x0
+; CHECK-NEXT: adds x11, x1, x0
; CHECK-NEXT: umulh x2, x13, x4
; CHECK-NEXT: cinc x16, x18, hs
; CHECK-NEXT: umulh x5, x14, x4
-; CHECK-NEXT: adds x10, x3, x10
+; CHECK-NEXT: adds x11, x3, x11
; CHECK-NEXT: mul x14, x14, x4
; CHECK-NEXT: mul x13, x13, x17
; CHECK-NEXT: cinc x17, x2, hs
@@ -887,17 +887,17 @@ define i256 @srem256(i256 %a, i256 %b) nounwind {
; CHECK-NEXT: adds x14, x14, x15
; CHECK-NEXT: adc x9, x16, x9
; CHECK-NEXT: subs x13, x22, x13
-; CHECK-NEXT: sbcs x10, x23, x10
+; CHECK-NEXT: sbcs x11, x23, x11
; CHECK-NEXT: eor x13, x13, x8
; CHECK-NEXT: sbcs x12, x12, x14
-; CHECK-NEXT: eor x10, x10, x8
-; CHECK-NEXT: sbc x9, x11, x9
+; CHECK-NEXT: ldp x22, x21, [sp, #208] // 16-byte Folded Reload
+; CHECK-NEXT: sbc x9, x10, x9
+; CHECK-NEXT: eor x10, x11, x8
; CHECK-NEXT: subs x0, x13, x8
; CHECK-NEXT: eor x11, x12, x8
; CHECK-NEXT: sbcs x1, x10, x8
-; CHECK-NEXT: ldp x22, x21, [sp, #208] // 16-byte Folded Reload
-; CHECK-NEXT: ldp x24, x23, [sp, #192] // 16-byte Folded Reload
; CHECK-NEXT: eor x9, x9, x8
+; CHECK-NEXT: ldp x24, x23, [sp, #192] // 16-byte Folded Reload
; CHECK-NEXT: sbcs x2, x11, x8
; CHECK-NEXT: sbc x3, x9, x8
; CHECK-NEXT: add sp, sp, #240
@@ -931,37 +931,37 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: eor x9, x2, x8
; CHECK-NEXT: sbcs x0, x10, x8
; CHECK-NEXT: eor x10, x3, x8
-; CHECK-NEXT: sbcs x1, x9, x8
-; CHECK-NEXT: clz x9, x18
-; CHECK-NEXT: clz x11, x0
+; CHECK-NEXT: clz x11, x18
+; CHECK-NEXT: sbcs x4, x9, x8
+; CHECK-NEXT: clz x9, x0
+; CHECK-NEXT: add x11, x11, #64
; CHECK-NEXT: sbcs x5, x10, x8
-; CHECK-NEXT: clz x10, x1
-; CHECK-NEXT: add x9, x9, #64
+; CHECK-NEXT: clz x10, x4
; CHECK-NEXT: add x10, x10, #64
; CHECK-NEXT: clz x12, x5
; CHECK-NEXT: orr x14, x0, x5
; CHECK-NEXT: csel x10, x12, x10, ne
; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: orr x12, x1, x5
-; CHECK-NEXT: csel x9, x11, x9, ne
-; CHECK-NEXT: cmp x12, #0
-; CHECK-NEXT: mov w11, #253 // =0xfd
+; CHECK-NEXT: csel x9, x9, x11, ne
+; CHECK-NEXT: orr x11, x4, x5
; CHECK-NEXT: add x9, x9, #128
+; CHECK-NEXT: mov w12, #253 // =0xfd
+; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: csel x9, x10, x9, ne
-; CHECK-NEXT: subs x9, x11, x9
+; CHECK-NEXT: subs x9, x12, x9
; CHECK-NEXT: ngcs x10, xzr
; CHECK-NEXT: ngcs x11, xzr
; CHECK-NEXT: ngc x12, xzr
; CHECK-NEXT: cmp x13, x9
-; CHECK-NEXT: orr x13, x18, x1
+; CHECK-NEXT: orr x13, x18, x4
; CHECK-NEXT: ngcs xzr, x10
; CHECK-NEXT: orr x13, x13, x14
; CHECK-NEXT: ngcs xzr, x11
; CHECK-NEXT: ngcs xzr, x12
; CHECK-NEXT: ccmp x13, #0, #4, hs
; CHECK-NEXT: csel x13, xzr, x5, eq
-; CHECK-NEXT: csel x15, xzr, x1, eq
-; CHECK-NEXT: csel x2, xzr, x0, eq
+; CHECK-NEXT: csel x15, xzr, x4, eq
+; CHECK-NEXT: csel x1, xzr, x0, eq
; CHECK-NEXT: csel x14, xzr, x18, eq
; CHECK-NEXT: b.eq .LBB5_6
; CHECK-NEXT: // %bb.1: // %_udiv-special-cases
@@ -982,35 +982,35 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT: adds x9, x9, #1
; CHECK-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
-; CHECK-NEXT: and x3, x13, #0x3f
+; CHECK-NEXT: and x2, x13, #0x3f
; CHECK-NEXT: adcs x10, x10, xzr
; CHECK-NEXT: and x14, x14, #0x18
; CHECK-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
-; CHECK-NEXT: mvn w4, w13
+; CHECK-NEXT: mvn w3, w13
; CHECK-NEXT: stp x18, x0, [sp, #96]
; CHECK-NEXT: sub x14, x15, x14
-; CHECK-NEXT: eor x3, x3, #0x3f
-; CHECK-NEXT: str x1, [sp, #112]
+; CHECK-NEXT: eor x2, x2, #0x3f
+; CHECK-NEXT: str x4, [sp, #112]
; CHECK-NEXT: adcs x11, x11, xzr
; CHECK-NEXT: stp q0, q0, [sp, #64]
-; CHECK-NEXT: ldp x16, x2, [x14, #8]
+; CHECK-NEXT: ldp x16, x1, [x14, #8]
; CHECK-NEXT: ldr x17, [x14, #24]
; CHECK-NEXT: ldr x14, [x14]
; CHECK-NEXT: lsl x17, x17, x13
; CHECK-NEXT: lsr x15, x16, #1
-; CHECK-NEXT: lsr x6, x2, #1
+; CHECK-NEXT: lsr x6, x1, #1
; CHECK-NEXT: lsr x7, x14, #1
-; CHECK-NEXT: lsl x2, x2, x13
+; CHECK-NEXT: lsl x1, x1, x13
; CHECK-NEXT: lsl x19, x16, x13
-; CHECK-NEXT: lsr x4, x15, x4
-; CHECK-NEXT: lsr x6, x6, x3
-; CHECK-NEXT: lsr x3, x7, x3
+; CHECK-NEXT: lsr x3, x15, x3
+; CHECK-NEXT: lsr x6, x6, x2
+; CHECK-NEXT: lsr x2, x7, x2
; CHECK-NEXT: adcs x15, x12, xzr
; CHECK-NEXT: lsl x12, x14, x13
; CHECK-NEXT: cset w7, hs
; CHECK-NEXT: orr x16, x17, x6
-; CHECK-NEXT: orr x14, x2, x4
-; CHECK-NEXT: orr x13, x19, x3
+; CHECK-NEXT: orr x14, x1, x3
+; CHECK-NEXT: orr x13, x19, x2
; CHECK-NEXT: mov x17, xzr
; CHECK-NEXT: tbnz w7, #0, .LBB5_5
; CHECK-NEXT: // %bb.3: // %udiv-preheader
@@ -1019,28 +1019,28 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: stp q0, q0, [sp, #32]
; CHECK-NEXT: mvn w7, w9
-; CHECK-NEXT: mov x3, xzr
+; CHECK-NEXT: mov x2, xzr
; CHECK-NEXT: and x18, x6, #0x18
-; CHECK-NEXT: stp x1, x5, [sp, #16]
+; CHECK-NEXT: stp x4, x5, [sp, #16]
; CHECK-NEXT: and x6, x9, #0x3f
; CHECK-NEXT: add x0, x0, x18
; CHECK-NEXT: mov w18, #7 // =0x7
; CHECK-NEXT: eor x6, x6, #0x3f
-; CHECK-NEXT: ldp x1, x5, [x0, #16]
-; CHECK-NEXT: mov x4, xzr
+; CHECK-NEXT: ldp x4, x5, [x0, #16]
+; CHECK-NEXT: mov x3, xzr
; CHECK-NEXT: ldp x21, x19, [x0]
-; CHECK-NEXT: mov x2, xzr
-; CHECK-NEXT: lsl x0, x1, #1
+; CHECK-NEXT: mov x1, xzr
+; CHECK-NEXT: lsl x0, x4, #1
; CHECK-NEXT: lsl x20, x5, #1
-; CHECK-NEXT: lsr x22, x1, x9
-; CHECK-NEXT: lsl x1, x19, #1
+; CHECK-NEXT: lsr x22, x4, x9
+; CHECK-NEXT: lsl x4, x19, #1
; CHECK-NEXT: lsr x24, x19, x9
; CHECK-NEXT: lsr x21, x21, x9
; CHECK-NEXT: lsl x23, x0, x7
; CHECK-NEXT: subs x0, x18, #1
; CHECK-NEXT: lsl x20, x20, x6
-; CHECK-NEXT: lsl x6, x1, x6
-; CHECK-NEXT: ngcs x1, xzr
+; CHECK-NEXT: lsl x6, x4, x6
+; CHECK-NEXT: ngcs x4, xzr
; CHECK-NEXT: lsr x19, x5, x9
; CHECK-NEXT: ngcs x5, xzr
; CHECK-NEXT: orr x7, x20, x22
@@ -1056,11 +1056,11 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: extr x16, x16, x14, #63
; CHECK-NEXT: extr x14, x14, x13, #63
; CHECK-NEXT: cmp x0, x22
-; CHECK-NEXT: sbcs xzr, x1, x23
-; CHECK-NEXT: orr x14, x4, x14
-; CHECK-NEXT: orr x16, x2, x16
+; CHECK-NEXT: sbcs xzr, x4, x23
+; CHECK-NEXT: orr x14, x3, x14
+; CHECK-NEXT: orr x16, x1, x16
; CHECK-NEXT: sbcs xzr, x5, x24
-; CHECK-NEXT: mov x2, xzr
+; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: sbc x7, x6, x19
; CHECK-NEXT: asr x25, x7, #63
; CHECK-NEXT: and x7, x25, x18
@@ -1070,21 +1070,21 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: sbcs x20, x23, xzr
; CHECK-NEXT: and x17, x25, #0x1
; CHECK-NEXT: sbcs x7, x24, xzr
-; CHECK-NEXT: orr x13, x3, x22
+; CHECK-NEXT: orr x13, x2, x22
; CHECK-NEXT: sbc x19, x19, xzr
; CHECK-NEXT: subs x9, x9, #1
; CHECK-NEXT: sbcs x10, x10, xzr
; CHECK-NEXT: sbcs x11, x11, xzr
; CHECK-NEXT: sbc x15, x15, xzr
-; CHECK-NEXT: orr x4, x9, x11
-; CHECK-NEXT: orr x3, x10, x15
-; CHECK-NEXT: orr x22, x4, x3
+; CHECK-NEXT: orr x3, x9, x11
+; CHECK-NEXT: orr x2, x10, x15
+; CHECK-NEXT: orr x22, x3, x2
+; CHECK-NEXT: mov x2, xzr
; CHECK-NEXT: mov x3, xzr
-; CHECK-NEXT: mov x4, xzr
; CHECK-NEXT: cbnz x22, .LBB5_4
; CHECK-NEXT: .LBB5_5: // %udiv-loop-exit
; CHECK-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
-; CHECK-NEXT: extr x2, x13, x12, #63
+; CHECK-NEXT: extr x1, x13, x12, #63
; CHECK-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT: extr x15, x14, x13, #63
; CHECK-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
@@ -1094,7 +1094,7 @@ define i256 @sdiv256_const(i256 %a) nounwind {
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: .LBB5_6: // %udiv-end
; CHECK-NEXT: eor x9, x14, x8
-; CHECK-NEXT: eor x10, x2, x8
+; CHECK-NEXT: eor x10, x1, x8
; CHECK-NEXT: subs x0, x9, x8
; CHECK-NEXT: eor x9, x15, x8
; CHECK-NEXT: sbcs x1, x10, x8
diff --git a/llvm/test/CodeGen/AArch64/fcvt-i256.ll b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
index d7d9d04187506..c28f8e14e6f54 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-i256.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-i256.ll
@@ -702,76 +702,76 @@ define i256 @f32_to_s256(float %val) {
; CHECK-GI-NEXT: mov w12, #128 // =0x80
; CHECK-GI-NEXT: sub x14, x11, #64
; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
+; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: cmp x11, #64
; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: csel x16, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x15, x14, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x15, x18, xzr, lo
+; CHECK-GI-NEXT: sub x18, x17, #64
; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
+; CHECK-GI-NEXT: lsl x0, x10, x17
; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
+; CHECK-GI-NEXT: lsl x18, x10, x18
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x15, eq
; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
+; CHECK-GI-NEXT: csel x15, x0, xzr, lo
+; CHECK-GI-NEXT: csel x10, x13, x18, lo
; CHECK-GI-NEXT: cmp x17, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
; CHECK-GI-NEXT: csel x10, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
+; CHECK-GI-NEXT: csel x12, x12, x15, lo
+; CHECK-GI-NEXT: umulh x15, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: csel x11, xzr, x12, eq
; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
-; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
+; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: umulh x12, x11, x8
+; CHECK-GI-NEXT: umulh x16, x10, x8
+; CHECK-GI-NEXT: add x18, x18, x15
+; CHECK-GI-NEXT: mul x17, x10, x9
+; CHECK-GI-NEXT: add x12, x12, x18
; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
; CHECK-GI-NEXT: umulh x2, x14, x8
-; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
+; CHECK-GI-NEXT: madd x12, x10, x9, x12
; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: madd x12, x14, x9, x12
+; CHECK-GI-NEXT: adds x14, x16, x17
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x16, x11, x8
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x15, x2, x15
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x15, x15, x17
+; CHECK-GI-NEXT: madd x9, x11, x9, x12
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x12, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x17, x0, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x12
+; CHECK-GI-NEXT: adds x12, x15, x18
+; CHECK-GI-NEXT: add x11, x17, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
+; CHECK-GI-NEXT: adds x12, x12, x16
; CHECK-GI-NEXT: madd x8, x13, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
+; CHECK-GI-NEXT: adds x2, x12, x10
+; CHECK-GI-NEXT: add x9, x11, x9
; CHECK-GI-NEXT: and x10, x13, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
@@ -875,29 +875,29 @@ define i256 @f32_to_u256(float %val) {
; CHECK-GI-NEXT: mov w10, #128 // =0x80
; CHECK-GI-NEXT: sub x12, x9, #64
; CHECK-GI-NEXT: sub x13, x11, x9
+; CHECK-GI-NEXT: sub x10, x10, x9
; CHECK-GI-NEXT: lsl x14, x8, x9
; CHECK-GI-NEXT: lsr x13, x8, x13
; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
; CHECK-GI-NEXT: csel x12, x13, x12, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x13, x16, xzr, lo
+; CHECK-GI-NEXT: sub x16, x15, #64
; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: lsl x17, x8, x15
; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
+; CHECK-GI-NEXT: lsl x16, x8, x16
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: csel x8, x8, x13, eq
; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: csel x11, x11, x16, lo
; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x11, xzr, x11, eq
; CHECK-GI-NEXT: cmp x9, #128
@@ -1063,76 +1063,76 @@ define i256 @f64_to_s256(double %val) {
; CHECK-GI-NEXT: mov w12, #128 // =0x80
; CHECK-GI-NEXT: sub x14, x11, #64
; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
+; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: cmp x11, #64
; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: csel x16, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x15, x14, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x15, x18, xzr, lo
+; CHECK-GI-NEXT: sub x18, x17, #64
; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
+; CHECK-GI-NEXT: lsl x0, x10, x17
; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
+; CHECK-GI-NEXT: lsl x18, x10, x18
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x15, eq
; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
+; CHECK-GI-NEXT: csel x15, x0, xzr, lo
+; CHECK-GI-NEXT: csel x10, x13, x18, lo
; CHECK-GI-NEXT: cmp x17, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
; CHECK-GI-NEXT: csel x10, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
+; CHECK-GI-NEXT: csel x12, x12, x15, lo
+; CHECK-GI-NEXT: umulh x15, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: csel x11, xzr, x12, eq
; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
-; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
+; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: umulh x12, x11, x8
+; CHECK-GI-NEXT: umulh x16, x10, x8
+; CHECK-GI-NEXT: add x18, x18, x15
+; CHECK-GI-NEXT: mul x17, x10, x9
+; CHECK-GI-NEXT: add x12, x12, x18
; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
; CHECK-GI-NEXT: umulh x2, x14, x8
-; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
+; CHECK-GI-NEXT: madd x12, x10, x9, x12
; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: madd x12, x14, x9, x12
+; CHECK-GI-NEXT: adds x14, x16, x17
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x16, x11, x8
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x15, x2, x15
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x15, x15, x17
+; CHECK-GI-NEXT: madd x9, x11, x9, x12
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x12, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x17, x0, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x12
+; CHECK-GI-NEXT: adds x12, x15, x18
+; CHECK-GI-NEXT: add x11, x17, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
+; CHECK-GI-NEXT: adds x12, x12, x16
; CHECK-GI-NEXT: madd x8, x13, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
+; CHECK-GI-NEXT: adds x2, x12, x10
+; CHECK-GI-NEXT: add x9, x11, x9
; CHECK-GI-NEXT: and x10, x13, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
@@ -1236,29 +1236,29 @@ define i256 @f64_to_u256(double %val) {
; CHECK-GI-NEXT: mov w10, #128 // =0x80
; CHECK-GI-NEXT: sub x12, x9, #64
; CHECK-GI-NEXT: sub x13, x11, x9
+; CHECK-GI-NEXT: sub x10, x10, x9
; CHECK-GI-NEXT: lsl x14, x8, x9
; CHECK-GI-NEXT: lsr x13, x8, x13
; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
; CHECK-GI-NEXT: csel x12, x13, x12, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x13, x16, xzr, lo
+; CHECK-GI-NEXT: sub x16, x15, #64
; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: lsl x17, x8, x15
; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
+; CHECK-GI-NEXT: lsl x16, x8, x16
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: csel x8, x8, x13, eq
; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: csel x11, x11, x16, lo
; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x11, xzr, x11, eq
; CHECK-GI-NEXT: cmp x9, #128
@@ -1452,76 +1452,76 @@ define i256 @f32_to_s256_sat(float %val) {
; CHECK-GI-NEXT: mov w12, #128 // =0x80
; CHECK-GI-NEXT: sub x14, x11, #64
; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
+; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: cmp x11, #64
; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: csel x16, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x15, x14, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x15, x18, xzr, lo
+; CHECK-GI-NEXT: sub x18, x17, #64
; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
+; CHECK-GI-NEXT: lsl x0, x10, x17
; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
+; CHECK-GI-NEXT: lsl x18, x10, x18
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x15, eq
; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
+; CHECK-GI-NEXT: csel x15, x0, xzr, lo
+; CHECK-GI-NEXT: csel x10, x13, x18, lo
; CHECK-GI-NEXT: cmp x17, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
; CHECK-GI-NEXT: csel x10, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
+; CHECK-GI-NEXT: csel x12, x12, x15, lo
+; CHECK-GI-NEXT: umulh x15, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: csel x11, xzr, x12, eq
; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
-; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
+; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: umulh x12, x11, x8
+; CHECK-GI-NEXT: umulh x16, x10, x8
+; CHECK-GI-NEXT: add x18, x18, x15
+; CHECK-GI-NEXT: mul x17, x10, x9
+; CHECK-GI-NEXT: add x12, x12, x18
; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
; CHECK-GI-NEXT: umulh x2, x14, x8
-; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
+; CHECK-GI-NEXT: madd x12, x10, x9, x12
; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: madd x12, x14, x9, x12
+; CHECK-GI-NEXT: adds x14, x16, x17
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x16, x11, x8
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x15, x2, x15
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x15, x15, x17
+; CHECK-GI-NEXT: madd x9, x11, x9, x12
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x12, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x17, x0, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x12
+; CHECK-GI-NEXT: adds x12, x15, x18
+; CHECK-GI-NEXT: add x11, x17, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
+; CHECK-GI-NEXT: adds x12, x12, x16
; CHECK-GI-NEXT: madd x8, x13, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
+; CHECK-GI-NEXT: adds x2, x12, x10
+; CHECK-GI-NEXT: add x9, x11, x9
; CHECK-GI-NEXT: and x10, x13, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
@@ -1661,29 +1661,29 @@ define i256 @f32_to_u256_sat(float %val) {
; CHECK-GI-NEXT: mov w10, #128 // =0x80
; CHECK-GI-NEXT: sub x12, x9, #64
; CHECK-GI-NEXT: sub x13, x11, x9
+; CHECK-GI-NEXT: sub x10, x10, x9
; CHECK-GI-NEXT: lsl x14, x8, x9
; CHECK-GI-NEXT: lsr x13, x8, x13
; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
; CHECK-GI-NEXT: csel x12, x13, x12, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x13, x16, xzr, lo
+; CHECK-GI-NEXT: sub x16, x15, #64
; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: lsl x17, x8, x15
; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
+; CHECK-GI-NEXT: lsl x16, x8, x16
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: csel x8, x8, x13, eq
; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: csel x11, x11, x16, lo
; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x11, xzr, x11, eq
; CHECK-GI-NEXT: cmp x9, #128
@@ -1879,76 +1879,76 @@ define i256 @f64_to_s256_sat(double %val) {
; CHECK-GI-NEXT: mov w12, #128 // =0x80
; CHECK-GI-NEXT: sub x14, x11, #64
; CHECK-GI-NEXT: sub x15, x13, x11
+; CHECK-GI-NEXT: sub x12, x12, x11
; CHECK-GI-NEXT: lsl x16, x10, x11
; CHECK-GI-NEXT: lsr x15, x10, x15
; CHECK-GI-NEXT: lsl x14, x10, x14
-; CHECK-GI-NEXT: sub x12, x12, x11
+; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: cmp x11, #64
; CHECK-GI-NEXT: sub x17, x11, #128
-; CHECK-GI-NEXT: lsr x18, x10, x12
; CHECK-GI-NEXT: csel x16, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x15, x14, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: sub x15, x17, #64
; CHECK-GI-NEXT: csel x14, xzr, x14, eq
; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x15, x18, xzr, lo
+; CHECK-GI-NEXT: sub x18, x17, #64
; CHECK-GI-NEXT: sub x13, x13, x17
-; CHECK-GI-NEXT: csel x18, x18, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #0
-; CHECK-GI-NEXT: lsl x12, x10, x17
+; CHECK-GI-NEXT: lsl x0, x10, x17
; CHECK-GI-NEXT: lsr x13, x10, x13
-; CHECK-GI-NEXT: lsl x15, x10, x15
-; CHECK-GI-NEXT: csel x18, x10, x18, eq
+; CHECK-GI-NEXT: lsl x18, x10, x18
+; CHECK-GI-NEXT: cmp x12, #0
+; CHECK-GI-NEXT: csel x12, x10, x15, eq
; CHECK-GI-NEXT: cmp x17, #64
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: csel x10, x13, x15, lo
+; CHECK-GI-NEXT: csel x15, x0, xzr, lo
+; CHECK-GI-NEXT: csel x10, x13, x18, lo
; CHECK-GI-NEXT: cmp x17, #0
; CHECK-GI-NEXT: csel x13, xzr, x10, eq
; CHECK-GI-NEXT: cmp x11, #128
; CHECK-GI-NEXT: csel x10, x16, xzr, lo
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
-; CHECK-GI-NEXT: csel x12, x18, x12, lo
+; CHECK-GI-NEXT: csel x12, x12, x15, lo
+; CHECK-GI-NEXT: umulh x15, x10, x9
; CHECK-GI-NEXT: csel x13, xzr, x13, lo
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: umulh x11, x10, x9
-; CHECK-GI-NEXT: csel x12, xzr, x12, eq
-; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: csel x11, xzr, x12, eq
; CHECK-GI-NEXT: umulh x18, x14, x9
-; CHECK-GI-NEXT: umulh x17, x12, x8
-; CHECK-GI-NEXT: umulh x15, x10, x8
-; CHECK-GI-NEXT: add x18, x18, x11
-; CHECK-GI-NEXT: mul x16, x10, x9
-; CHECK-GI-NEXT: add x17, x17, x18
+; CHECK-GI-NEXT: csel x13, xzr, x13, eq
+; CHECK-GI-NEXT: umulh x12, x11, x8
+; CHECK-GI-NEXT: umulh x16, x10, x8
+; CHECK-GI-NEXT: add x18, x18, x15
+; CHECK-GI-NEXT: mul x17, x10, x9
+; CHECK-GI-NEXT: add x12, x12, x18
; CHECK-GI-NEXT: mul x0, x14, x8
-; CHECK-GI-NEXT: madd x17, x10, x9, x17
-; CHECK-GI-NEXT: adds x15, x15, x16
; CHECK-GI-NEXT: umulh x2, x14, x8
-; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x1, x15, x0
+; CHECK-GI-NEXT: madd x12, x10, x9, x12
; CHECK-GI-NEXT: mul x18, x14, x9
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x14, x14, x9, x17
-; CHECK-GI-NEXT: adds x11, x2, x11
-; CHECK-GI-NEXT: mul x17, x12, x8
+; CHECK-GI-NEXT: madd x12, x14, x9, x12
+; CHECK-GI-NEXT: adds x14, x16, x17
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x1, x14, x0
+; CHECK-GI-NEXT: mul x16, x11, x8
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x15, x2, x15
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x11, x11, x16
-; CHECK-GI-NEXT: and x16, x0, #0x1
-; CHECK-GI-NEXT: madd x9, x12, x9, x14
-; CHECK-GI-NEXT: and x12, x3, #0x1
-; CHECK-GI-NEXT: and x14, x15, #0x1
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x11, x11, x18
-; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: adds x15, x15, x17
+; CHECK-GI-NEXT: madd x9, x11, x9, x12
+; CHECK-GI-NEXT: and x11, x3, #0x1
+; CHECK-GI-NEXT: and x12, x14, #0x1
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: and x17, x0, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: mul x0, x10, x8
-; CHECK-GI-NEXT: add x10, x12, x14
+; CHECK-GI-NEXT: add x10, x11, x12
+; CHECK-GI-NEXT: adds x12, x15, x18
+; CHECK-GI-NEXT: add x11, x17, x14
; CHECK-GI-NEXT: cset w14, hs
-; CHECK-GI-NEXT: adds x11, x11, x17
-; CHECK-GI-NEXT: add x12, x16, x15
+; CHECK-GI-NEXT: adds x12, x12, x16
; CHECK-GI-NEXT: madd x8, x13, x8, x9
; CHECK-GI-NEXT: and x9, x14, #0x1
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x2, x11, x10
-; CHECK-GI-NEXT: add x9, x12, x9
+; CHECK-GI-NEXT: adds x2, x12, x10
+; CHECK-GI-NEXT: add x9, x11, x9
; CHECK-GI-NEXT: and x10, x13, #0x1
; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: add x9, x9, x10
@@ -2088,29 +2088,29 @@ define i256 @f64_to_u256_sat(double %val) {
; CHECK-GI-NEXT: mov w10, #128 // =0x80
; CHECK-GI-NEXT: sub x12, x9, #64
; CHECK-GI-NEXT: sub x13, x11, x9
+; CHECK-GI-NEXT: sub x10, x10, x9
; CHECK-GI-NEXT: lsl x14, x8, x9
; CHECK-GI-NEXT: lsr x13, x8, x13
; CHECK-GI-NEXT: lsl x12, x8, x12
-; CHECK-GI-NEXT: sub x10, x10, x9
+; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: sub x15, x9, #128
-; CHECK-GI-NEXT: lsr x16, x8, x10
; CHECK-GI-NEXT: csel x14, x14, xzr, lo
; CHECK-GI-NEXT: csel x12, x13, x12, lo
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: sub x13, x15, #64
; CHECK-GI-NEXT: csel x12, xzr, x12, eq
; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x13, x16, xzr, lo
+; CHECK-GI-NEXT: sub x16, x15, #64
; CHECK-GI-NEXT: sub x11, x11, x15
-; CHECK-GI-NEXT: csel x16, x16, xzr, lo
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: lsl x10, x8, x15
+; CHECK-GI-NEXT: lsl x17, x8, x15
; CHECK-GI-NEXT: lsr x11, x8, x11
-; CHECK-GI-NEXT: lsl x13, x8, x13
-; CHECK-GI-NEXT: csel x8, x8, x16, eq
+; CHECK-GI-NEXT: lsl x16, x8, x16
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: csel x8, x8, x13, eq
; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: csel x10, x10, xzr, lo
-; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: csel x11, x11, x16, lo
; CHECK-GI-NEXT: cmp x15, #0
; CHECK-GI-NEXT: csel x11, xzr, x11, eq
; CHECK-GI-NEXT: cmp x9, #128
diff --git a/llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll b/llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll
index e2ea83d54633e..d8129c2bb7895 100644
--- a/llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll
+++ b/llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll
@@ -82,8 +82,8 @@ define i32 @cttzne(i32 %x) {
; CHECK-LABEL: cttzne:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rbit w8, w0
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: clz w8, w8
+; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w0, wzr, w8, ne
; CHECK-NEXT: ret
entry:
@@ -97,8 +97,8 @@ define i32 @cttzxnot0(i32 %x) {
; CHECK-LABEL: cttzxnot0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rbit w8, w0
-; CHECK-NEXT: cmp w0, #10
; CHECK-NEXT: clz w8, w8
+; CHECK-NEXT: cmp w0, #10
; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
entry:
@@ -113,8 +113,8 @@ define i32 @cttzlhsnot0(i32 %x) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rbit w9, w0
; CHECK-NEXT: mov w8, #10 // =0xa
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: clz w9, w9
+; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w0, w8, w9, eq
; CHECK-NEXT: ret
entry:
@@ -142,8 +142,8 @@ define i32 @cttzlhsnotx(i32 %x, i32 %y) {
; CHECK-LABEL: cttzlhsnotx:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rbit w8, w0
-; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: clz w8, w8
+; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: csel w0, wzr, w8, eq
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
index ab219e8e30641..2391b94fbc2d8 100644
--- a/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
@@ -95,10 +95,10 @@ entry:
define float @test_unsigned_min_max(float %x) {
; CHECK-LABEL: test_unsigned_min_max:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: mov w8, #512 // =0x200
-; CHECK-NEXT: cmp w9, #512
-; CHECK-NEXT: csel w8, w9, w8, hi
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: mov w9, #512 // =0x200
+; CHECK-NEXT: cmp w8, #512
+; CHECK-NEXT: csel w8, w8, w9, hi
; CHECK-NEXT: mov w9, #1023 // =0x3ff
; CHECK-NEXT: cmp w8, #1023
; CHECK-NEXT: csel w8, w8, w9, lo
@@ -136,11 +136,11 @@ define float @test_inexact_16777217(float %x) {
; CHECK-LABEL: test_inexact_16777217:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w10, #1 // =0x1
; CHECK-NEXT: mov w9, #16777216 // =0x1000000
+; CHECK-NEXT: movk w10, #256, lsl #16
; CHECK-NEXT: cmp w8, w9
-; CHECK-NEXT: mov w9, #1 // =0x1
-; CHECK-NEXT: movk w9, #256, lsl #16
-; CHECK-NEXT: csel w8, w8, w9, le
+; CHECK-NEXT: csel w8, w8, w10, le
; CHECK-NEXT: scvtf s0, w8
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat.ll b/llvm/test/CodeGen/AArch64/fpclamptosat.ll
index 24be9234515e8..a8b097922154f 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat.ll
@@ -900,10 +900,10 @@ define i64 @ustest_f64i64_mm(double %x) {
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: csel x0, xzr, x9, mi
+; CHECK-NEXT: csel x8, x0, xzr, lt
+; CHECK-NEXT: csinc x9, x1, xzr, lt
+; CHECK-NEXT: cmp x9, #0
+; CHECK-NEXT: csel x0, xzr, x8, mi
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
@@ -953,10 +953,10 @@ define i64 @ustest_f32i64_mm(float %x) {
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: csel x0, xzr, x9, mi
+; CHECK-NEXT: csel x8, x0, xzr, lt
+; CHECK-NEXT: csinc x9, x1, xzr, lt
+; CHECK-NEXT: cmp x9, #0
+; CHECK-NEXT: csel x0, xzr, x8, mi
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
@@ -1012,10 +1012,10 @@ define i64 @ustest_f16i64_mm(half %x) {
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: csel x0, xzr, x9, mi
+; CHECK-NEXT: csel x8, x0, xzr, lt
+; CHECK-NEXT: csinc x9, x1, xzr, lt
+; CHECK-NEXT: cmp x9, #0
+; CHECK-NEXT: csel x0, xzr, x8, mi
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index b406a8c43b12d..4231d1ab242b5 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -667,10 +667,10 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -696,10 +696,10 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -801,15 +801,15 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) {
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
; CHECK-CVT-SD-NEXT: bl __fixdfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: cmp xzr, x10
-; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
; CHECK-CVT-SD-NEXT: cmp xzr, x8
; CHECK-CVT-SD-NEXT: ngcs xzr, x9
@@ -838,15 +838,15 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) {
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
; CHECK-FP16-SD-NEXT: bl __fixdfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: cmp xzr, x10
-; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
; CHECK-FP16-SD-NEXT: cmp xzr, x8
; CHECK-FP16-SD-NEXT: ngcs xzr, x9
@@ -1130,10 +1130,10 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunssfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -1160,10 +1160,10 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunssfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -1268,20 +1268,20 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) {
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
; CHECK-CVT-SD-NEXT: bl __fixsfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: cmp xzr, x10
-; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp xzr, x9
-; CHECK-CVT-SD-NEXT: ngcs xzr, x8
+; CHECK-CVT-SD-NEXT: cmp xzr, x8
+; CHECK-CVT-SD-NEXT: ngcs xzr, x9
; CHECK-CVT-SD-NEXT: fmov d0, x10
-; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x8, x8, xzr, lt
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -1306,20 +1306,20 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) {
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
; CHECK-FP16-SD-NEXT: bl __fixsfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: cmp xzr, x10
-; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp xzr, x9
-; CHECK-FP16-SD-NEXT: ngcs xzr, x8
+; CHECK-FP16-SD-NEXT: cmp xzr, x8
+; CHECK-FP16-SD-NEXT: ngcs xzr, x9
; CHECK-FP16-SD-NEXT: fmov d0, x10
-; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x8, x8, xzr, lt
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -1578,10 +1578,10 @@ define <2 x i64> @utest_f16i64(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunshfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -1608,10 +1608,10 @@ define <2 x i64> @utest_f16i64(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunshfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -1668,20 +1668,20 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
; CHECK-CVT-SD-NEXT: bl __fixhfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: cmp xzr, x10
-; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
+; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp xzr, x9
-; CHECK-CVT-SD-NEXT: ngcs xzr, x8
+; CHECK-CVT-SD-NEXT: cmp xzr, x8
+; CHECK-CVT-SD-NEXT: ngcs xzr, x9
; CHECK-CVT-SD-NEXT: fmov d0, x10
-; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-CVT-SD-NEXT: csel x8, x8, xzr, lt
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -1706,20 +1706,20 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
; CHECK-FP16-SD-NEXT: bl __fixhfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: cmp xzr, x10
-; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
+; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp xzr, x9
-; CHECK-FP16-SD-NEXT: ngcs xzr, x8
+; CHECK-FP16-SD-NEXT: cmp xzr, x8
+; CHECK-FP16-SD-NEXT: ngcs xzr, x9
; CHECK-FP16-SD-NEXT: fmov d0, x10
-; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-FP16-SD-NEXT: csel x8, x8, xzr, lt
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -2445,10 +2445,10 @@ define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -2474,10 +2474,10 @@ define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -2578,15 +2578,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
; CHECK-CVT-SD-NEXT: bl __fixdfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x11, #0
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-CVT-SD-NEXT: cmp x9, #0
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-CVT-SD-NEXT: fmov d0, x10
@@ -2613,15 +2613,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
; CHECK-FP16-SD-NEXT: bl __fixdfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x11, #0
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-FP16-SD-NEXT: cmp x9, #0
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-FP16-SD-NEXT: fmov d0, x10
@@ -2899,10 +2899,10 @@ define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunssfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -2929,10 +2929,10 @@ define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunssfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -3036,15 +3036,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
; CHECK-CVT-SD-NEXT: bl __fixsfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x11, #0
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-CVT-SD-NEXT: cmp x9, #0
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-CVT-SD-NEXT: fmov d0, x10
@@ -3072,15 +3072,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
; CHECK-FP16-SD-NEXT: bl __fixsfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x11, #0
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-FP16-SD-NEXT: cmp x9, #0
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-FP16-SD-NEXT: fmov d0, x10
@@ -3338,10 +3338,10 @@ define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixunshfti
; CHECK-CVT-SD-NEXT: cmp x1, #0
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: cmp x20, #0
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -3368,10 +3368,10 @@ define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixunshfti
; CHECK-FP16-SD-NEXT: cmp x1, #0
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
-; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: cmp x20, #0
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
@@ -3427,15 +3427,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
; CHECK-CVT-SD-NEXT: bl __fixhfti
; CHECK-CVT-SD-NEXT: cmp x1, #1
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-CVT-SD-NEXT: cmp x11, #0
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-CVT-SD-NEXT: cmp x9, #0
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-CVT-SD-NEXT: fmov d0, x10
@@ -3463,15 +3463,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
; CHECK-FP16-SD-NEXT: bl __fixhfti
; CHECK-FP16-SD-NEXT: cmp x1, #1
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
+; CHECK-FP16-SD-NEXT: cmp x11, #0
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x10, mi
; CHECK-FP16-SD-NEXT: cmp x9, #0
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
; CHECK-FP16-SD-NEXT: fmov d0, x10
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index f95d338198c4d..3a22581fa446e 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -44,10 +44,10 @@ define i1 @test_signed_i1_f32(float %f) nounwind {
define i8 @test_signed_i8_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i8_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: mov w8, #127 // =0x7f
-; CHECK-NEXT: cmp w9, #127
-; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #127 // =0x7f
+; CHECK-NEXT: cmp w8, #127
+; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: csel w0, w8, w9, gt
@@ -59,10 +59,10 @@ define i8 @test_signed_i8_f32(float %f) nounwind {
define i13 @test_signed_i13_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i13_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: mov w8, #4095 // =0xfff
-; CHECK-NEXT: cmp w9, #4095
-; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #4095 // =0xfff
+; CHECK-NEXT: cmp w8, #4095
+; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-NEXT: csel w0, w8, w9, gt
@@ -289,10 +289,10 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
define i8 @test_signed_i8_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i8_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs w9, d0
-; CHECK-NEXT: mov w8, #127 // =0x7f
-; CHECK-NEXT: cmp w9, #127
-; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #127 // =0x7f
+; CHECK-NEXT: cmp w8, #127
+; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-NEXT: cmn w8, #128
; CHECK-NEXT: csel w0, w8, w9, gt
@@ -304,10 +304,10 @@ define i8 @test_signed_i8_f64(double %f) nounwind {
define i13 @test_signed_i13_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i13_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzs w9, d0
-; CHECK-NEXT: mov w8, #4095 // =0xfff
-; CHECK-NEXT: cmp w9, #4095
-; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #4095 // =0xfff
+; CHECK-NEXT: cmp w8, #4095
+; CHECK-NEXT: csel w8, w8, w9, lt
; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-NEXT: csel w0, w8, w9, gt
@@ -559,10 +559,10 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
; CHECK-SD-CVT-LABEL: test_signed_i8_f16:
; CHECK-SD-CVT: // %bb.0:
; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: mov w8, #127 // =0x7f
-; CHECK-SD-CVT-NEXT: fcvtzs w9, s0
-; CHECK-SD-CVT-NEXT: cmp w9, #127
-; CHECK-SD-CVT-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-CVT-NEXT: mov w9, #127 // =0x7f
+; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
+; CHECK-SD-CVT-NEXT: cmp w8, #127
+; CHECK-SD-CVT-NEXT: csel w8, w8, w9, lt
; CHECK-SD-CVT-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-SD-CVT-NEXT: cmn w8, #128
; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
@@ -570,10 +570,10 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
;
; CHECK-SD-FP16-LABEL: test_signed_i8_f16:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w9, h0
-; CHECK-SD-FP16-NEXT: mov w8, #127 // =0x7f
-; CHECK-SD-FP16-NEXT: cmp w9, #127
-; CHECK-SD-FP16-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
+; CHECK-SD-FP16-NEXT: mov w9, #127 // =0x7f
+; CHECK-SD-FP16-NEXT: cmp w8, #127
+; CHECK-SD-FP16-NEXT: csel w8, w8, w9, lt
; CHECK-SD-FP16-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-SD-FP16-NEXT: cmn w8, #128
; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
@@ -582,10 +582,10 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_signed_i8_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov w8, #127 // =0x7f
-; CHECK-GI-CVT-NEXT: fcvtzs w9, s0
-; CHECK-GI-CVT-NEXT: cmp w9, #127
-; CHECK-GI-CVT-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-CVT-NEXT: mov w9, #127 // =0x7f
+; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
+; CHECK-GI-CVT-NEXT: cmp w8, #127
+; CHECK-GI-CVT-NEXT: csel w8, w8, w9, lt
; CHECK-GI-CVT-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-GI-CVT-NEXT: cmn w8, #128
; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
@@ -593,10 +593,10 @@ define i8 @test_signed_i8_f16(half %f) nounwind {
;
; CHECK-GI-FP16-LABEL: test_signed_i8_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs w9, h0
-; CHECK-GI-FP16-NEXT: mov w8, #127 // =0x7f
-; CHECK-GI-FP16-NEXT: cmp w9, #127
-; CHECK-GI-FP16-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
+; CHECK-GI-FP16-NEXT: mov w9, #127 // =0x7f
+; CHECK-GI-FP16-NEXT: cmp w8, #127
+; CHECK-GI-FP16-NEXT: csel w8, w8, w9, lt
; CHECK-GI-FP16-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-GI-FP16-NEXT: cmn w8, #128
; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
@@ -609,10 +609,10 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
; CHECK-SD-CVT-LABEL: test_signed_i13_f16:
; CHECK-SD-CVT: // %bb.0:
; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: mov w8, #4095 // =0xfff
-; CHECK-SD-CVT-NEXT: fcvtzs w9, s0
-; CHECK-SD-CVT-NEXT: cmp w9, #4095
-; CHECK-SD-CVT-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-CVT-NEXT: mov w9, #4095 // =0xfff
+; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
+; CHECK-SD-CVT-NEXT: cmp w8, #4095
+; CHECK-SD-CVT-NEXT: csel w8, w8, w9, lt
; CHECK-SD-CVT-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-SD-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-SD-CVT-NEXT: csel w0, w8, w9, gt
@@ -620,10 +620,10 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
;
; CHECK-SD-FP16-LABEL: test_signed_i13_f16:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzs w9, h0
-; CHECK-SD-FP16-NEXT: mov w8, #4095 // =0xfff
-; CHECK-SD-FP16-NEXT: cmp w9, #4095
-; CHECK-SD-FP16-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
+; CHECK-SD-FP16-NEXT: mov w9, #4095 // =0xfff
+; CHECK-SD-FP16-NEXT: cmp w8, #4095
+; CHECK-SD-FP16-NEXT: csel w8, w8, w9, lt
; CHECK-SD-FP16-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-SD-FP16-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-SD-FP16-NEXT: csel w0, w8, w9, gt
@@ -632,10 +632,10 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
; CHECK-GI-CVT-LABEL: test_signed_i13_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov w8, #4095 // =0xfff
-; CHECK-GI-CVT-NEXT: fcvtzs w9, s0
-; CHECK-GI-CVT-NEXT: cmp w9, #4095
-; CHECK-GI-CVT-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-CVT-NEXT: mov w9, #4095 // =0xfff
+; CHECK-GI-CVT-NEXT: fcvtzs w8, s0
+; CHECK-GI-CVT-NEXT: cmp w8, #4095
+; CHECK-GI-CVT-NEXT: csel w8, w8, w9, lt
; CHECK-GI-CVT-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-GI-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-GI-CVT-NEXT: csel w0, w8, w9, gt
@@ -643,10 +643,10 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
;
; CHECK-GI-FP16-LABEL: test_signed_i13_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzs w9, h0
-; CHECK-GI-FP16-NEXT: mov w8, #4095 // =0xfff
-; CHECK-GI-FP16-NEXT: cmp w9, #4095
-; CHECK-GI-FP16-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-FP16-NEXT: fcvtzs w8, h0
+; CHECK-GI-FP16-NEXT: mov w9, #4095 // =0xfff
+; CHECK-GI-FP16-NEXT: cmp w8, #4095
+; CHECK-GI-FP16-NEXT: csel w8, w8, w9, lt
; CHECK-GI-FP16-NEXT: mov w9, #-4096 // =0xfffff000
; CHECK-GI-FP16-NEXT: cmn w8, #1, lsl #12 // =4096
; CHECK-GI-FP16-NEXT: csel w0, w8, w9, gt
@@ -947,8 +947,8 @@ define i32 @test_signed_f128_i32(fp128 %f) {
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
; CHECK-SD-NEXT: bl __fixtfsi
-; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: csel w19, w8, w0, mi
; CHECK-SD-NEXT: adrp x8, .LCPI30_1
@@ -1004,8 +1004,8 @@ define i32 @test_signed_f128_i32(fp128 %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: csel w0, wzr, w19, ne
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: add sp, sp, #48
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 145aef9123a4e..b9eb9f365e4fb 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -495,8 +495,8 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: mov w19, w0
; CHECK-SD-NEXT: bl __fixtfsi
-; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: mov w8, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: csel w19, w8, w0, mi
; CHECK-SD-NEXT: adrp x8, .LCPI14_1
@@ -553,8 +553,8 @@ define <1 x i32> @test_signed_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-GI-NEXT: mov v1.16b, v0.16b
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
+; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: fmov s0, w8
; CHECK-GI-NEXT: add sp, sp, #48
@@ -588,9 +588,9 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-NEXT: bl __fixtfsi
; CHECK-SD-NEXT: adrp x8, .LCPI15_1
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-SD-NEXT: mov w20, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
+; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: csel w19, w20, w0, mi
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
@@ -619,10 +619,10 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-SD-NEXT: fmov s0, w8
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
; CHECK-SD-NEXT: mov v0.s[1], w22
; CHECK-SD-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -700,9 +700,9 @@ define <2 x i32> @test_signed_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
; CHECK-GI-NEXT: ldp x20, x19, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #64] // 8-byte Reload
; CHECK-GI-NEXT: ldp x22, x21, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w8
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -738,9 +738,9 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: bl __fixtfsi
; CHECK-SD-NEXT: adrp x8, .LCPI16_1
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
-; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-SD-NEXT: mov w20, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
+; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: csel w19, w20, w0, mi
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
@@ -788,8 +788,8 @@ define <3 x i32> @test_signed_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-SD-NEXT: fmov s0, w8
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-SD-NEXT: mov v0.s[1], w23
; CHECK-SD-NEXT: ldp x30, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-SD-NEXT: mov v0.s[2], w21
@@ -932,9 +932,9 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-SD-NEXT: bl __fixtfsi
; CHECK-SD-NEXT: adrp x8, .LCPI17_1
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-SD-NEXT: mov w20, #-2147483648 // =0x80000000
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
+; CHECK-SD-NEXT: cmp w19, #0
; CHECK-SD-NEXT: csel w19, w20, w0, mi
; CHECK-SD-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
@@ -962,8 +962,8 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
+; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: fmov s0, w8
; CHECK-SD-NEXT: mov v0.s[1], w22
; CHECK-SD-NEXT: str q0, [sp, #48] // 16-byte Spill
@@ -1003,10 +1003,10 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-SD-NEXT: mov v1.16b, v0.16b
; CHECK-SD-NEXT: bl __unordtf2
; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
-; CHECK-SD-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-SD-NEXT: csel w8, wzr, w19, ne
+; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
; CHECK-SD-NEXT: ldp x20, x19, [sp, #128] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-SD-NEXT: ldp x22, x21, [sp, #112] // 16-byte Folded Reload
; CHECK-SD-NEXT: mov v0.s[3], w8
; CHECK-SD-NEXT: add sp, sp, #144
@@ -1133,9 +1133,9 @@ define <4 x i32> @test_signed_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-GI-NEXT: bl __unordtf2
; CHECK-GI-NEXT: fmov s0, w21
; CHECK-GI-NEXT: cmp w0, #0
-; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: csel w8, wzr, w19, ne
; CHECK-GI-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldr x30, [sp, #96] // 8-byte Reload
; CHECK-GI-NEXT: ldp x22, x21, [sp, #128] // 16-byte Folded Reload
; CHECK-GI-NEXT: mov v0.s[1], w23
; CHECK-GI-NEXT: mov v0.s[2], w24
@@ -1485,20 +1485,20 @@ define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-NEXT: fcvtzs x10, s0
+; CHECK-SD-NEXT: fcvtzs x9, s0
+; CHECK-SD-NEXT: mov x10, #562949953421311 // =0x1ffffffffffff
; CHECK-SD-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-NEXT: fcvtzs x9, s1
-; CHECK-SD-NEXT: cmp x9, x8
-; CHECK-SD-NEXT: csel x9, x9, x8, lt
-; CHECK-SD-NEXT: cmp x9, x11
-; CHECK-SD-NEXT: csel x9, x9, x11, gt
-; CHECK-SD-NEXT: cmp x10, x8
-; CHECK-SD-NEXT: csel x8, x10, x8, lt
+; CHECK-SD-NEXT: fcvtzs x8, s1
+; CHECK-SD-NEXT: cmp x8, x10
+; CHECK-SD-NEXT: csel x8, x8, x10, lt
; CHECK-SD-NEXT: cmp x8, x11
; CHECK-SD-NEXT: csel x8, x8, x11, gt
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: mov v0.d[1], x9
+; CHECK-SD-NEXT: cmp x9, x10
+; CHECK-SD-NEXT: csel x9, x9, x10, lt
+; CHECK-SD-NEXT: cmp x9, x11
+; CHECK-SD-NEXT: csel x9, x9, x11, gt
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: mov v0.d[1], x8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f32_v2i50:
@@ -2379,20 +2379,20 @@ define <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: fcvtzs w10, d0
-; CHECK-SD-NEXT: mov w8, #127 // =0x7f
+; CHECK-SD-NEXT: fcvtzs w9, d0
+; CHECK-SD-NEXT: mov w10, #127 // =0x7f
; CHECK-SD-NEXT: mov w11, #-128 // =0xffffff80
-; CHECK-SD-NEXT: fcvtzs w9, d1
+; CHECK-SD-NEXT: fcvtzs w8, d1
+; CHECK-SD-NEXT: cmp w8, #127
+; CHECK-SD-NEXT: csel w8, w8, w10, lt
+; CHECK-SD-NEXT: cmn w8, #128
+; CHECK-SD-NEXT: csel w8, w8, w11, gt
; CHECK-SD-NEXT: cmp w9, #127
-; CHECK-SD-NEXT: csel w9, w9, w8, lt
+; CHECK-SD-NEXT: csel w9, w9, w10, lt
; CHECK-SD-NEXT: cmn w9, #128
; CHECK-SD-NEXT: csel w9, w9, w11, gt
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
-; CHECK-SD-NEXT: cmn w8, #128
-; CHECK-SD-NEXT: csel w8, w8, w11, gt
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
@@ -2417,20 +2417,20 @@ define <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i13:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: fcvtzs w10, d0
-; CHECK-SD-NEXT: mov w8, #4095 // =0xfff
+; CHECK-SD-NEXT: fcvtzs w9, d0
+; CHECK-SD-NEXT: mov w10, #4095 // =0xfff
; CHECK-SD-NEXT: mov w11, #-4096 // =0xfffff000
-; CHECK-SD-NEXT: fcvtzs w9, d1
+; CHECK-SD-NEXT: fcvtzs w8, d1
+; CHECK-SD-NEXT: cmp w8, #4095
+; CHECK-SD-NEXT: csel w8, w8, w10, lt
+; CHECK-SD-NEXT: cmn w8, #1, lsl #12 // =4096
+; CHECK-SD-NEXT: csel w8, w8, w11, gt
; CHECK-SD-NEXT: cmp w9, #4095
-; CHECK-SD-NEXT: csel w9, w9, w8, lt
+; CHECK-SD-NEXT: csel w9, w9, w10, lt
; CHECK-SD-NEXT: cmn w9, #1, lsl #12 // =4096
; CHECK-SD-NEXT: csel w9, w9, w11, gt
-; CHECK-SD-NEXT: cmp w10, #4095
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
-; CHECK-SD-NEXT: cmn w8, #1, lsl #12 // =4096
-; CHECK-SD-NEXT: csel w8, w8, w11, gt
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
@@ -2455,20 +2455,20 @@ define <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-SD-NEXT: fcvtzs w10, d0
+; CHECK-SD-NEXT: fcvtzs w9, d0
+; CHECK-SD-NEXT: mov w10, #32767 // =0x7fff
; CHECK-SD-NEXT: mov w11, #-32768 // =0xffff8000
-; CHECK-SD-NEXT: fcvtzs w9, d1
-; CHECK-SD-NEXT: cmp w9, w8
-; CHECK-SD-NEXT: csel w9, w9, w8, lt
-; CHECK-SD-NEXT: cmn w9, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w9, w9, w11, gt
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w8, d1
+; CHECK-SD-NEXT: cmp w8, w10
+; CHECK-SD-NEXT: csel w8, w8, w10, lt
; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-SD-NEXT: csel w8, w8, w11, gt
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w9, w9, w10, lt
+; CHECK-SD-NEXT: cmn w9, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w9, w9, w11, gt
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
@@ -2493,20 +2493,20 @@ define <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i19:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: mov w8, #262143 // =0x3ffff
-; CHECK-SD-NEXT: fcvtzs w10, d0
+; CHECK-SD-NEXT: fcvtzs w9, d0
+; CHECK-SD-NEXT: mov w10, #262143 // =0x3ffff
; CHECK-SD-NEXT: mov w11, #-262144 // =0xfffc0000
-; CHECK-SD-NEXT: fcvtzs w9, d1
-; CHECK-SD-NEXT: cmp w9, w8
-; CHECK-SD-NEXT: csel w9, w9, w8, lt
-; CHECK-SD-NEXT: cmn w9, #64, lsl #12 // =262144
-; CHECK-SD-NEXT: csel w9, w9, w11, gt
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w8, d1
+; CHECK-SD-NEXT: cmp w8, w10
+; CHECK-SD-NEXT: csel w8, w8, w10, lt
; CHECK-SD-NEXT: cmn w8, #64, lsl #12 // =262144
; CHECK-SD-NEXT: csel w8, w8, w11, gt
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w9, w9, w10, lt
+; CHECK-SD-NEXT: cmn w9, #64, lsl #12 // =262144
+; CHECK-SD-NEXT: csel w9, w9, w11, gt
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
@@ -2559,20 +2559,20 @@ define <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
; CHECK-SD-LABEL: test_signed_v2f64_v2i50:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-SD-NEXT: fcvtzs x10, d0
+; CHECK-SD-NEXT: fcvtzs x9, d0
+; CHECK-SD-NEXT: mov x10, #562949953421311 // =0x1ffffffffffff
; CHECK-SD-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
-; CHECK-SD-NEXT: fcvtzs x9, d1
-; CHECK-SD-NEXT: cmp x9, x8
-; CHECK-SD-NEXT: csel x9, x9, x8, lt
-; CHECK-SD-NEXT: cmp x9, x11
-; CHECK-SD-NEXT: csel x9, x9, x11, gt
-; CHECK-SD-NEXT: cmp x10, x8
-; CHECK-SD-NEXT: csel x8, x10, x8, lt
+; CHECK-SD-NEXT: fcvtzs x8, d1
+; CHECK-SD-NEXT: cmp x8, x10
+; CHECK-SD-NEXT: csel x8, x8, x10, lt
; CHECK-SD-NEXT: cmp x8, x11
; CHECK-SD-NEXT: csel x8, x8, x11, gt
-; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: mov v0.d[1], x9
+; CHECK-SD-NEXT: cmp x9, x10
+; CHECK-SD-NEXT: csel x9, x9, x10, lt
+; CHECK-SD-NEXT: cmp x9, x11
+; CHECK-SD-NEXT: csel x9, x9, x11, gt
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: mov v0.d[1], x8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_signed_v2f64_v2i50:
@@ -3058,8 +3058,8 @@ define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
; CHECK-FP16-NEXT: fcvtzs x9, h0
; CHECK-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
; CHECK-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
; CHECK-FP16-NEXT: mov h0, v0.h[3]
+; CHECK-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
; CHECK-FP16-NEXT: fcvtzs x10, h1
; CHECK-FP16-NEXT: cmp x9, x8
; CHECK-FP16-NEXT: csel x9, x9, x8, lt
@@ -3638,114 +3638,114 @@ define <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
; CHECK-CVT: // %bb.0:
; CHECK-CVT-NEXT: mov d1, v0.d[1]
; CHECK-CVT-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
+; CHECK-CVT-NEXT: mov x13, #-562949953421312 // =0xfffe000000000000
; CHECK-CVT-NEXT: mov h2, v1.h[1]
-; CHECK-CVT-NEXT: fcvt s3, h1
-; CHECK-CVT-NEXT: mov h4, v1.h[2]
-; CHECK-CVT-NEXT: mov h1, v1.h[3]
-; CHECK-CVT-NEXT: fcvt s2, h2
-; CHECK-CVT-NEXT: fcvtzs x10, s3
-; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: fcvtzs x11, s2
-; CHECK-CVT-NEXT: cmp x10, x8
-; CHECK-CVT-NEXT: fcvtzs x12, s3
-; CHECK-CVT-NEXT: csel x10, x10, x8, lt
-; CHECK-CVT-NEXT: mov h2, v0.h[1]
-; CHECK-CVT-NEXT: fcvt s3, h0
-; CHECK-CVT-NEXT: cmp x10, x9
-; CHECK-CVT-NEXT: csel x4, x10, x9, gt
-; CHECK-CVT-NEXT: cmp x11, x8
-; CHECK-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-CVT-NEXT: fcvtzs x11, s1
-; CHECK-CVT-NEXT: mov h1, v0.h[2]
-; CHECK-CVT-NEXT: cmp x10, x9
; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h4
+; CHECK-CVT-NEXT: fcvtzs x9, s1
+; CHECK-CVT-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-NEXT: fcvtzs x10, s2
+; CHECK-CVT-NEXT: fcvtzs x11, s3
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v0.h[2]
+; CHECK-CVT-NEXT: cmp x9, x8
+; CHECK-CVT-NEXT: csel x9, x9, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x4, x9, x13, gt
+; CHECK-CVT-NEXT: fcvtzs x12, s4
; CHECK-CVT-NEXT: mov h0, v0.h[3]
-; CHECK-CVT-NEXT: csel x5, x10, x9, gt
-; CHECK-CVT-NEXT: cmp x12, x8
-; CHECK-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-CVT-NEXT: fcvtzs x12, s3
-; CHECK-CVT-NEXT: cmp x10, x9
; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: csel x6, x10, x9, gt
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x9, x10, x8, lt
+; CHECK-CVT-NEXT: fcvtzs x10, s2
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x5, x9, x13, gt
+; CHECK-CVT-NEXT: fcvt s2, h3
; CHECK-CVT-NEXT: cmp x11, x8
+; CHECK-CVT-NEXT: csel x9, x11, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x6, x9, x13, gt
; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-CVT-NEXT: fcvtzs x11, s2
-; CHECK-CVT-NEXT: cmp x10, x9
-; CHECK-CVT-NEXT: csel x7, x10, x9, gt
+; CHECK-CVT-NEXT: fcvtzs x11, s1
; CHECK-CVT-NEXT: cmp x12, x8
-; CHECK-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-CVT-NEXT: fcvtzs x12, s1
-; CHECK-CVT-NEXT: cmp x10, x9
-; CHECK-CVT-NEXT: csel x0, x10, x9, gt
+; CHECK-CVT-NEXT: csel x9, x12, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x7, x9, x13, gt
+; CHECK-CVT-NEXT: fcvtzs x12, s2
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x9, x10, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x0, x9, x13, gt
+; CHECK-CVT-NEXT: fcvtzs x10, s0
; CHECK-CVT-NEXT: cmp x11, x8
-; CHECK-CVT-NEXT: csel x10, x11, x8, lt
-; CHECK-CVT-NEXT: fcvtzs x11, s0
-; CHECK-CVT-NEXT: cmp x10, x9
-; CHECK-CVT-NEXT: csel x1, x10, x9, gt
+; CHECK-CVT-NEXT: csel x9, x11, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x1, x9, x13, gt
; CHECK-CVT-NEXT: cmp x12, x8
-; CHECK-CVT-NEXT: csel x10, x12, x8, lt
-; CHECK-CVT-NEXT: cmp x10, x9
-; CHECK-CVT-NEXT: csel x2, x10, x9, gt
-; CHECK-CVT-NEXT: cmp x11, x8
-; CHECK-CVT-NEXT: csel x8, x11, x8, lt
-; CHECK-CVT-NEXT: cmp x8, x9
-; CHECK-CVT-NEXT: csel x3, x8, x9, gt
+; CHECK-CVT-NEXT: csel x9, x12, x8, lt
+; CHECK-CVT-NEXT: cmp x9, x13
+; CHECK-CVT-NEXT: csel x2, x9, x13, gt
+; CHECK-CVT-NEXT: cmp x10, x8
+; CHECK-CVT-NEXT: csel x8, x10, x8, lt
+; CHECK-CVT-NEXT: cmp x8, x13
+; CHECK-CVT-NEXT: csel x3, x8, x13, gt
; CHECK-CVT-NEXT: ret
;
; CHECK-FP16-LABEL: test_signed_v8f16_v8i50:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: mov d1, v0.d[1]
-; CHECK-FP16-NEXT: mov x8, #562949953421311 // =0x1ffffffffffff
-; CHECK-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
+; CHECK-FP16-NEXT: mov x10, #562949953421311 // =0x1ffffffffffff
+; CHECK-FP16-NEXT: mov x11, #-562949953421312 // =0xfffe000000000000
; CHECK-FP16-NEXT: mov h2, v1.h[1]
-; CHECK-FP16-NEXT: fcvtzs x10, h1
+; CHECK-FP16-NEXT: fcvtzs x8, h1
; CHECK-FP16-NEXT: mov h3, v1.h[2]
; CHECK-FP16-NEXT: mov h1, v1.h[3]
-; CHECK-FP16-NEXT: fcvtzs x11, h2
-; CHECK-FP16-NEXT: cmp x10, x8
+; CHECK-FP16-NEXT: fcvtzs x9, h2
+; CHECK-FP16-NEXT: cmp x8, x10
+; CHECK-FP16-NEXT: csel x8, x8, x10, lt
; CHECK-FP16-NEXT: fcvtzs x12, h3
-; CHECK-FP16-NEXT: csel x10, x10, x8, lt
-; CHECK-FP16-NEXT: mov h2, v0.h[2]
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x4, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x11, x8
-; CHECK-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-FP16-NEXT: fcvtzs x11, h1
-; CHECK-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x5, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x12, x8
-; CHECK-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-FP16-NEXT: fcvtzs x12, h0
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x4, x8, x11, gt
+; CHECK-FP16-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-NEXT: fcvtzs x13, h1
+; CHECK-FP16-NEXT: mov h1, v0.h[2]
+; CHECK-FP16-NEXT: cmp x9, x10
+; CHECK-FP16-NEXT: csel x8, x9, x10, lt
+; CHECK-FP16-NEXT: fcvtzs x9, h0
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x5, x8, x11, gt
; CHECK-FP16-NEXT: mov h0, v0.h[3]
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x6, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x11, x8
-; CHECK-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-FP16-NEXT: fcvtzs x11, h1
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x7, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x12, x8
-; CHECK-FP16-NEXT: csel x10, x12, x8, lt
+; CHECK-FP16-NEXT: cmp x12, x10
+; CHECK-FP16-NEXT: csel x8, x12, x10, lt
; CHECK-FP16-NEXT: fcvtzs x12, h2
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x0, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x11, x8
-; CHECK-FP16-NEXT: csel x10, x11, x8, lt
-; CHECK-FP16-NEXT: fcvtzs x11, h0
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x1, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x12, x8
-; CHECK-FP16-NEXT: csel x10, x12, x8, lt
-; CHECK-FP16-NEXT: cmp x10, x9
-; CHECK-FP16-NEXT: csel x2, x10, x9, gt
-; CHECK-FP16-NEXT: cmp x11, x8
-; CHECK-FP16-NEXT: csel x8, x11, x8, lt
-; CHECK-FP16-NEXT: cmp x8, x9
-; CHECK-FP16-NEXT: csel x3, x8, x9, gt
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x6, x8, x11, gt
+; CHECK-FP16-NEXT: cmp x13, x10
+; CHECK-FP16-NEXT: csel x8, x13, x10, lt
+; CHECK-FP16-NEXT: fcvtzs x13, h1
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x7, x8, x11, gt
+; CHECK-FP16-NEXT: cmp x9, x10
+; CHECK-FP16-NEXT: csel x8, x9, x10, lt
+; CHECK-FP16-NEXT: fcvtzs x9, h0
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x0, x8, x11, gt
+; CHECK-FP16-NEXT: cmp x12, x10
+; CHECK-FP16-NEXT: csel x8, x12, x10, lt
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x1, x8, x11, gt
+; CHECK-FP16-NEXT: cmp x13, x10
+; CHECK-FP16-NEXT: csel x8, x13, x10, lt
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x2, x8, x11, gt
+; CHECK-FP16-NEXT: cmp x9, x10
+; CHECK-FP16-NEXT: csel x8, x9, x10, lt
+; CHECK-FP16-NEXT: cmp x8, x11
+; CHECK-FP16-NEXT: csel x3, x8, x11, gt
; CHECK-FP16-NEXT: ret
%x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
ret <8 x i50> %x
@@ -4554,40 +4554,40 @@ define <8 x i8> @test_signed_v8f64_v8i8(<8 x double> %f) {
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: cmp w12, #127
; CHECK-SD-NEXT: fmov s0, w10
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: csel w10, w12, w8, lt
+; CHECK-SD-NEXT: cmn w10, #128
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[1], w11
-; CHECK-SD-NEXT: csel w11, w12, w8, lt
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
-; CHECK-SD-NEXT: mov v0.b[2], w11
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: mov v0.b[2], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
; CHECK-SD-NEXT: fcvtzs w11, d2
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, #127
; CHECK-SD-NEXT: mov v0.b[3], w10
; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: cmn w11, #128
; CHECK-SD-NEXT: csel w11, w11, w9, gt
; CHECK-SD-NEXT: mov v0.b[4], w11
; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: csel w10, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[5], w10
; CHECK-SD-NEXT: cmp w11, #127
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v0.b[6], w11
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: cmn w10, #128
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
+; CHECK-SD-NEXT: mov v0.b[6], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w8, w11, w8, lt
; CHECK-SD-NEXT: cmn w8, #128
; CHECK-SD-NEXT: csel w8, w8, w9, gt
; CHECK-SD-NEXT: mov v0.b[7], w8
@@ -4649,92 +4649,92 @@ define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: cmp w12, #127
; CHECK-SD-NEXT: fmov s0, w10
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: csel w10, w12, w8, lt
+; CHECK-SD-NEXT: cmn w10, #128
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[1], w11
-; CHECK-SD-NEXT: csel w11, w12, w8, lt
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
-; CHECK-SD-NEXT: mov v0.b[2], w11
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: mov v0.b[2], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
; CHECK-SD-NEXT: fcvtzs w11, d2
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, #127
; CHECK-SD-NEXT: mov v0.b[3], w10
; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: cmn w11, #128
; CHECK-SD-NEXT: csel w11, w11, w9, gt
; CHECK-SD-NEXT: mov v0.b[4], w11
-; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: cmp w10, #127
; CHECK-SD-NEXT: csel w10, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[5], w10
-; CHECK-SD-NEXT: fcvtzs w10, d1
; CHECK-SD-NEXT: cmp w11, #127
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: mov d1, v4.d[1]
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v0.b[6], w11
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
+; CHECK-SD-NEXT: mov v0.b[6], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
; CHECK-SD-NEXT: fcvtzs w11, d4
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, #127
; CHECK-SD-NEXT: mov v0.b[7], w10
; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: mov d1, v5.d[1]
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: cmn w11, #128
; CHECK-SD-NEXT: csel w11, w11, w9, gt
; CHECK-SD-NEXT: mov v0.b[8], w11
-; CHECK-SD-NEXT: fcvtzs w11, d5
; CHECK-SD-NEXT: cmp w10, #127
; CHECK-SD-NEXT: csel w10, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d5
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[9], w10
-; CHECK-SD-NEXT: fcvtzs w10, d1
; CHECK-SD-NEXT: cmp w11, #127
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: mov d1, v6.d[1]
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v0.b[10], w11
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
+; CHECK-SD-NEXT: mov v0.b[10], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
; CHECK-SD-NEXT: fcvtzs w11, d6
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, #127
; CHECK-SD-NEXT: mov v0.b[11], w10
; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: mov d1, v7.d[1]
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: cmn w11, #128
; CHECK-SD-NEXT: csel w11, w11, w9, gt
; CHECK-SD-NEXT: mov v0.b[12], w11
; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: fcvtzs w11, d7
; CHECK-SD-NEXT: csel w10, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d7
; CHECK-SD-NEXT: cmn w10, #128
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.b[13], w10
; CHECK-SD-NEXT: cmp w11, #127
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
-; CHECK-SD-NEXT: cmn w11, #128
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v0.b[14], w11
-; CHECK-SD-NEXT: cmp w10, #127
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: cmn w10, #128
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
+; CHECK-SD-NEXT: mov v0.b[14], w10
+; CHECK-SD-NEXT: cmp w11, #127
+; CHECK-SD-NEXT: csel w8, w11, w8, lt
; CHECK-SD-NEXT: cmn w8, #128
; CHECK-SD-NEXT: csel w8, w8, w9, gt
; CHECK-SD-NEXT: mov v0.b[15], w8
@@ -4802,8 +4802,8 @@ define <8 x i16> @test_signed_v8f64_v8i16(<8 x double> %f) {
; CHECK-SD-LABEL: test_signed_v8f64_v8i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d4, v0.d[1]
-; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
; CHECK-SD-NEXT: fcvtzs w10, d0
+; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
; CHECK-SD-NEXT: fcvtzs w12, d1
; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: fcvtzs w9, d4
@@ -4818,40 +4818,40 @@ define <8 x i16> @test_signed_v8f64_v8i16(<8 x double> %f) {
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: cmp w12, w8
; CHECK-SD-NEXT: fmov s0, w10
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: csel w10, w12, w8, lt
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.h[1], w11
-; CHECK-SD-NEXT: csel w11, w12, w8, lt
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
-; CHECK-SD-NEXT: mov v0.h[2], w11
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: mov d1, v2.d[1]
+; CHECK-SD-NEXT: mov v0.h[2], w10
+; CHECK-SD-NEXT: cmp w11, w8
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
; CHECK-SD-NEXT: fcvtzs w11, d2
; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, w8
; CHECK-SD-NEXT: mov v0.h[3], w10
; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w11, w8
+; CHECK-SD-NEXT: csel w11, w11, w8, lt
; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
; CHECK-SD-NEXT: csel w11, w11, w9, gt
; CHECK-SD-NEXT: mov v0.h[4], w11
; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: csel w10, w10, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d3
; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-SD-NEXT: csel w10, w10, w9, gt
; CHECK-SD-NEXT: mov v0.h[5], w10
; CHECK-SD-NEXT: cmp w11, w8
-; CHECK-SD-NEXT: fcvtzs w10, d1
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v0.h[6], w11
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
+; CHECK-SD-NEXT: csel w10, w11, w8, lt
+; CHECK-SD-NEXT: fcvtzs w11, d1
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w10, w10, w9, gt
+; CHECK-SD-NEXT: mov v0.h[6], w10
+; CHECK-SD-NEXT: cmp w11, w8
+; CHECK-SD-NEXT: csel w8, w11, w8, lt
; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-SD-NEXT: csel w8, w8, w9, gt
; CHECK-SD-NEXT: mov v0.h[7], w8
@@ -4895,110 +4895,110 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
; CHECK-SD-LABEL: test_signed_v16f64_v16i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d16, v0.d[1]
-; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
; CHECK-SD-NEXT: fcvtzs w11, d0
-; CHECK-SD-NEXT: mov d0, v1.d[1]
+; CHECK-SD-NEXT: mov w9, #32767 // =0x7fff
; CHECK-SD-NEXT: fcvtzs w12, d1
-; CHECK-SD-NEXT: fcvtzs w15, d3
-; CHECK-SD-NEXT: mov d1, v4.d[1]
-; CHECK-SD-NEXT: fcvtzs w1, d5
-; CHECK-SD-NEXT: fcvtzs w9, d16
-; CHECK-SD-NEXT: fcvtzs w14, d0
+; CHECK-SD-NEXT: mov w8, #-32768 // =0xffff8000
; CHECK-SD-NEXT: mov d0, v2.d[1]
-; CHECK-SD-NEXT: fcvtzs w0, d1
-; CHECK-SD-NEXT: cmp w9, w8
-; CHECK-SD-NEXT: csel w10, w9, w8, lt
-; CHECK-SD-NEXT: mov w9, #-32768 // =0xffff8000
+; CHECK-SD-NEXT: fcvtzs w18, d3
+; CHECK-SD-NEXT: fcvtzs w0, d4
+; CHECK-SD-NEXT: fcvtzs w1, d5
+; CHECK-SD-NEXT: fcvtzs w10, d16
+; CHECK-SD-NEXT: mov d16, v1.d[1]
+; CHECK-SD-NEXT: mov d1, v4.d[1]
+; CHECK-SD-NEXT: cmp w10, w9
+; CHECK-SD-NEXT: csel w10, w10, w9, lt
+; CHECK-SD-NEXT: fcvtzs w14, d16
; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: cmp w11, w8
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w13, w11, w9, gt
-; CHECK-SD-NEXT: cmp w12, w8
-; CHECK-SD-NEXT: csel w11, w12, w8, lt
-; CHECK-SD-NEXT: fcvtzs w12, d2
+; CHECK-SD-NEXT: csel w13, w10, w8, gt
+; CHECK-SD-NEXT: cmp w11, w9
+; CHECK-SD-NEXT: csel w10, w11, w9, lt
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: fcvtzs w11, d2
; CHECK-SD-NEXT: mov d2, v5.d[1]
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w17, w11, w9, gt
-; CHECK-SD-NEXT: cmp w14, w8
-; CHECK-SD-NEXT: csel w11, w14, w8, lt
-; CHECK-SD-NEXT: fcvtzs w14, d0
+; CHECK-SD-NEXT: csel w17, w10, w8, gt
+; CHECK-SD-NEXT: cmp w12, w9
+; CHECK-SD-NEXT: csel w10, w12, w9, lt
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: fcvtzs w12, d0
; CHECK-SD-NEXT: mov d0, v3.d[1]
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: cmp w12, w8
-; CHECK-SD-NEXT: csel w12, w12, w8, lt
-; CHECK-SD-NEXT: cmn w12, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: fcvtzs w18, d0
-; CHECK-SD-NEXT: fmov s0, w13
-; CHECK-SD-NEXT: csel w16, w12, w9, gt
-; CHECK-SD-NEXT: cmp w14, w8
-; CHECK-SD-NEXT: csel w12, w14, w8, lt
-; CHECK-SD-NEXT: cmn w12, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: mov v0.h[1], w10
-; CHECK-SD-NEXT: fcvtzs w10, d2
-; CHECK-SD-NEXT: csel w14, w12, w9, gt
-; CHECK-SD-NEXT: cmp w15, w8
+; CHECK-SD-NEXT: csel w15, w10, w8, gt
+; CHECK-SD-NEXT: cmp w14, w9
+; CHECK-SD-NEXT: csel w10, w14, w9, lt
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w14, w10, w8, gt
+; CHECK-SD-NEXT: cmp w11, w9
+; CHECK-SD-NEXT: csel w10, w11, w9, lt
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w16, w10, w8, gt
+; CHECK-SD-NEXT: cmp w12, w9
+; CHECK-SD-NEXT: csel w10, w12, w9, lt
+; CHECK-SD-NEXT: fcvtzs w12, d0
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: fmov s0, w17
+; CHECK-SD-NEXT: csel w11, w10, w8, gt
+; CHECK-SD-NEXT: cmp w18, w9
+; CHECK-SD-NEXT: csel w10, w18, w9, lt
+; CHECK-SD-NEXT: fcvtzs w18, d1
+; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: fcvtzs w17, d2
+; CHECK-SD-NEXT: csel w10, w10, w8, gt
+; CHECK-SD-NEXT: mov v0.h[1], w13
; CHECK-SD-NEXT: mov d2, v6.d[1]
-; CHECK-SD-NEXT: csel w12, w15, w8, lt
+; CHECK-SD-NEXT: cmp w12, w9
+; CHECK-SD-NEXT: csel w12, w12, w9, lt
; CHECK-SD-NEXT: cmn w12, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w12, w12, w9, gt
-; CHECK-SD-NEXT: cmp w18, w8
-; CHECK-SD-NEXT: mov v0.h[2], w17
-; CHECK-SD-NEXT: csel w15, w18, w8, lt
-; CHECK-SD-NEXT: fcvtzs w18, d4
-; CHECK-SD-NEXT: cmn w15, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w15, w15, w9, gt
-; CHECK-SD-NEXT: cmp w0, w8
-; CHECK-SD-NEXT: csel w0, w0, w8, lt
-; CHECK-SD-NEXT: mov v0.h[3], w11
-; CHECK-SD-NEXT: cmn w0, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w0, w0, w9, gt
-; CHECK-SD-NEXT: cmp w18, w8
-; CHECK-SD-NEXT: csel w18, w18, w8, lt
+; CHECK-SD-NEXT: csel w12, w12, w8, gt
+; CHECK-SD-NEXT: cmp w18, w9
+; CHECK-SD-NEXT: csel w18, w18, w9, lt
; CHECK-SD-NEXT: cmn w18, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: mov v0.h[4], w16
-; CHECK-SD-NEXT: csel w13, w18, w9, gt
-; CHECK-SD-NEXT: cmp w1, w8
-; CHECK-SD-NEXT: fmov s1, w13
-; CHECK-SD-NEXT: csel w13, w1, w8, lt
+; CHECK-SD-NEXT: mov v0.h[2], w15
+; CHECK-SD-NEXT: fcvtzs w15, d6
+; CHECK-SD-NEXT: csel w18, w18, w8, gt
+; CHECK-SD-NEXT: cmp w0, w9
+; CHECK-SD-NEXT: csel w0, w0, w9, lt
+; CHECK-SD-NEXT: cmn w0, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w0, w0, w8, gt
+; CHECK-SD-NEXT: cmp w1, w9
+; CHECK-SD-NEXT: csel w13, w1, w9, lt
+; CHECK-SD-NEXT: fmov s1, w0
; CHECK-SD-NEXT: cmn w13, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w13, w13, w9, gt
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: mov v0.h[5], w14
-; CHECK-SD-NEXT: mov v1.h[1], w0
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
-; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: mov v0.h[6], w12
+; CHECK-SD-NEXT: mov v0.h[3], w14
+; CHECK-SD-NEXT: csel w13, w13, w8, gt
+; CHECK-SD-NEXT: cmp w17, w9
+; CHECK-SD-NEXT: mov v1.h[1], w18
+; CHECK-SD-NEXT: mov v0.h[4], w16
; CHECK-SD-NEXT: mov v1.h[2], w13
-; CHECK-SD-NEXT: fcvtzs w13, d6
-; CHECK-SD-NEXT: mov v0.h[7], w15
-; CHECK-SD-NEXT: cmp w13, w8
-; CHECK-SD-NEXT: mov v1.h[3], w10
-; CHECK-SD-NEXT: fcvtzs w10, d2
-; CHECK-SD-NEXT: csel w11, w13, w8, lt
+; CHECK-SD-NEXT: csel w13, w17, w9, lt
+; CHECK-SD-NEXT: cmn w13, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: mov v0.h[5], w11
+; CHECK-SD-NEXT: csel w13, w13, w8, gt
+; CHECK-SD-NEXT: cmp w15, w9
+; CHECK-SD-NEXT: csel w14, w15, w9, lt
+; CHECK-SD-NEXT: cmn w14, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: mov v1.h[3], w13
+; CHECK-SD-NEXT: fcvtzs w13, d2
+; CHECK-SD-NEXT: csel w14, w14, w8, gt
; CHECK-SD-NEXT: mov d2, v7.d[1]
+; CHECK-SD-NEXT: mov v0.h[6], w10
+; CHECK-SD-NEXT: mov v1.h[4], w14
+; CHECK-SD-NEXT: cmp w13, w9
+; CHECK-SD-NEXT: csel w13, w13, w9, lt
+; CHECK-SD-NEXT: fcvtzs w14, d7
+; CHECK-SD-NEXT: cmn w13, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: mov v0.h[7], w12
+; CHECK-SD-NEXT: csel w13, w13, w8, gt
+; CHECK-SD-NEXT: mov v1.h[5], w13
+; CHECK-SD-NEXT: fcvtzs w13, d2
+; CHECK-SD-NEXT: cmp w14, w9
+; CHECK-SD-NEXT: csel w11, w14, w9, lt
; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
-; CHECK-SD-NEXT: mov v1.h[4], w11
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: fcvtzs w11, d7
-; CHECK-SD-NEXT: csel w10, w10, w8, lt
-; CHECK-SD-NEXT: cmn w10, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w10, w10, w9, gt
-; CHECK-SD-NEXT: mov v1.h[5], w10
-; CHECK-SD-NEXT: cmp w11, w8
-; CHECK-SD-NEXT: fcvtzs w10, d2
-; CHECK-SD-NEXT: csel w11, w11, w8, lt
-; CHECK-SD-NEXT: cmn w11, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w11, w11, w9, gt
+; CHECK-SD-NEXT: csel w11, w11, w8, gt
; CHECK-SD-NEXT: mov v1.h[6], w11
-; CHECK-SD-NEXT: cmp w10, w8
-; CHECK-SD-NEXT: csel w8, w10, w8, lt
-; CHECK-SD-NEXT: cmn w8, #8, lsl #12 // =32768
-; CHECK-SD-NEXT: csel w8, w8, w9, gt
+; CHECK-SD-NEXT: cmp w13, w9
+; CHECK-SD-NEXT: csel w9, w13, w9, lt
+; CHECK-SD-NEXT: cmn w9, #8, lsl #12 // =32768
+; CHECK-SD-NEXT: csel w8, w9, w8, gt
; CHECK-SD-NEXT: mov v1.h[7], w8
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
index 7a5fe0f4222bc..3f52906e0b107 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -41,10 +41,10 @@ define i1 @test_unsigned_i1_f32(float %f) nounwind {
define i8 @test_unsigned_i8_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i8_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: mov w8, #255 // =0xff
-; CHECK-NEXT: cmp w9, #255
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: mov w9, #255 // =0xff
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f32(float %f)
ret i8 %x
@@ -235,10 +235,10 @@ define i1 @test_unsigned_i1_f64(double %f) nounwind {
define i8 @test_unsigned_i8_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i8_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvtzu w9, d0
-; CHECK-NEXT: mov w8, #255 // =0xff
-; CHECK-NEXT: cmp w9, #255
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: mov w9, #255 // =0xff
+; CHECK-NEXT: cmp w8, #255
+; CHECK-NEXT: csel w0, w8, w9, lo
; CHECK-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f64(double %f)
ret i8 %x
@@ -447,35 +447,35 @@ define i8 @test_unsigned_i8_f16(half %f) nounwind {
; CHECK-SD-CVT-LABEL: test_unsigned_i8_f16:
; CHECK-SD-CVT: // %bb.0:
; CHECK-SD-CVT-NEXT: fcvt s0, h0
-; CHECK-SD-CVT-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-CVT-NEXT: fcvtzu w9, s0
-; CHECK-SD-CVT-NEXT: cmp w9, #255
-; CHECK-SD-CVT-NEXT: csel w0, w9, w8, lo
+; CHECK-SD-CVT-NEXT: mov w9, #255 // =0xff
+; CHECK-SD-CVT-NEXT: fcvtzu w8, s0
+; CHECK-SD-CVT-NEXT: cmp w8, #255
+; CHECK-SD-CVT-NEXT: csel w0, w8, w9, lo
; CHECK-SD-CVT-NEXT: ret
;
; CHECK-SD-FP16-LABEL: test_unsigned_i8_f16:
; CHECK-SD-FP16: // %bb.0:
-; CHECK-SD-FP16-NEXT: fcvtzu w9, h0
-; CHECK-SD-FP16-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-FP16-NEXT: cmp w9, #255
-; CHECK-SD-FP16-NEXT: csel w0, w9, w8, lo
+; CHECK-SD-FP16-NEXT: fcvtzu w8, h0
+; CHECK-SD-FP16-NEXT: mov w9, #255 // =0xff
+; CHECK-SD-FP16-NEXT: cmp w8, #255
+; CHECK-SD-FP16-NEXT: csel w0, w8, w9, lo
; CHECK-SD-FP16-NEXT: ret
;
; CHECK-GI-CVT-LABEL: test_unsigned_i8_f16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvt s0, h0
-; CHECK-GI-CVT-NEXT: mov w8, #255 // =0xff
-; CHECK-GI-CVT-NEXT: fcvtzu w9, s0
-; CHECK-GI-CVT-NEXT: cmp w9, #255
-; CHECK-GI-CVT-NEXT: csel w0, w9, w8, lo
+; CHECK-GI-CVT-NEXT: mov w9, #255 // =0xff
+; CHECK-GI-CVT-NEXT: fcvtzu w8, s0
+; CHECK-GI-CVT-NEXT: cmp w8, #255
+; CHECK-GI-CVT-NEXT: csel w0, w8, w9, lo
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_i8_f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: fcvtzu w9, h0
-; CHECK-GI-FP16-NEXT: mov w8, #255 // =0xff
-; CHECK-GI-FP16-NEXT: cmp w9, #255
-; CHECK-GI-FP16-NEXT: csel w0, w9, w8, lo
+; CHECK-GI-FP16-NEXT: fcvtzu w8, h0
+; CHECK-GI-FP16-NEXT: mov w9, #255 // =0xff
+; CHECK-GI-FP16-NEXT: cmp w8, #255
+; CHECK-GI-FP16-NEXT: csel w0, w8, w9, lo
; CHECK-GI-FP16-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
ret i8 %x
@@ -772,8 +772,8 @@ define i32 @test_unsigned_f128_i32(fp128 %f) {
; CHECK-SD-NEXT: adrp x8, .LCPI30_1
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-SD-NEXT: csel w19, wzr, w0, mi
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: csinv w0, w19, wzr, le
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 083a84292029d..54d46b8f37d64 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -461,8 +461,8 @@ define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
; CHECK-SD-NEXT: adrp x8, .LCPI14_1
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-SD-NEXT: csel w19, wzr, w0, mi
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI14_1]
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: csinv w8, w19, wzr, le
@@ -534,8 +534,8 @@ define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
; CHECK-SD-NEXT: adrp x8, .LCPI15_1
; CHECK-SD-NEXT: ldr q0, [sp, #32] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-SD-NEXT: csel w19, wzr, w0, mi
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI15_1]
; CHECK-SD-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #48] // 16-byte Reload
@@ -651,8 +651,8 @@ define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
; CHECK-SD-NEXT: adrp x8, .LCPI16_1
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-SD-NEXT: csel w19, wzr, w0, mi
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI16_1]
; CHECK-SD-NEXT: str q1, [sp, #16] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload
@@ -802,8 +802,8 @@ define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
; CHECK-SD-NEXT: adrp x8, .LCPI17_1
; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-SD-NEXT: cmp w19, #0
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-SD-NEXT: csel w19, wzr, w0, mi
+; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI17_1]
; CHECK-SD-NEXT: str q1, [sp, #48] // 16-byte Spill
; CHECK-SD-NEXT: bl __gttf2
; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload
@@ -1947,15 +1947,15 @@ define <2 x i8> @test_unsigned_v2f64_v2i8(<2 x double> %f) {
; CHECK-SD-LABEL: test_unsigned_v2f64_v2i8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: fcvtzu w10, d0
-; CHECK-SD-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: fcvtzu w9, d0
+; CHECK-SD-NEXT: mov w10, #255 // =0xff
+; CHECK-SD-NEXT: fcvtzu w8, d1
+; CHECK-SD-NEXT: cmp w8, #255
+; CHECK-SD-NEXT: csel w8, w8, w10, lo
; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: csel w9, w9, w8, lo
-; CHECK-SD-NEXT: cmp w10, #255
-; CHECK-SD-NEXT: csel w8, w10, w8, lo
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: csel w9, w9, w10, lo
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
@@ -2961,14 +2961,14 @@ define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
; CHECK-CVT-NEXT: fcvtzu x12, s4
; CHECK-CVT-NEXT: fcvt s3, h7
; CHECK-CVT-NEXT: cmp x9, x8
-; CHECK-CVT-NEXT: fcvtzu x14, s1
; CHECK-CVT-NEXT: csel x4, x9, x8, lo
+; CHECK-CVT-NEXT: fcvtzu x14, s1
; CHECK-CVT-NEXT: cmp x10, x8
-; CHECK-CVT-NEXT: fcvtzu x9, s2
; CHECK-CVT-NEXT: csel x5, x10, x8, lo
+; CHECK-CVT-NEXT: fcvtzu x9, s2
; CHECK-CVT-NEXT: cmp x11, x8
-; CHECK-CVT-NEXT: fcvtzu x10, s3
; CHECK-CVT-NEXT: csel x6, x11, x8, lo
+; CHECK-CVT-NEXT: fcvtzu x10, s3
; CHECK-CVT-NEXT: cmp x12, x8
; CHECK-CVT-NEXT: csel x7, x12, x8, lo
; CHECK-CVT-NEXT: cmp x13, x8
@@ -2997,14 +2997,14 @@ define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
; CHECK-FP16-NEXT: fcvtzu x12, h4
; CHECK-FP16-NEXT: mov h3, v0.h[3]
; CHECK-FP16-NEXT: cmp x9, x8
-; CHECK-FP16-NEXT: fcvtzu x14, h1
; CHECK-FP16-NEXT: csel x4, x9, x8, lo
+; CHECK-FP16-NEXT: fcvtzu x14, h1
; CHECK-FP16-NEXT: cmp x10, x8
-; CHECK-FP16-NEXT: fcvtzu x9, h2
; CHECK-FP16-NEXT: csel x5, x10, x8, lo
+; CHECK-FP16-NEXT: fcvtzu x9, h2
; CHECK-FP16-NEXT: cmp x11, x8
-; CHECK-FP16-NEXT: fcvtzu x10, h3
; CHECK-FP16-NEXT: csel x6, x11, x8, lo
+; CHECK-FP16-NEXT: fcvtzu x10, h3
; CHECK-FP16-NEXT: cmp x12, x8
; CHECK-FP16-NEXT: csel x7, x12, x8, lo
; CHECK-FP16-NEXT: cmp x13, x8
@@ -3714,39 +3714,39 @@ define <8 x i8> @test_unsigned_v8f64_v8i8(<8 x double> %f) {
; CHECK-SD-NEXT: mov d4, v0.d[1]
; CHECK-SD-NEXT: fcvtzu w10, d0
; CHECK-SD-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-NEXT: fcvtzu w11, d1
-; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: fcvtzu w9, d4
; CHECK-SD-NEXT: cmp w9, #255
; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: csel w10, w10, w8, lo
-; CHECK-SD-NEXT: cmp w11, #255
; CHECK-SD-NEXT: fmov s0, w10
-; CHECK-SD-NEXT: csel w10, w11, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
+; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: mov v0.b[1], w9
-; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
; CHECK-SD-NEXT: mov d1, v2.d[1]
-; CHECK-SD-NEXT: mov v0.b[2], w10
-; CHECK-SD-NEXT: cmp w9, #255
+; CHECK-SD-NEXT: mov v0.b[2], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
; CHECK-SD-NEXT: fcvtzu w10, d2
-; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: mov v0.b[3], w9
-; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[4], w10
; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: fcvtzu w10, d3
; CHECK-SD-NEXT: csel w9, w9, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d3
; CHECK-SD-NEXT: mov v0.b[5], w9
; CHECK-SD-NEXT: cmp w10, #255
-; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
-; CHECK-SD-NEXT: mov v0.b[6], w10
-; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: csel w8, w9, w8, lo
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
+; CHECK-SD-NEXT: mov v0.b[6], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w8, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[7], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
@@ -3781,75 +3781,75 @@ define <16 x i8> @test_unsigned_v16f64_v16i8(<16 x double> %f) {
; CHECK-SD-NEXT: mov d16, v0.d[1]
; CHECK-SD-NEXT: fcvtzu w10, d0
; CHECK-SD-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-NEXT: fcvtzu w11, d1
-; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: fcvtzu w9, d16
; CHECK-SD-NEXT: cmp w9, #255
; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: csel w10, w10, w8, lo
-; CHECK-SD-NEXT: cmp w11, #255
; CHECK-SD-NEXT: fmov s0, w10
-; CHECK-SD-NEXT: csel w10, w11, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
+; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: mov v0.b[1], w9
-; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
; CHECK-SD-NEXT: mov d1, v2.d[1]
-; CHECK-SD-NEXT: mov v0.b[2], w10
-; CHECK-SD-NEXT: cmp w9, #255
+; CHECK-SD-NEXT: mov v0.b[2], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
; CHECK-SD-NEXT: fcvtzu w10, d2
-; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: mov v0.b[3], w9
-; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[4], w10
; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: fcvtzu w10, d3
; CHECK-SD-NEXT: csel w9, w9, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d3
; CHECK-SD-NEXT: mov v0.b[5], w9
; CHECK-SD-NEXT: cmp w10, #255
-; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
; CHECK-SD-NEXT: mov d1, v4.d[1]
-; CHECK-SD-NEXT: mov v0.b[6], w10
-; CHECK-SD-NEXT: cmp w9, #255
+; CHECK-SD-NEXT: mov v0.b[6], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
; CHECK-SD-NEXT: fcvtzu w10, d4
-; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: mov v0.b[7], w9
-; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov d1, v5.d[1]
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[8], w10
; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: fcvtzu w10, d5
; CHECK-SD-NEXT: csel w9, w9, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d5
; CHECK-SD-NEXT: mov v0.b[9], w9
; CHECK-SD-NEXT: cmp w10, #255
-; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
; CHECK-SD-NEXT: mov d1, v6.d[1]
-; CHECK-SD-NEXT: mov v0.b[10], w10
-; CHECK-SD-NEXT: cmp w9, #255
+; CHECK-SD-NEXT: mov v0.b[10], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
; CHECK-SD-NEXT: fcvtzu w10, d6
-; CHECK-SD-NEXT: csel w9, w9, w8, lo
; CHECK-SD-NEXT: mov v0.b[11], w9
-; CHECK-SD-NEXT: cmp w10, #255
; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov d1, v7.d[1]
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[12], w10
; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: fcvtzu w10, d7
; CHECK-SD-NEXT: csel w9, w9, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d7
; CHECK-SD-NEXT: mov v0.b[13], w9
; CHECK-SD-NEXT: cmp w10, #255
-; CHECK-SD-NEXT: fcvtzu w9, d1
-; CHECK-SD-NEXT: csel w10, w10, w8, lo
-; CHECK-SD-NEXT: mov v0.b[14], w10
-; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: csel w8, w9, w8, lo
+; CHECK-SD-NEXT: csel w9, w10, w8, lo
+; CHECK-SD-NEXT: fcvtzu w10, d1
+; CHECK-SD-NEXT: mov v0.b[14], w9
+; CHECK-SD-NEXT: cmp w10, #255
+; CHECK-SD-NEXT: csel w8, w10, w8, lo
; CHECK-SD-NEXT: mov v0.b[15], w8
; CHECK-SD-NEXT: ret
;
@@ -3898,39 +3898,39 @@ define <8 x i16> @test_unsigned_v8f64_v8i16(<8 x double> %f) {
; CHECK-SD-NEXT: mov d4, v0.d[1]
; CHECK-SD-NEXT: fcvtzu w9, d0
; CHECK-SD-NEXT: mov w10, #65535 // =0xffff
-; CHECK-SD-NEXT: fcvtzu w11, d1
-; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: fcvtzu w8, d4
; CHECK-SD-NEXT: cmp w8, w10
; CHECK-SD-NEXT: csel w8, w8, w10, lo
; CHECK-SD-NEXT: cmp w9, w10
; CHECK-SD-NEXT: csel w9, w9, w10, lo
-; CHECK-SD-NEXT: cmp w11, w10
; CHECK-SD-NEXT: fmov s0, w9
-; CHECK-SD-NEXT: csel w9, w11, w10, lo
+; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: mov d1, v1.d[1]
; CHECK-SD-NEXT: mov v0.h[1], w8
-; CHECK-SD-NEXT: fcvtzu w8, d1
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w8, w9, w10, lo
+; CHECK-SD-NEXT: fcvtzu w9, d1
; CHECK-SD-NEXT: mov d1, v2.d[1]
-; CHECK-SD-NEXT: mov v0.h[2], w9
-; CHECK-SD-NEXT: cmp w8, w10
+; CHECK-SD-NEXT: mov v0.h[2], w8
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w8, w9, w10, lo
; CHECK-SD-NEXT: fcvtzu w9, d2
-; CHECK-SD-NEXT: csel w8, w8, w10, lo
; CHECK-SD-NEXT: mov v0.h[3], w8
-; CHECK-SD-NEXT: cmp w9, w10
; CHECK-SD-NEXT: fcvtzu w8, d1
-; CHECK-SD-NEXT: csel w9, w9, w10, lo
; CHECK-SD-NEXT: mov d1, v3.d[1]
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w9, w9, w10, lo
; CHECK-SD-NEXT: mov v0.h[4], w9
; CHECK-SD-NEXT: cmp w8, w10
-; CHECK-SD-NEXT: fcvtzu w9, d3
; CHECK-SD-NEXT: csel w8, w8, w10, lo
+; CHECK-SD-NEXT: fcvtzu w9, d3
; CHECK-SD-NEXT: mov v0.h[5], w8
; CHECK-SD-NEXT: cmp w9, w10
-; CHECK-SD-NEXT: fcvtzu w8, d1
-; CHECK-SD-NEXT: csel w9, w9, w10, lo
-; CHECK-SD-NEXT: mov v0.h[6], w9
-; CHECK-SD-NEXT: cmp w8, w10
-; CHECK-SD-NEXT: csel w8, w8, w10, lo
+; CHECK-SD-NEXT: csel w8, w9, w10, lo
+; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: mov v0.h[6], w8
+; CHECK-SD-NEXT: cmp w9, w10
+; CHECK-SD-NEXT: csel w8, w9, w10, lo
; CHECK-SD-NEXT: mov v0.h[7], w8
; CHECK-SD-NEXT: ret
;
@@ -3977,57 +3977,57 @@ define <16 x i16> @test_unsigned_v16f64_v16i16(<16 x double> %f) {
; CHECK-SD-NEXT: mov d2, v5.d[1]
; CHECK-SD-NEXT: cmp w9, w8
; CHECK-SD-NEXT: csel w14, w9, w8, lo
-; CHECK-SD-NEXT: cmp w10, w8
; CHECK-SD-NEXT: fcvtzu w9, d0
+; CHECK-SD-NEXT: cmp w10, w8
; CHECK-SD-NEXT: csel w15, w10, w8, lo
-; CHECK-SD-NEXT: cmp w11, w8
; CHECK-SD-NEXT: fcvtzu w10, d3
+; CHECK-SD-NEXT: cmp w11, w8
; CHECK-SD-NEXT: csel w11, w11, w8, lo
-; CHECK-SD-NEXT: cmp w12, w8
; CHECK-SD-NEXT: fmov s0, w15
+; CHECK-SD-NEXT: cmp w12, w8
; CHECK-SD-NEXT: csel w12, w12, w8, lo
; CHECK-SD-NEXT: cmp w13, w8
; CHECK-SD-NEXT: csel w13, w13, w8, lo
; CHECK-SD-NEXT: cmp w9, w8
; CHECK-SD-NEXT: csel w0, w9, w8, lo
-; CHECK-SD-NEXT: cmp w10, w8
; CHECK-SD-NEXT: mov v0.h[1], w14
+; CHECK-SD-NEXT: cmp w10, w8
; CHECK-SD-NEXT: csel w10, w10, w8, lo
; CHECK-SD-NEXT: cmp w16, w8
-; CHECK-SD-NEXT: fcvtzu w14, d2
; CHECK-SD-NEXT: csel w9, w16, w8, lo
; CHECK-SD-NEXT: cmp w17, w8
-; CHECK-SD-NEXT: mov d2, v6.d[1]
-; CHECK-SD-NEXT: csel w16, w17, w8, lo
+; CHECK-SD-NEXT: csel w15, w17, w8, lo
; CHECK-SD-NEXT: cmp w18, w8
-; CHECK-SD-NEXT: csel w17, w18, w8, lo
-; CHECK-SD-NEXT: fcvtzu w18, d5
+; CHECK-SD-NEXT: csel w16, w18, w8, lo
; CHECK-SD-NEXT: mov v0.h[2], w11
-; CHECK-SD-NEXT: fmov s1, w17
-; CHECK-SD-NEXT: fcvtzu w11, d6
-; CHECK-SD-NEXT: mov v1.h[1], w16
-; CHECK-SD-NEXT: cmp w18, w8
+; CHECK-SD-NEXT: fmov s1, w16
+; CHECK-SD-NEXT: fcvtzu w16, d5
+; CHECK-SD-NEXT: mov v1.h[1], w15
+; CHECK-SD-NEXT: fcvtzu w15, d2
+; CHECK-SD-NEXT: mov d2, v6.d[1]
+; CHECK-SD-NEXT: cmp w16, w8
+; CHECK-SD-NEXT: csel w14, w16, w8, lo
; CHECK-SD-NEXT: mov v0.h[3], w12
-; CHECK-SD-NEXT: csel w15, w18, w8, lo
+; CHECK-SD-NEXT: mov v1.h[2], w14
+; CHECK-SD-NEXT: cmp w15, w8
+; CHECK-SD-NEXT: csel w11, w15, w8, lo
+; CHECK-SD-NEXT: fcvtzu w14, d6
+; CHECK-SD-NEXT: mov v0.h[4], w13
+; CHECK-SD-NEXT: mov v1.h[3], w11
+; CHECK-SD-NEXT: fcvtzu w11, d2
+; CHECK-SD-NEXT: mov d2, v7.d[1]
; CHECK-SD-NEXT: cmp w14, w8
-; CHECK-SD-NEXT: fcvtzu w12, d2
-; CHECK-SD-NEXT: csel w14, w14, w8, lo
+; CHECK-SD-NEXT: csel w12, w14, w8, lo
+; CHECK-SD-NEXT: mov v0.h[5], w0
+; CHECK-SD-NEXT: mov v1.h[4], w12
; CHECK-SD-NEXT: cmp w11, w8
-; CHECK-SD-NEXT: mov d2, v7.d[1]
; CHECK-SD-NEXT: csel w11, w11, w8, lo
-; CHECK-SD-NEXT: mov v1.h[2], w15
-; CHECK-SD-NEXT: mov v0.h[4], w13
-; CHECK-SD-NEXT: cmp w12, w8
-; CHECK-SD-NEXT: csel w12, w12, w8, lo
-; CHECK-SD-NEXT: mov v1.h[3], w14
-; CHECK-SD-NEXT: mov v0.h[5], w0
-; CHECK-SD-NEXT: mov v1.h[4], w11
-; CHECK-SD-NEXT: fcvtzu w11, d7
+; CHECK-SD-NEXT: fcvtzu w12, d7
; CHECK-SD-NEXT: mov v0.h[6], w10
-; CHECK-SD-NEXT: mov v1.h[5], w12
-; CHECK-SD-NEXT: cmp w11, w8
+; CHECK-SD-NEXT: mov v1.h[5], w11
+; CHECK-SD-NEXT: cmp w12, w8
+; CHECK-SD-NEXT: csel w11, w12, w8, lo
; CHECK-SD-NEXT: fcvtzu w12, d2
-; CHECK-SD-NEXT: csel w11, w11, w8, lo
; CHECK-SD-NEXT: mov v0.h[7], w9
; CHECK-SD-NEXT: mov v1.h[6], w11
; CHECK-SD-NEXT: cmp w12, w8
diff --git a/llvm/test/CodeGen/AArch64/fsh.ll b/llvm/test/CodeGen/AArch64/fsh.ll
index 312010904cf50..6ce4e246f757d 100644
--- a/llvm/test/CodeGen/AArch64/fsh.ll
+++ b/llvm/test/CodeGen/AArch64/fsh.ll
@@ -182,34 +182,34 @@ define i128 @rotl_i128(i128 %a, i128 %c) {
; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: and x9, x2, #0x7f
; CHECK-GI-NEXT: neg x10, x2
-; CHECK-GI-NEXT: sub x12, x8, x9
-; CHECK-GI-NEXT: sub x11, x9, #64
-; CHECK-GI-NEXT: lsl x14, x1, x9
-; CHECK-GI-NEXT: lsr x12, x0, x12
-; CHECK-GI-NEXT: lsl x13, x0, x9
+; CHECK-GI-NEXT: sub x11, x8, x9
+; CHECK-GI-NEXT: sub x12, x9, #64
+; CHECK-GI-NEXT: lsl x13, x1, x9
+; CHECK-GI-NEXT: lsr x11, x0, x11
+; CHECK-GI-NEXT: lsl x14, x0, x9
+; CHECK-GI-NEXT: and x15, x10, #0x7f
+; CHECK-GI-NEXT: lsl x12, x0, x12
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: and x9, x10, #0x7f
-; CHECK-GI-NEXT: lsl x11, x0, x11
-; CHECK-GI-NEXT: orr x12, x12, x14
-; CHECK-GI-NEXT: sub x8, x8, x9
-; CHECK-GI-NEXT: sub x14, x9, #64
-; CHECK-GI-NEXT: csel x11, x12, x11, lo
-; CHECK-GI-NEXT: lsr x12, x0, x9
+; CHECK-GI-NEXT: sub x8, x8, x15
+; CHECK-GI-NEXT: orr x9, x11, x13
+; CHECK-GI-NEXT: sub x11, x15, #64
+; CHECK-GI-NEXT: csel x13, x14, xzr, lo
+; CHECK-GI-NEXT: csel x9, x9, x12, lo
+; CHECK-GI-NEXT: lsr x12, x0, x15
; CHECK-GI-NEXT: lsl x8, x1, x8
-; CHECK-GI-NEXT: csel x13, x13, xzr, lo
; CHECK-GI-NEXT: tst x2, #0x7f
-; CHECK-GI-NEXT: lsr x14, x1, x14
-; CHECK-GI-NEXT: csel x11, x1, x11, eq
+; CHECK-GI-NEXT: lsr x11, x1, x11
+; CHECK-GI-NEXT: lsr x14, x1, x15
+; CHECK-GI-NEXT: csel x9, x1, x9, eq
; CHECK-GI-NEXT: orr x8, x12, x8
-; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: lsr x12, x1, x9
-; CHECK-GI-NEXT: csel x8, x8, x14, lo
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x8, x8, x11, lo
; CHECK-GI-NEXT: tst x10, #0x7f
; CHECK-GI-NEXT: csel x8, x0, x8, eq
-; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: csel x9, x12, xzr, lo
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x10, x14, xzr, lo
; CHECK-GI-NEXT: orr x0, x13, x8
-; CHECK-GI-NEXT: orr x1, x11, x9
+; CHECK-GI-NEXT: orr x1, x9, x10
; CHECK-GI-NEXT: ret
entry:
%d = call i128 @llvm.fshl(i128 %a, i128 %a, i128 %c)
@@ -239,33 +239,33 @@ define i128 @rotr_i128(i128 %a, i128 %c) {
; CHECK-GI-NEXT: and x9, x2, #0x7f
; CHECK-GI-NEXT: neg x13, x2
; CHECK-GI-NEXT: sub x10, x8, x9
-; CHECK-GI-NEXT: sub x11, x9, #64
; CHECK-GI-NEXT: lsr x12, x0, x9
+; CHECK-GI-NEXT: sub x11, x9, #64
; CHECK-GI-NEXT: lsl x10, x1, x10
; CHECK-GI-NEXT: lsr x11, x1, x11
-; CHECK-GI-NEXT: and x14, x13, #0x7f
-; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: sub x8, x8, x14
-; CHECK-GI-NEXT: lsl x15, x1, x14
+; CHECK-GI-NEXT: lsr x14, x1, x9
; CHECK-GI-NEXT: orr x10, x12, x10
-; CHECK-GI-NEXT: lsr x12, x1, x9
-; CHECK-GI-NEXT: lsr x8, x0, x8
+; CHECK-GI-NEXT: and x12, x13, #0x7f
+; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: csel x10, x10, x11, lo
-; CHECK-GI-NEXT: sub x11, x14, #64
+; CHECK-GI-NEXT: sub x8, x8, x12
+; CHECK-GI-NEXT: sub x11, x12, #64
; CHECK-GI-NEXT: tst x2, #0x7f
+; CHECK-GI-NEXT: lsl x15, x1, x12
+; CHECK-GI-NEXT: lsr x8, x0, x8
; CHECK-GI-NEXT: csel x10, x0, x10, eq
-; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: lsl x9, x0, x14
; CHECK-GI-NEXT: lsl x11, x0, x11
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
+; CHECK-GI-NEXT: lsl x16, x0, x12
+; CHECK-GI-NEXT: cmp x9, #64
+; CHECK-GI-NEXT: csel x9, x14, xzr, lo
; CHECK-GI-NEXT: orr x8, x8, x15
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: csel x9, x9, xzr, lo
+; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x12, x16, xzr, lo
; CHECK-GI-NEXT: csel x8, x8, x11, lo
; CHECK-GI-NEXT: tst x13, #0x7f
+; CHECK-GI-NEXT: orr x0, x10, x12
; CHECK-GI-NEXT: csel x8, x1, x8, eq
-; CHECK-GI-NEXT: orr x0, x10, x9
-; CHECK-GI-NEXT: orr x1, x12, x8
+; CHECK-GI-NEXT: orr x1, x9, x8
; CHECK-GI-NEXT: ret
entry:
%d = call i128 @llvm.fshr(i128 %a, i128 %a, i128 %c)
@@ -504,40 +504,40 @@ define i128 @fshl_i128(i128 %a, i128 %b, i128 %c) {
;
; CHECK-GI-LABEL: fshl_i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: and x9, x4, #0x7f
-; CHECK-GI-NEXT: mov w10, #127 // =0x7f
-; CHECK-GI-NEXT: sub x12, x8, x9
-; CHECK-GI-NEXT: lsl x13, x1, x9
-; CHECK-GI-NEXT: bic x10, x10, x4
-; CHECK-GI-NEXT: lsr x12, x0, x12
-; CHECK-GI-NEXT: sub x14, x9, #64
-; CHECK-GI-NEXT: lsl x15, x0, x9
-; CHECK-GI-NEXT: extr x16, x3, x2, #1
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: mov w8, #127 // =0x7f
+; CHECK-GI-NEXT: sub x11, x10, x9
+; CHECK-GI-NEXT: lsl x12, x0, x9
+; CHECK-GI-NEXT: lsl x14, x1, x9
+; CHECK-GI-NEXT: lsr x11, x0, x11
+; CHECK-GI-NEXT: sub x13, x9, #64
+; CHECK-GI-NEXT: bic x8, x8, x4
+; CHECK-GI-NEXT: lsl x13, x0, x13
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: sub x8, x8, x10
-; CHECK-GI-NEXT: orr x9, x12, x13
-; CHECK-GI-NEXT: lsr x12, x3, #1
-; CHECK-GI-NEXT: lsl x13, x0, x14
-; CHECK-GI-NEXT: csel x14, x15, xzr, lo
-; CHECK-GI-NEXT: sub x15, x10, #64
-; CHECK-GI-NEXT: lsr x17, x16, x10
-; CHECK-GI-NEXT: lsl x8, x12, x8
-; CHECK-GI-NEXT: csel x9, x9, x13, lo
+; CHECK-GI-NEXT: csel x9, x12, xzr, lo
+; CHECK-GI-NEXT: orr x11, x11, x14
+; CHECK-GI-NEXT: extr x12, x3, x2, #1
+; CHECK-GI-NEXT: lsr x14, x3, #1
+; CHECK-GI-NEXT: sub x10, x10, x8
+; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: sub x13, x8, #64
+; CHECK-GI-NEXT: lsr x15, x12, x8
+; CHECK-GI-NEXT: lsl x10, x14, x10
; CHECK-GI-NEXT: tst x4, #0x7f
-; CHECK-GI-NEXT: lsr x13, x12, x15
-; CHECK-GI-NEXT: mvn x11, x4
-; CHECK-GI-NEXT: csel x9, x1, x9, eq
-; CHECK-GI-NEXT: orr x8, x17, x8
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: lsr x12, x12, x10
-; CHECK-GI-NEXT: csel x8, x8, x13, lo
-; CHECK-GI-NEXT: tst x11, #0x7f
-; CHECK-GI-NEXT: csel x8, x16, x8, eq
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: csel x10, x12, xzr, lo
-; CHECK-GI-NEXT: orr x0, x14, x8
-; CHECK-GI-NEXT: orr x1, x9, x10
+; CHECK-GI-NEXT: lsr x13, x14, x13
+; CHECK-GI-NEXT: mvn x16, x4
+; CHECK-GI-NEXT: csel x11, x1, x11, eq
+; CHECK-GI-NEXT: lsr x14, x14, x8
+; CHECK-GI-NEXT: orr x10, x15, x10
+; CHECK-GI-NEXT: cmp x8, #64
+; CHECK-GI-NEXT: csel x10, x10, x13, lo
+; CHECK-GI-NEXT: tst x16, #0x7f
+; CHECK-GI-NEXT: csel x10, x12, x10, eq
+; CHECK-GI-NEXT: cmp x8, #64
+; CHECK-GI-NEXT: csel x8, x14, xzr, lo
+; CHECK-GI-NEXT: orr x0, x9, x10
+; CHECK-GI-NEXT: orr x1, x11, x8
; CHECK-GI-NEXT: ret
entry:
%d = call i128 @llvm.fshl(i128 %a, i128 %b, i128 %c)
@@ -569,35 +569,35 @@ define i128 @fshr_i128(i128 %a, i128 %b, i128 %c) {
; CHECK-GI-NEXT: extr x10, x1, x0, #63
; CHECK-GI-NEXT: bic x8, x8, x4
; CHECK-GI-NEXT: mov w11, #64 // =0x40
-; CHECK-GI-NEXT: and x14, x4, #0x7f
-; CHECK-GI-NEXT: sub x12, x11, x8
-; CHECK-GI-NEXT: lsl x13, x10, x8
-; CHECK-GI-NEXT: lsl x16, x9, x8
-; CHECK-GI-NEXT: lsr x12, x9, x12
-; CHECK-GI-NEXT: sub x17, x8, #64
+; CHECK-GI-NEXT: and x16, x4, #0x7f
+; CHECK-GI-NEXT: sub x13, x11, x8
+; CHECK-GI-NEXT: sub x12, x8, #64
+; CHECK-GI-NEXT: lsl x15, x10, x8
+; CHECK-GI-NEXT: lsr x13, x9, x13
+; CHECK-GI-NEXT: lsl x14, x9, x8
+; CHECK-GI-NEXT: lsl x9, x9, x12
+; CHECK-GI-NEXT: mvn x17, x4
; CHECK-GI-NEXT: cmp x8, #64
-; CHECK-GI-NEXT: lsl x8, x9, x17
-; CHECK-GI-NEXT: sub x11, x11, x14
-; CHECK-GI-NEXT: mvn x15, x4
-; CHECK-GI-NEXT: orr x12, x12, x13
-; CHECK-GI-NEXT: csel x9, x16, xzr, lo
-; CHECK-GI-NEXT: sub x13, x14, #64
-; CHECK-GI-NEXT: lsr x16, x2, x14
+; CHECK-GI-NEXT: sub x11, x11, x16
+; CHECK-GI-NEXT: orr x12, x13, x15
+; CHECK-GI-NEXT: csel x8, x14, xzr, lo
+; CHECK-GI-NEXT: lsr x13, x2, x16
+; CHECK-GI-NEXT: csel x9, x12, x9, lo
+; CHECK-GI-NEXT: tst x17, #0x7f
+; CHECK-GI-NEXT: sub x12, x16, #64
; CHECK-GI-NEXT: lsl x11, x3, x11
-; CHECK-GI-NEXT: csel x8, x12, x8, lo
-; CHECK-GI-NEXT: tst x15, #0x7f
-; CHECK-GI-NEXT: lsr x12, x3, x13
-; CHECK-GI-NEXT: csel x8, x10, x8, eq
-; CHECK-GI-NEXT: orr x10, x16, x11
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: lsr x11, x3, x14
-; CHECK-GI-NEXT: csel x10, x10, x12, lo
+; CHECK-GI-NEXT: csel x9, x10, x9, eq
+; CHECK-GI-NEXT: lsr x10, x3, x12
+; CHECK-GI-NEXT: lsr x12, x3, x16
+; CHECK-GI-NEXT: orr x11, x13, x11
+; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: csel x10, x11, x10, lo
; CHECK-GI-NEXT: tst x4, #0x7f
; CHECK-GI-NEXT: csel x10, x2, x10, eq
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: csel x11, x11, xzr, lo
-; CHECK-GI-NEXT: orr x0, x9, x10
-; CHECK-GI-NEXT: orr x1, x8, x11
+; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: csel x11, x12, xzr, lo
+; CHECK-GI-NEXT: orr x0, x8, x10
+; CHECK-GI-NEXT: orr x1, x9, x11
; CHECK-GI-NEXT: ret
entry:
%d = call i128 @llvm.fshr(i128 %a, i128 %b, i128 %c)
@@ -1760,67 +1760,67 @@ define <2 x i128> @rotl_v2i128(<2 x i128> %a, <2 x i128> %c) {
;
; CHECK-GI-LABEL: rotl_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and x8, x4, #0x7f
-; CHECK-GI-NEXT: mov w9, #64 // =0x40
-; CHECK-GI-NEXT: neg x13, x4
-; CHECK-GI-NEXT: sub x10, x9, x8
-; CHECK-GI-NEXT: lsl x12, x1, x8
-; CHECK-GI-NEXT: sub x11, x8, #64
-; CHECK-GI-NEXT: lsr x10, x0, x10
-; CHECK-GI-NEXT: lsl x14, x0, x8
-; CHECK-GI-NEXT: lsl x11, x0, x11
-; CHECK-GI-NEXT: cmp x8, #64
-; CHECK-GI-NEXT: neg x15, x6
-; CHECK-GI-NEXT: orr x8, x10, x12
-; CHECK-GI-NEXT: and x10, x6, #0x7f
-; CHECK-GI-NEXT: csel x12, x14, xzr, lo
-; CHECK-GI-NEXT: sub x14, x9, x10
-; CHECK-GI-NEXT: csel x8, x8, x11, lo
+; CHECK-GI-NEXT: and x9, x4, #0x7f
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: and x16, x6, #0x7f
+; CHECK-GI-NEXT: sub x8, x10, x9
+; CHECK-GI-NEXT: lsl x12, x1, x9
+; CHECK-GI-NEXT: sub x14, x9, #64
+; CHECK-GI-NEXT: lsr x13, x0, x8
+; CHECK-GI-NEXT: lsl x15, x0, x9
+; CHECK-GI-NEXT: lsl x14, x0, x14
+; CHECK-GI-NEXT: cmp x9, #64
+; CHECK-GI-NEXT: neg x11, x4
+; CHECK-GI-NEXT: lsl x17, x2, x16
+; CHECK-GI-NEXT: orr x12, x13, x12
+; CHECK-GI-NEXT: sub x13, x10, x16
+; CHECK-GI-NEXT: csel x9, x15, xzr, lo
+; CHECK-GI-NEXT: csel x12, x12, x14, lo
+; CHECK-GI-NEXT: lsr x13, x2, x13
+; CHECK-GI-NEXT: lsl x14, x3, x16
+; CHECK-GI-NEXT: sub x15, x16, #64
; CHECK-GI-NEXT: tst x4, #0x7f
-; CHECK-GI-NEXT: sub x11, x10, #64
-; CHECK-GI-NEXT: lsl x16, x2, x10
-; CHECK-GI-NEXT: lsr x14, x2, x14
-; CHECK-GI-NEXT: lsl x17, x3, x10
-; CHECK-GI-NEXT: csel x8, x1, x8, eq
-; CHECK-GI-NEXT: lsl x11, x2, x11
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: and x4, x15, #0x7f
-; CHECK-GI-NEXT: orr x10, x14, x17
-; CHECK-GI-NEXT: csel x14, x16, xzr, lo
-; CHECK-GI-NEXT: and x16, x13, #0x7f
-; CHECK-GI-NEXT: csel x10, x10, x11, lo
-; CHECK-GI-NEXT: sub x11, x9, x16
+; CHECK-GI-NEXT: neg x8, x6
+; CHECK-GI-NEXT: orr x13, x13, x14
+; CHECK-GI-NEXT: lsl x14, x2, x15
+; CHECK-GI-NEXT: csel x12, x1, x12, eq
+; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: csel x15, x17, xzr, lo
+; CHECK-GI-NEXT: and x16, x11, #0x7f
+; CHECK-GI-NEXT: csel x13, x13, x14, lo
+; CHECK-GI-NEXT: sub x14, x10, x16
; CHECK-GI-NEXT: sub x17, x16, #64
; CHECK-GI-NEXT: lsr x18, x0, x16
-; CHECK-GI-NEXT: lsl x11, x1, x11
+; CHECK-GI-NEXT: lsl x14, x1, x14
; CHECK-GI-NEXT: tst x6, #0x7f
+; CHECK-GI-NEXT: and x4, x8, #0x7f
; CHECK-GI-NEXT: lsr x17, x1, x17
-; CHECK-GI-NEXT: csel x10, x3, x10, eq
+; CHECK-GI-NEXT: csel x13, x3, x13, eq
+; CHECK-GI-NEXT: orr x14, x18, x14
; CHECK-GI-NEXT: cmp x16, #64
-; CHECK-GI-NEXT: orr x11, x18, x11
-; CHECK-GI-NEXT: sub x9, x9, x4
+; CHECK-GI-NEXT: sub x10, x10, x4
; CHECK-GI-NEXT: lsr x1, x1, x16
-; CHECK-GI-NEXT: csel x11, x11, x17, lo
-; CHECK-GI-NEXT: tst x13, #0x7f
-; CHECK-GI-NEXT: sub x13, x4, #64
+; CHECK-GI-NEXT: csel x14, x14, x17, lo
+; CHECK-GI-NEXT: tst x11, #0x7f
+; CHECK-GI-NEXT: sub x11, x4, #64
; CHECK-GI-NEXT: lsr x17, x2, x4
-; CHECK-GI-NEXT: lsl x9, x3, x9
-; CHECK-GI-NEXT: csel x11, x0, x11, eq
+; CHECK-GI-NEXT: lsl x10, x3, x10
+; CHECK-GI-NEXT: csel x14, x0, x14, eq
+; CHECK-GI-NEXT: lsr x11, x3, x11
; CHECK-GI-NEXT: cmp x16, #64
-; CHECK-GI-NEXT: lsr x13, x3, x13
-; CHECK-GI-NEXT: orr x0, x12, x11
; CHECK-GI-NEXT: csel x16, x1, xzr, lo
-; CHECK-GI-NEXT: orr x9, x17, x9
+; CHECK-GI-NEXT: orr x10, x17, x10
; CHECK-GI-NEXT: cmp x4, #64
+; CHECK-GI-NEXT: csel x10, x10, x11, lo
; CHECK-GI-NEXT: lsr x17, x3, x4
-; CHECK-GI-NEXT: csel x9, x9, x13, lo
-; CHECK-GI-NEXT: tst x15, #0x7f
-; CHECK-GI-NEXT: csel x9, x2, x9, eq
+; CHECK-GI-NEXT: tst x8, #0x7f
+; CHECK-GI-NEXT: csel x8, x2, x10, eq
; CHECK-GI-NEXT: cmp x4, #64
-; CHECK-GI-NEXT: orr x1, x8, x16
-; CHECK-GI-NEXT: csel x13, x17, xzr, lo
-; CHECK-GI-NEXT: orr x2, x14, x9
-; CHECK-GI-NEXT: orr x3, x10, x13
+; CHECK-GI-NEXT: orr x0, x9, x14
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: orr x1, x12, x16
+; CHECK-GI-NEXT: orr x2, x15, x8
+; CHECK-GI-NEXT: orr x3, x13, x10
; CHECK-GI-NEXT: ret
entry:
%d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c)
@@ -1858,67 +1858,67 @@ define <2 x i128> @rotr_v2i128(<2 x i128> %a, <2 x i128> %c) {
;
; CHECK-GI-LABEL: rotr_v2i128:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and x8, x4, #0x7f
-; CHECK-GI-NEXT: mov w9, #64 // =0x40
-; CHECK-GI-NEXT: and x14, x6, #0x7f
-; CHECK-GI-NEXT: sub x10, x9, x8
-; CHECK-GI-NEXT: sub x11, x8, #64
-; CHECK-GI-NEXT: lsr x12, x0, x8
-; CHECK-GI-NEXT: lsl x10, x1, x10
+; CHECK-GI-NEXT: and x9, x4, #0x7f
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: and x15, x6, #0x7f
+; CHECK-GI-NEXT: sub x8, x10, x9
+; CHECK-GI-NEXT: sub x11, x9, #64
+; CHECK-GI-NEXT: lsr x12, x0, x9
+; CHECK-GI-NEXT: lsl x13, x1, x8
; CHECK-GI-NEXT: lsr x11, x1, x11
-; CHECK-GI-NEXT: cmp x8, #64
-; CHECK-GI-NEXT: sub x15, x9, x14
-; CHECK-GI-NEXT: neg x13, x4
-; CHECK-GI-NEXT: lsr x17, x3, x14
-; CHECK-GI-NEXT: orr x10, x12, x10
-; CHECK-GI-NEXT: lsr x12, x1, x8
-; CHECK-GI-NEXT: lsl x15, x3, x15
-; CHECK-GI-NEXT: csel x10, x10, x11, lo
+; CHECK-GI-NEXT: sub x16, x10, x15
+; CHECK-GI-NEXT: lsr x17, x2, x15
+; CHECK-GI-NEXT: lsl x16, x3, x16
+; CHECK-GI-NEXT: neg x14, x4
+; CHECK-GI-NEXT: orr x12, x12, x13
+; CHECK-GI-NEXT: cmp x9, #64
+; CHECK-GI-NEXT: lsr x13, x1, x9
+; CHECK-GI-NEXT: csel x11, x12, x11, lo
+; CHECK-GI-NEXT: sub x12, x15, #64
; CHECK-GI-NEXT: tst x4, #0x7f
-; CHECK-GI-NEXT: sub x11, x14, #64
-; CHECK-GI-NEXT: csel x10, x0, x10, eq
-; CHECK-GI-NEXT: cmp x8, #64
-; CHECK-GI-NEXT: lsr x8, x2, x14
-; CHECK-GI-NEXT: lsr x11, x3, x11
-; CHECK-GI-NEXT: csel x12, x12, xzr, lo
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: orr x8, x8, x15
-; CHECK-GI-NEXT: neg x16, x6
-; CHECK-GI-NEXT: csel x8, x8, x11, lo
+; CHECK-GI-NEXT: lsr x12, x3, x12
+; CHECK-GI-NEXT: csel x11, x0, x11, eq
+; CHECK-GI-NEXT: cmp x9, #64
+; CHECK-GI-NEXT: csel x9, x13, xzr, lo
+; CHECK-GI-NEXT: orr x16, x17, x16
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x12, x16, x12, lo
+; CHECK-GI-NEXT: and x16, x14, #0x7f
+; CHECK-GI-NEXT: neg x8, x6
+; CHECK-GI-NEXT: sub x18, x10, x16
+; CHECK-GI-NEXT: lsr x13, x3, x15
; CHECK-GI-NEXT: tst x6, #0x7f
-; CHECK-GI-NEXT: and x11, x13, #0x7f
-; CHECK-GI-NEXT: csel x8, x2, x8, eq
-; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: sub x14, x9, x11
-; CHECK-GI-NEXT: sub x15, x11, #64
-; CHECK-GI-NEXT: lsr x14, x0, x14
-; CHECK-GI-NEXT: lsl x18, x1, x11
-; CHECK-GI-NEXT: lsl x4, x0, x11
-; CHECK-GI-NEXT: lsl x15, x0, x15
-; CHECK-GI-NEXT: and x0, x16, #0x7f
-; CHECK-GI-NEXT: csel x17, x17, xzr, lo
-; CHECK-GI-NEXT: orr x14, x14, x18
-; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: sub x9, x9, x0
-; CHECK-GI-NEXT: csel x14, x14, x15, lo
-; CHECK-GI-NEXT: sub x15, x0, #64
-; CHECK-GI-NEXT: lsr x9, x2, x9
+; CHECK-GI-NEXT: sub x17, x16, #64
+; CHECK-GI-NEXT: lsr x18, x0, x18
+; CHECK-GI-NEXT: lsl x4, x1, x16
+; CHECK-GI-NEXT: csel x12, x2, x12, eq
+; CHECK-GI-NEXT: cmp x15, #64
+; CHECK-GI-NEXT: csel x13, x13, xzr, lo
+; CHECK-GI-NEXT: lsl x15, x0, x16
+; CHECK-GI-NEXT: lsl x17, x0, x17
+; CHECK-GI-NEXT: and x0, x8, #0x7f
+; CHECK-GI-NEXT: orr x18, x18, x4
+; CHECK-GI-NEXT: cmp x16, #64
+; CHECK-GI-NEXT: sub x10, x10, x0
+; CHECK-GI-NEXT: csel x15, x15, xzr, lo
+; CHECK-GI-NEXT: csel x16, x18, x17, lo
+; CHECK-GI-NEXT: sub x17, x0, #64
+; CHECK-GI-NEXT: lsr x10, x2, x10
; CHECK-GI-NEXT: lsl x18, x3, x0
-; CHECK-GI-NEXT: csel x11, x4, xzr, lo
-; CHECK-GI-NEXT: tst x13, #0x7f
-; CHECK-GI-NEXT: lsl x13, x2, x0
-; CHECK-GI-NEXT: lsl x15, x2, x15
-; CHECK-GI-NEXT: csel x14, x1, x14, eq
-; CHECK-GI-NEXT: orr x9, x9, x18
+; CHECK-GI-NEXT: tst x14, #0x7f
+; CHECK-GI-NEXT: lsl x14, x2, x0
+; CHECK-GI-NEXT: lsl x17, x2, x17
+; CHECK-GI-NEXT: csel x16, x1, x16, eq
+; CHECK-GI-NEXT: orr x10, x10, x18
; CHECK-GI-NEXT: cmp x0, #64
-; CHECK-GI-NEXT: csel x13, x13, xzr, lo
-; CHECK-GI-NEXT: csel x9, x9, x15, lo
-; CHECK-GI-NEXT: tst x16, #0x7f
-; CHECK-GI-NEXT: csel x9, x3, x9, eq
-; CHECK-GI-NEXT: orr x0, x10, x11
-; CHECK-GI-NEXT: orr x1, x12, x14
-; CHECK-GI-NEXT: orr x2, x8, x13
-; CHECK-GI-NEXT: orr x3, x17, x9
+; CHECK-GI-NEXT: orr x0, x11, x15
+; CHECK-GI-NEXT: csel x14, x14, xzr, lo
+; CHECK-GI-NEXT: csel x10, x10, x17, lo
+; CHECK-GI-NEXT: tst x8, #0x7f
+; CHECK-GI-NEXT: csel x8, x3, x10, eq
+; CHECK-GI-NEXT: orr x1, x9, x16
+; CHECK-GI-NEXT: orr x2, x12, x14
+; CHECK-GI-NEXT: orr x3, x13, x8
; CHECK-GI-NEXT: ret
entry:
%d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c)
@@ -2876,61 +2876,61 @@ define <2 x i128> @fshl_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) {
; CHECK-GI-NEXT: sub x15, x8, #64
; CHECK-GI-NEXT: lsl x17, x1, x8
; CHECK-GI-NEXT: lsr x16, x0, x10
+; CHECK-GI-NEXT: lsl x19, x0, x8
; CHECK-GI-NEXT: lsl x15, x0, x15
; CHECK-GI-NEXT: cmp x8, #64
-; CHECK-GI-NEXT: lsl x19, x0, x8
; CHECK-GI-NEXT: lsl x0, x3, x14
; CHECK-GI-NEXT: mvn x10, x12
; CHECK-GI-NEXT: orr x16, x16, x17
+; CHECK-GI-NEXT: csel x8, x19, xzr, lo
; CHECK-GI-NEXT: sub x17, x14, #64
; CHECK-GI-NEXT: csel x15, x16, x15, lo
; CHECK-GI-NEXT: sub x16, x9, x14
-; CHECK-GI-NEXT: csel x8, x19, xzr, lo
-; CHECK-GI-NEXT: lsr x16, x2, x16
; CHECK-GI-NEXT: tst x11, #0x7f
+; CHECK-GI-NEXT: lsr x16, x2, x16
; CHECK-GI-NEXT: lsl x19, x2, x14
; CHECK-GI-NEXT: lsl x17, x2, x17
; CHECK-GI-NEXT: csel x15, x1, x15, eq
; CHECK-GI-NEXT: cmp x14, #64
-; CHECK-GI-NEXT: orr x16, x16, x0
; CHECK-GI-NEXT: bic x11, x13, x11
+; CHECK-GI-NEXT: orr x16, x16, x0
; CHECK-GI-NEXT: csel x14, x19, xzr, lo
+; CHECK-GI-NEXT: extr x0, x5, x4, #1
; CHECK-GI-NEXT: csel x16, x16, x17, lo
; CHECK-GI-NEXT: tst x12, #0x7f
; CHECK-GI-NEXT: lsr x17, x5, #1
-; CHECK-GI-NEXT: extr x0, x5, x4, #1
; CHECK-GI-NEXT: bic x12, x13, x12
; CHECK-GI-NEXT: csel x13, x3, x16, eq
; CHECK-GI-NEXT: sub x16, x9, x11
; CHECK-GI-NEXT: sub x1, x11, #64
-; CHECK-GI-NEXT: lsr x3, x7, #1
; CHECK-GI-NEXT: lsr x2, x0, x11
; CHECK-GI-NEXT: lsl x16, x17, x16
+; CHECK-GI-NEXT: lsr x3, x7, #1
; CHECK-GI-NEXT: extr x4, x7, x6, #1
; CHECK-GI-NEXT: lsr x1, x17, x1
+; CHECK-GI-NEXT: orr x16, x2, x16
; CHECK-GI-NEXT: cmp x11, #64
; CHECK-GI-NEXT: sub x9, x9, x12
-; CHECK-GI-NEXT: orr x16, x2, x16
; CHECK-GI-NEXT: lsr x17, x17, x11
-; CHECK-GI-NEXT: lsl x9, x3, x9
; CHECK-GI-NEXT: csel x16, x16, x1, lo
; CHECK-GI-NEXT: tst x18, #0x7f
; CHECK-GI-NEXT: sub x18, x12, #64
; CHECK-GI-NEXT: lsr x1, x4, x12
+; CHECK-GI-NEXT: lsl x9, x3, x9
; CHECK-GI-NEXT: csel x16, x0, x16, eq
+; CHECK-GI-NEXT: lsr x18, x3, x18
; CHECK-GI-NEXT: cmp x11, #64
-; CHECK-GI-NEXT: lsr x11, x3, x18
-; CHECK-GI-NEXT: csel x17, x17, xzr, lo
-; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x11, x17, xzr, lo
; CHECK-GI-NEXT: orr x9, x1, x9
-; CHECK-GI-NEXT: lsr x18, x3, x12
-; CHECK-GI-NEXT: orr x0, x8, x16
-; CHECK-GI-NEXT: csel x9, x9, x11, lo
+; CHECK-GI-NEXT: cmp x12, #64
+; CHECK-GI-NEXT: csel x9, x9, x18, lo
+; CHECK-GI-NEXT: lsr x17, x3, x12
; CHECK-GI-NEXT: tst x10, #0x7f
-; CHECK-GI-NEXT: orr x1, x15, x17
; CHECK-GI-NEXT: csel x9, x4, x9, eq
; CHECK-GI-NEXT: cmp x12, #64
-; CHECK-GI-NEXT: csel x10, x18, xzr, lo
+; CHECK-GI-NEXT: orr x0, x8, x16
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: orr x1, x15, x11
; CHECK-GI-NEXT: orr x2, x14, x9
; CHECK-GI-NEXT: orr x3, x13, x10
; CHECK-GI-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
@@ -2976,73 +2976,73 @@ define <2 x i128> @fshr_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) {
; CHECK-GI-LABEL: fshr_v2i128:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldr x9, [sp]
-; CHECK-GI-NEXT: mov w10, #127 // =0x7f
-; CHECK-GI-NEXT: mov w12, #64 // =0x40
-; CHECK-GI-NEXT: lsl x13, x0, #1
-; CHECK-GI-NEXT: extr x14, x1, x0, #63
+; CHECK-GI-NEXT: mov w11, #127 // =0x7f
+; CHECK-GI-NEXT: mov w13, #64 // =0x40
+; CHECK-GI-NEXT: lsl x14, x0, #1
+; CHECK-GI-NEXT: extr x15, x1, x0, #63
; CHECK-GI-NEXT: ldr x8, [sp, #16]
-; CHECK-GI-NEXT: bic x11, x10, x9
+; CHECK-GI-NEXT: bic x12, x11, x9
; CHECK-GI-NEXT: mvn x16, x9
-; CHECK-GI-NEXT: and x15, x9, #0x7f
-; CHECK-GI-NEXT: sub x17, x12, x11
-; CHECK-GI-NEXT: sub x18, x11, #64
-; CHECK-GI-NEXT: lsl x0, x14, x11
-; CHECK-GI-NEXT: lsr x17, x13, x17
-; CHECK-GI-NEXT: lsl x1, x13, x11
-; CHECK-GI-NEXT: lsl x13, x13, x18
-; CHECK-GI-NEXT: bic x10, x10, x8
+; CHECK-GI-NEXT: and x10, x9, #0x7f
+; CHECK-GI-NEXT: sub x17, x13, x12
+; CHECK-GI-NEXT: sub x18, x12, #64
+; CHECK-GI-NEXT: lsl x0, x15, x12
+; CHECK-GI-NEXT: lsr x17, x14, x17
+; CHECK-GI-NEXT: lsl x1, x14, x12
+; CHECK-GI-NEXT: lsl x14, x14, x18
+; CHECK-GI-NEXT: bic x11, x11, x8
; CHECK-GI-NEXT: lsl x18, x2, #1
-; CHECK-GI-NEXT: cmp x11, #64
+; CHECK-GI-NEXT: cmp x12, #64
; CHECK-GI-NEXT: orr x17, x17, x0
-; CHECK-GI-NEXT: extr x11, x3, x2, #63
+; CHECK-GI-NEXT: extr x12, x3, x2, #63
; CHECK-GI-NEXT: csel x0, x1, xzr, lo
-; CHECK-GI-NEXT: csel x13, x17, x13, lo
-; CHECK-GI-NEXT: sub x17, x12, x10
+; CHECK-GI-NEXT: csel x14, x17, x14, lo
+; CHECK-GI-NEXT: sub x17, x13, x11
; CHECK-GI-NEXT: tst x16, #0x7f
-; CHECK-GI-NEXT: sub x16, x10, #64
+; CHECK-GI-NEXT: sub x16, x11, #64
; CHECK-GI-NEXT: lsr x17, x18, x17
-; CHECK-GI-NEXT: lsl x2, x11, x10
-; CHECK-GI-NEXT: lsl x1, x18, x10
-; CHECK-GI-NEXT: csel x13, x14, x13, eq
-; CHECK-GI-NEXT: lsl x14, x18, x16
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: mvn x10, x8
+; CHECK-GI-NEXT: lsl x2, x12, x11
+; CHECK-GI-NEXT: lsl x1, x18, x11
+; CHECK-GI-NEXT: csel x14, x15, x14, eq
+; CHECK-GI-NEXT: lsl x15, x18, x16
; CHECK-GI-NEXT: orr x16, x17, x2
-; CHECK-GI-NEXT: csel x17, x1, xzr, lo
-; CHECK-GI-NEXT: csel x14, x16, x14, lo
-; CHECK-GI-NEXT: tst x10, #0x7f
-; CHECK-GI-NEXT: sub x10, x12, x15
-; CHECK-GI-NEXT: sub x16, x15, #64
-; CHECK-GI-NEXT: lsr x18, x4, x15
-; CHECK-GI-NEXT: lsl x10, x5, x10
-; CHECK-GI-NEXT: csel x11, x11, x14, eq
-; CHECK-GI-NEXT: lsr x14, x5, x16
+; CHECK-GI-NEXT: cmp x11, #64
+; CHECK-GI-NEXT: mvn x3, x8
+; CHECK-GI-NEXT: csel x11, x1, xzr, lo
+; CHECK-GI-NEXT: csel x15, x16, x15, lo
+; CHECK-GI-NEXT: sub x16, x13, x10
+; CHECK-GI-NEXT: tst x3, #0x7f
+; CHECK-GI-NEXT: sub x17, x10, #64
+; CHECK-GI-NEXT: lsr x18, x4, x10
+; CHECK-GI-NEXT: lsl x16, x5, x16
+; CHECK-GI-NEXT: csel x12, x12, x15, eq
+; CHECK-GI-NEXT: lsr x15, x5, x17
; CHECK-GI-NEXT: and x1, x8, #0x7f
-; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: lsr x16, x5, x15
-; CHECK-GI-NEXT: orr x10, x18, x10
-; CHECK-GI-NEXT: csel x10, x10, x14, lo
+; CHECK-GI-NEXT: lsr x17, x5, x10
+; CHECK-GI-NEXT: orr x16, x18, x16
+; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x15, x16, x15, lo
; CHECK-GI-NEXT: tst x9, #0x7f
-; CHECK-GI-NEXT: sub x9, x12, x1
-; CHECK-GI-NEXT: sub x12, x1, #64
-; CHECK-GI-NEXT: lsr x14, x6, x1
+; CHECK-GI-NEXT: sub x9, x13, x1
+; CHECK-GI-NEXT: sub x13, x1, #64
+; CHECK-GI-NEXT: lsr x16, x6, x1
; CHECK-GI-NEXT: lsl x9, x7, x9
-; CHECK-GI-NEXT: csel x10, x4, x10, eq
-; CHECK-GI-NEXT: cmp x15, #64
-; CHECK-GI-NEXT: lsr x12, x7, x12
-; CHECK-GI-NEXT: csel x15, x16, xzr, lo
-; CHECK-GI-NEXT: orr x9, x14, x9
+; CHECK-GI-NEXT: csel x15, x4, x15, eq
+; CHECK-GI-NEXT: lsr x13, x7, x13
+; CHECK-GI-NEXT: cmp x10, #64
+; CHECK-GI-NEXT: csel x10, x17, xzr, lo
+; CHECK-GI-NEXT: orr x9, x16, x9
; CHECK-GI-NEXT: cmp x1, #64
-; CHECK-GI-NEXT: lsr x14, x7, x1
-; CHECK-GI-NEXT: csel x9, x9, x12, lo
+; CHECK-GI-NEXT: csel x9, x9, x13, lo
+; CHECK-GI-NEXT: lsr x16, x7, x1
; CHECK-GI-NEXT: tst x8, #0x7f
; CHECK-GI-NEXT: csel x8, x6, x9, eq
; CHECK-GI-NEXT: cmp x1, #64
-; CHECK-GI-NEXT: orr x0, x0, x10
-; CHECK-GI-NEXT: csel x9, x14, xzr, lo
-; CHECK-GI-NEXT: orr x1, x13, x15
-; CHECK-GI-NEXT: orr x2, x17, x8
-; CHECK-GI-NEXT: orr x3, x11, x9
+; CHECK-GI-NEXT: orr x0, x0, x15
+; CHECK-GI-NEXT: csel x9, x16, xzr, lo
+; CHECK-GI-NEXT: orr x1, x14, x10
+; CHECK-GI-NEXT: orr x2, x11, x8
+; CHECK-GI-NEXT: orr x3, x12, x9
; CHECK-GI-NEXT: ret
entry:
%d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c)
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll
index c4e4d3c7dcd2b..3f35328315096 100644
--- a/llvm/test/CodeGen/AArch64/funnel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/funnel-shift.ll
@@ -85,40 +85,40 @@ define i128 @fshl_i128(i128 %x, i128 %y, i128 %z) nounwind {
;
; CHECK-GI-LABEL: fshl_i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: and x9, x4, #0x7f
-; CHECK-GI-NEXT: mov w10, #127 // =0x7f
-; CHECK-GI-NEXT: sub x12, x8, x9
-; CHECK-GI-NEXT: lsl x13, x1, x9
-; CHECK-GI-NEXT: bic x10, x10, x4
-; CHECK-GI-NEXT: lsr x12, x0, x12
-; CHECK-GI-NEXT: sub x14, x9, #64
-; CHECK-GI-NEXT: lsl x15, x0, x9
-; CHECK-GI-NEXT: extr x16, x3, x2, #1
+; CHECK-GI-NEXT: mov w10, #64 // =0x40
+; CHECK-GI-NEXT: mov w8, #127 // =0x7f
+; CHECK-GI-NEXT: sub x11, x10, x9
+; CHECK-GI-NEXT: lsl x12, x0, x9
+; CHECK-GI-NEXT: lsl x14, x1, x9
+; CHECK-GI-NEXT: lsr x11, x0, x11
+; CHECK-GI-NEXT: sub x13, x9, #64
+; CHECK-GI-NEXT: bic x8, x8, x4
+; CHECK-GI-NEXT: lsl x13, x0, x13
; CHECK-GI-NEXT: cmp x9, #64
-; CHECK-GI-NEXT: sub x8, x8, x10
-; CHECK-GI-NEXT: orr x9, x12, x13
-; CHECK-GI-NEXT: lsr x12, x3, #1
-; CHECK-GI-NEXT: lsl x13, x0, x14
-; CHECK-GI-NEXT: csel x14, x15, xzr, lo
-; CHECK-GI-NEXT: sub x15, x10, #64
-; CHECK-GI-NEXT: lsr x17, x16, x10
-; CHECK-GI-NEXT: lsl x8, x12, x8
-; CHECK-GI-NEXT: csel x9, x9, x13, lo
+; CHECK-GI-NEXT: csel x9, x12, xzr, lo
+; CHECK-GI-NEXT: orr x11, x11, x14
+; CHECK-GI-NEXT: extr x12, x3, x2, #1
+; CHECK-GI-NEXT: lsr x14, x3, #1
+; CHECK-GI-NEXT: sub x10, x10, x8
+; CHECK-GI-NEXT: csel x11, x11, x13, lo
+; CHECK-GI-NEXT: sub x13, x8, #64
+; CHECK-GI-NEXT: lsr x15, x12, x8
+; CHECK-GI-NEXT: lsl x10, x14, x10
; CHECK-GI-NEXT: tst x4, #0x7f
-; CHECK-GI-NEXT: lsr x13, x12, x15
-; CHECK-GI-NEXT: mvn x11, x4
-; CHECK-GI-NEXT: csel x9, x1, x9, eq
-; CHECK-GI-NEXT: orr x8, x17, x8
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: lsr x12, x12, x10
-; CHECK-GI-NEXT: csel x8, x8, x13, lo
-; CHECK-GI-NEXT: tst x11, #0x7f
-; CHECK-GI-NEXT: csel x8, x16, x8, eq
-; CHECK-GI-NEXT: cmp x10, #64
-; CHECK-GI-NEXT: csel x10, x12, xzr, lo
-; CHECK-GI-NEXT: orr x0, x14, x8
-; CHECK-GI-NEXT: orr x1, x9, x10
+; CHECK-GI-NEXT: lsr x13, x14, x13
+; CHECK-GI-NEXT: mvn x16, x4
+; CHECK-GI-NEXT: csel x11, x1, x11, eq
+; CHECK-GI-NEXT: lsr x14, x14, x8
+; CHECK-GI-NEXT: orr x10, x15, x10
+; CHECK-GI-NEXT: cmp x8, #64
+; CHECK-GI-NEXT: csel x10, x10, x13, lo
+; CHECK-GI-NEXT: tst x16, #0x7f
+; CHECK-GI-NEXT: csel x10, x12, x10, eq
+; CHECK-GI-NEXT: cmp x8, #64
+; CHECK-GI-NEXT: csel x8, x14, xzr, lo
+; CHECK-GI-NEXT: orr x0, x9, x10
+; CHECK-GI-NEXT: orr x1, x11, x8
; CHECK-GI-NEXT: ret
%f = call i128 @llvm.fshl.i128(i128 %x, i128 %y, i128 %z)
ret i128 %f
diff --git a/llvm/test/CodeGen/AArch64/gpr_cttz.ll b/llvm/test/CodeGen/AArch64/gpr_cttz.ll
index 3b8269385d27d..3c65a4625961d 100644
--- a/llvm/test/CodeGen/AArch64/gpr_cttz.ll
+++ b/llvm/test/CodeGen/AArch64/gpr_cttz.ll
@@ -105,11 +105,11 @@ define i128 @cttz128(i128 %x) nounwind readnone {
; CHECK: // %bb.0:
; CHECK-NEXT: rbit x8, x1
; CHECK-NEXT: rbit x9, x0
-; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: clz x8, x8
; CHECK-NEXT: clz x9, x9
; CHECK-NEXT: add x8, x8, #64
+; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x0, x9, x8, ne
; CHECK-NEXT: ret
;
@@ -117,9 +117,9 @@ define i128 @cttz128(i128 %x) nounwind readnone {
; CHECK-CSSC: // %bb.0:
; CHECK-CSSC-NEXT: ctz x8, x1
; CHECK-CSSC-NEXT: ctz x9, x0
-; CHECK-CSSC-NEXT: cmp x0, #0
-; CHECK-CSSC-NEXT: add x8, x8, #64
; CHECK-CSSC-NEXT: mov x1, xzr
+; CHECK-CSSC-NEXT: add x8, x8, #64
+; CHECK-CSSC-NEXT: cmp x0, #0
; CHECK-CSSC-NEXT: csel x0, x9, x8, ne
; CHECK-CSSC-NEXT: ret
%ctz = tail call i128 @llvm.cttz.i128(i128 %x)
diff --git a/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll b/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
index d0026db0176e1..84b6cc174023a 100644
--- a/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
@@ -92,19 +92,19 @@ define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(ptr %a, ptr %
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: cnth x8
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: sub x8, x8, #8
+; CHECK-NEXT: cnth x8
+; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: mov w9, #8 // =0x8
+; CHECK-NEXT: sub x8, x8, #8
+; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
; CHECK-NEXT: cmp x8, #8
-; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: csel x8, x8, x9, lo
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: lsl x8, x8, #1
-; CHECK-NEXT: str z0, [sp]
-; CHECK-NEXT: str q1, [x9, x8]
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: str z1, [sp]
+; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ldr z0, [sp]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -136,19 +136,19 @@ define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(ptr %a, ptr
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: cntw x8
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: sub x8, x8, #4
+; CHECK-NEXT: cntw x8
+; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: mov w9, #4 // =0x4
+; CHECK-NEXT: sub x8, x8, #4
+; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT: cmp x8, #4
-; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: csel x8, x8, x9, lo
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: lsl x8, x8, #2
-; CHECK-NEXT: str z0, [sp]
-; CHECK-NEXT: str q1, [x9, x8]
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: str z1, [sp]
+; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ldr z0, [sp]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -180,19 +180,19 @@ define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(ptr %a, ptr
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: cntd x8
; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: sub x8, x8, #2
+; CHECK-NEXT: cntd x8
+; CHECK-NEXT: ldr d0, [x1]
; CHECK-NEXT: mov w9, #2 // =0x2
+; CHECK-NEXT: sub x8, x8, #2
+; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]
; CHECK-NEXT: cmp x8, #2
-; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
-; CHECK-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-NEXT: csel x8, x8, x9, lo
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: lsl x8, x8, #3
-; CHECK-NEXT: str z0, [sp]
-; CHECK-NEXT: str q1, [x9, x8]
+; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: str z1, [sp]
+; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ldr z0, [sp]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll b/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
index 4a74a2587b39c..3e1f06b2db080 100644
--- a/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
+++ b/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
@@ -9,13 +9,13 @@ define i32 @ctz_nxv32i1(<vscale x 32 x i1> %a) #0 {
; NONSTREAMING: // %bb.0:
; NONSTREAMING-NEXT: ptrue p2.b
; NONSTREAMING-NEXT: rdvl x8, #1
-; NONSTREAMING-NEXT: mov w10, w8
-; NONSTREAMING-NEXT: brkb p0.b, p2/z, p0.b
+; NONSTREAMING-NEXT: mov w9, w8
; NONSTREAMING-NEXT: brkb p1.b, p2/z, p1.b
-; NONSTREAMING-NEXT: cntp x9, p0, p0.b
+; NONSTREAMING-NEXT: brkb p0.b, p2/z, p0.b
; NONSTREAMING-NEXT: incp x8, p1.b
-; NONSTREAMING-NEXT: cmp w9, w10
-; NONSTREAMING-NEXT: csel w0, w9, w8, ne
+; NONSTREAMING-NEXT: cntp x10, p0, p0.b
+; NONSTREAMING-NEXT: cmp w10, w9
+; NONSTREAMING-NEXT: csel w0, w10, w8, ne
; NONSTREAMING-NEXT: ret
;
; STREAMING-LABEL: ctz_nxv32i1:
diff --git a/llvm/test/CodeGen/AArch64/itofp-bf16.ll b/llvm/test/CodeGen/AArch64/itofp-bf16.ll
index 77d0c318f0fc4..cd6cf182d3618 100644
--- a/llvm/test/CodeGen/AArch64/itofp-bf16.ll
+++ b/llvm/test/CodeGen/AArch64/itofp-bf16.ll
@@ -124,13 +124,13 @@ define bfloat @stofp_i64_bf16(i64 %a) {
; CHECK-NOFP16-LABEL: stofp_i64_bf16:
; CHECK-NOFP16: // %bb.0: // %entry
; CHECK-NOFP16-NEXT: cmp x0, #0
-; CHECK-NOFP16-NEXT: and x11, x0, #0x8000000000000000
; CHECK-NOFP16-NEXT: mov w8, #32767 // =0x7fff
; CHECK-NOFP16-NEXT: cneg x9, x0, mi
; CHECK-NOFP16-NEXT: lsr x10, x9, #53
+; CHECK-NOFP16-NEXT: and x11, x9, #0xfffffffffffff000
; CHECK-NOFP16-NEXT: cmp x10, #0
-; CHECK-NOFP16-NEXT: and x10, x9, #0xfffffffffffff000
-; CHECK-NOFP16-NEXT: csel x10, x10, x9, ne
+; CHECK-NOFP16-NEXT: csel x10, x11, x9, ne
+; CHECK-NOFP16-NEXT: and x11, x0, #0x8000000000000000
; CHECK-NOFP16-NEXT: scvtf d0, x10
; CHECK-NOFP16-NEXT: cset w10, ne
; CHECK-NOFP16-NEXT: tst x9, #0xfff
@@ -158,8 +158,8 @@ define bfloat @stofp_i64_bf16(i64 %a) {
; CHECK-FP16-NEXT: cmp x9, #0
; CHECK-FP16-NEXT: csel x9, x10, x8, ne
; CHECK-FP16-NEXT: and x10, x0, #0x8000000000000000
-; CHECK-FP16-NEXT: cset w11, ne
; CHECK-FP16-NEXT: scvtf d0, x9
+; CHECK-FP16-NEXT: cset w11, ne
; CHECK-FP16-NEXT: tst x8, #0xfff
; CHECK-FP16-NEXT: fmov x9, d0
; CHECK-FP16-NEXT: orr x8, x9, x10
@@ -178,10 +178,10 @@ define bfloat @utofp_i64_bf16(i64 %a) {
; CHECK-NOFP16-LABEL: utofp_i64_bf16:
; CHECK-NOFP16: // %bb.0: // %entry
; CHECK-NOFP16-NEXT: lsr x9, x0, #53
+; CHECK-NOFP16-NEXT: and x10, x0, #0xfffffffffffff000
; CHECK-NOFP16-NEXT: mov w8, #32767 // =0x7fff
; CHECK-NOFP16-NEXT: cmp x9, #0
-; CHECK-NOFP16-NEXT: and x9, x0, #0xfffffffffffff000
-; CHECK-NOFP16-NEXT: csel x9, x9, x0, ne
+; CHECK-NOFP16-NEXT: csel x9, x10, x0, ne
; CHECK-NOFP16-NEXT: ucvtf d0, x9
; CHECK-NOFP16-NEXT: cset w9, ne
; CHECK-NOFP16-NEXT: tst x0, #0xfff
@@ -397,13 +397,13 @@ define <2 x bfloat> @stofp_v2i64_v2bf16(<2 x i64> %a) {
; CHECK-NOFP16-NEXT: cneg x13, x10, mi
; CHECK-NOFP16-NEXT: and x10, x10, #0x8000000000000000
; CHECK-NOFP16-NEXT: lsr x14, x13, #53
+; CHECK-NOFP16-NEXT: and x15, x13, #0xfffffffffffff000
; CHECK-NOFP16-NEXT: cmp x14, #0
-; CHECK-NOFP16-NEXT: and x14, x13, #0xfffffffffffff000
-; CHECK-NOFP16-NEXT: csel x11, x14, x13, ne
-; CHECK-NOFP16-NEXT: cset w14, ne
-; CHECK-NOFP16-NEXT: tst x13, #0xfff
+; CHECK-NOFP16-NEXT: csel x11, x15, x13, ne
; CHECK-NOFP16-NEXT: scvtf d1, x11
; CHECK-NOFP16-NEXT: fmov x11, d0
+; CHECK-NOFP16-NEXT: cset w14, ne
+; CHECK-NOFP16-NEXT: tst x13, #0xfff
; CHECK-NOFP16-NEXT: orr x9, x11, x9
; CHECK-NOFP16-NEXT: csel w11, wzr, w14, eq
; CHECK-NOFP16-NEXT: fmov x13, d1
@@ -449,13 +449,13 @@ define <2 x bfloat> @stofp_v2i64_v2bf16(<2 x i64> %a) {
; CHECK-FP16-NEXT: cneg x12, x9, mi
; CHECK-FP16-NEXT: and x9, x9, #0x8000000000000000
; CHECK-FP16-NEXT: lsr x13, x12, #53
+; CHECK-FP16-NEXT: and x14, x12, #0xfffffffffffff000
; CHECK-FP16-NEXT: cmp x13, #0
-; CHECK-FP16-NEXT: and x13, x12, #0xfffffffffffff000
-; CHECK-FP16-NEXT: csel x10, x13, x12, ne
-; CHECK-FP16-NEXT: cset w13, ne
-; CHECK-FP16-NEXT: tst x12, #0xfff
+; CHECK-FP16-NEXT: csel x10, x14, x12, ne
; CHECK-FP16-NEXT: scvtf d1, x10
; CHECK-FP16-NEXT: fmov x10, d0
+; CHECK-FP16-NEXT: cset w13, ne
+; CHECK-FP16-NEXT: tst x12, #0xfff
; CHECK-FP16-NEXT: orr x8, x10, x8
; CHECK-FP16-NEXT: csel w10, wzr, w13, eq
; CHECK-FP16-NEXT: fmov x12, d1
@@ -480,37 +480,37 @@ define <2 x bfloat> @utofp_v2i64_v2bf16(<2 x i64> %a) {
; CHECK-NOFP16-LABEL: utofp_v2i64_v2bf16:
; CHECK-NOFP16: // %bb.0: // %entry
; CHECK-NOFP16-NEXT: mov x9, v0.d[1]
-; CHECK-NOFP16-NEXT: fmov x11, d0
+; CHECK-NOFP16-NEXT: fmov x12, d0
; CHECK-NOFP16-NEXT: mov w8, #32767 // =0x7fff
; CHECK-NOFP16-NEXT: lsr x10, x9, #53
-; CHECK-NOFP16-NEXT: and x12, x9, #0xfffffffffffff000
+; CHECK-NOFP16-NEXT: and x11, x9, #0xfffffffffffff000
; CHECK-NOFP16-NEXT: cmp x10, #0
-; CHECK-NOFP16-NEXT: lsr x10, x11, #53
-; CHECK-NOFP16-NEXT: csel x12, x12, x9, ne
+; CHECK-NOFP16-NEXT: csel x10, x11, x9, ne
+; CHECK-NOFP16-NEXT: lsr x11, x12, #53
; CHECK-NOFP16-NEXT: cset w13, ne
; CHECK-NOFP16-NEXT: tst x9, #0xfff
-; CHECK-NOFP16-NEXT: csel w9, wzr, w13, eq
-; CHECK-NOFP16-NEXT: cmp x10, #0
-; CHECK-NOFP16-NEXT: and x10, x11, #0xfffffffffffff000
-; CHECK-NOFP16-NEXT: csel x10, x10, x11, ne
-; CHECK-NOFP16-NEXT: ucvtf d0, x12
-; CHECK-NOFP16-NEXT: ucvtf d1, x10
-; CHECK-NOFP16-NEXT: cset w10, ne
-; CHECK-NOFP16-NEXT: tst x11, #0xfff
-; CHECK-NOFP16-NEXT: csel w10, wzr, w10, eq
-; CHECK-NOFP16-NEXT: fmov x11, d0
-; CHECK-NOFP16-NEXT: fmov x12, d1
+; CHECK-NOFP16-NEXT: and x9, x12, #0xfffffffffffff000
+; CHECK-NOFP16-NEXT: csel w13, wzr, w13, eq
+; CHECK-NOFP16-NEXT: cmp x11, #0
+; CHECK-NOFP16-NEXT: csel x9, x9, x12, ne
+; CHECK-NOFP16-NEXT: ucvtf d0, x10
+; CHECK-NOFP16-NEXT: ucvtf d1, x9
+; CHECK-NOFP16-NEXT: cset w9, ne
+; CHECK-NOFP16-NEXT: tst x12, #0xfff
+; CHECK-NOFP16-NEXT: csel w9, wzr, w9, eq
+; CHECK-NOFP16-NEXT: fmov x10, d0
+; CHECK-NOFP16-NEXT: fmov x11, d1
+; CHECK-NOFP16-NEXT: orr x10, x10, x13
; CHECK-NOFP16-NEXT: orr x9, x11, x9
-; CHECK-NOFP16-NEXT: orr x10, x12, x10
-; CHECK-NOFP16-NEXT: fmov d0, x9
-; CHECK-NOFP16-NEXT: fmov d1, x10
+; CHECK-NOFP16-NEXT: fmov d0, x10
+; CHECK-NOFP16-NEXT: fmov d1, x9
; CHECK-NOFP16-NEXT: fcvtxn s0, d0
; CHECK-NOFP16-NEXT: fcvtxn s1, d1
; CHECK-NOFP16-NEXT: fmov w9, s0
; CHECK-NOFP16-NEXT: fmov w10, s1
; CHECK-NOFP16-NEXT: ubfx w11, w9, #16, #1
-; CHECK-NOFP16-NEXT: add w9, w9, w8
; CHECK-NOFP16-NEXT: ubfx w12, w10, #16, #1
+; CHECK-NOFP16-NEXT: add w9, w9, w8
; CHECK-NOFP16-NEXT: add w8, w10, w8
; CHECK-NOFP16-NEXT: add w9, w11, w9
; CHECK-NOFP16-NEXT: add w8, w12, w8
@@ -525,29 +525,29 @@ define <2 x bfloat> @utofp_v2i64_v2bf16(<2 x i64> %a) {
; CHECK-FP16-LABEL: utofp_v2i64_v2bf16:
; CHECK-FP16: // %bb.0: // %entry
; CHECK-FP16-NEXT: mov x8, v0.d[1]
-; CHECK-FP16-NEXT: fmov x10, d0
+; CHECK-FP16-NEXT: fmov x11, d0
; CHECK-FP16-NEXT: lsr x9, x8, #53
-; CHECK-FP16-NEXT: and x11, x8, #0xfffffffffffff000
+; CHECK-FP16-NEXT: and x10, x8, #0xfffffffffffff000
; CHECK-FP16-NEXT: cmp x9, #0
-; CHECK-FP16-NEXT: lsr x9, x10, #53
-; CHECK-FP16-NEXT: csel x11, x11, x8, ne
+; CHECK-FP16-NEXT: csel x9, x10, x8, ne
+; CHECK-FP16-NEXT: lsr x10, x11, #53
; CHECK-FP16-NEXT: cset w12, ne
; CHECK-FP16-NEXT: tst x8, #0xfff
-; CHECK-FP16-NEXT: csel w8, wzr, w12, eq
-; CHECK-FP16-NEXT: cmp x9, #0
-; CHECK-FP16-NEXT: and x9, x10, #0xfffffffffffff000
-; CHECK-FP16-NEXT: csel x9, x9, x10, ne
-; CHECK-FP16-NEXT: ucvtf d0, x11
-; CHECK-FP16-NEXT: ucvtf d1, x9
-; CHECK-FP16-NEXT: cset w9, ne
-; CHECK-FP16-NEXT: tst x10, #0xfff
-; CHECK-FP16-NEXT: csel w9, wzr, w9, eq
-; CHECK-FP16-NEXT: fmov x10, d0
-; CHECK-FP16-NEXT: fmov x11, d1
+; CHECK-FP16-NEXT: and x8, x11, #0xfffffffffffff000
+; CHECK-FP16-NEXT: csel w12, wzr, w12, eq
+; CHECK-FP16-NEXT: cmp x10, #0
+; CHECK-FP16-NEXT: csel x8, x8, x11, ne
+; CHECK-FP16-NEXT: ucvtf d0, x9
+; CHECK-FP16-NEXT: ucvtf d1, x8
+; CHECK-FP16-NEXT: cset w8, ne
+; CHECK-FP16-NEXT: tst x11, #0xfff
+; CHECK-FP16-NEXT: csel w8, wzr, w8, eq
+; CHECK-FP16-NEXT: fmov x9, d0
+; CHECK-FP16-NEXT: fmov x10, d1
+; CHECK-FP16-NEXT: orr x9, x9, x12
; CHECK-FP16-NEXT: orr x8, x10, x8
-; CHECK-FP16-NEXT: orr x9, x11, x9
-; CHECK-FP16-NEXT: fmov d0, x8
-; CHECK-FP16-NEXT: fmov d1, x9
+; CHECK-FP16-NEXT: fmov d0, x9
+; CHECK-FP16-NEXT: fmov d1, x8
; CHECK-FP16-NEXT: fcvtxn s0, d0
; CHECK-FP16-NEXT: fcvtxn s1, d1
; CHECK-FP16-NEXT: bfcvt h2, s0
diff --git a/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll b/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
index 398a2ac24e5d0..51679c2afd405 100644
--- a/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
+++ b/llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
@@ -8,12 +8,12 @@ define i64 @csed_impdef_killflag(i64 %a) {
; CHECK-LABEL: csed_impdef_killflag:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #1 ; =0x1
-; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: mov x9, #2 ; =0x2
-; CHECK-NEXT: csel w8, wzr, w8, ne
; CHECK-NEXT: mov x10, #3 ; =0x3
-; CHECK-NEXT: lsr w8, w8, #0
+; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: csel x9, x9, x10, ne
+; CHECK-NEXT: csel w8, wzr, w8, ne
+; CHECK-NEXT: lsr w8, w8, #0
; CHECK-NEXT: add x0, x9, x8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
index dc7c3cbf9459c..89f929bbd52df 100644
--- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
+++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
@@ -132,9 +132,9 @@ define <4 x i32> @splice_left_v4i32_variable_offset(<4 x i32> %a, <4 x i32> %b,
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: ubfiz x8, x0, #2, #32
+; CHECK-NEXT: stp q0, q1, [sp, #-32]!
; CHECK-NEXT: mov w9, #16 // =0x10
; CHECK-NEXT: cmp x8, #16
-; CHECK-NEXT: stp q0, q1, [sp, #-32]!
; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr q0, [x9, x8]
diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
index 747c134913931..5aadd559dccdb 100644
--- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
+++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
@@ -587,11 +587,11 @@ define <vscale x 16 x i8> @splice_nxv16i8_neg17(<vscale x 16 x i8> %a, <vscale x
; CHECK-NEXT: mov w9, #17 // =0x11
; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: cmp x8, #17
-; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: add x8, x10, x8
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
+; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: sub x8, x8, x9
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: ldr z0, [x8]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -631,11 +631,11 @@ define <vscale x 8 x i16> @splice_nxv8i16_neg9(<vscale x 8 x i16> %a, <vscale x
; CHECK-NEXT: mov w9, #18 // =0x12
; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: cmp x8, #18
-; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: add x8, x10, x8
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
+; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: sub x8, x8, x9
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: ldr z0, [x8]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -741,11 +741,11 @@ define <vscale x 8 x half> @splice_nxv8f16_neg9(<vscale x 8 x half> %a, <vscale
; CHECK-NEXT: mov w9, #18 // =0x12
; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: cmp x8, #18
-; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: csel x9, x8, x9, lo
; CHECK-NEXT: add x8, x10, x8
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
+; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: sub x8, x8, x9
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: ldr z0, [x8]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -1118,8 +1118,8 @@ define <vscale x 4 x i32> @splice_left_nxv4i32_variable_offset(<vscale x 4 x i32
; CHECK-NEXT: rdvl x9, #1
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: str z0, [sp]
-; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: str z1, [sp, #1, mul vl]
+; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x9, x8]
@@ -1141,9 +1141,9 @@ define <vscale x 4 x i32> @splice_right_nxv4i32_variable_offset(<vscale x 4 x i3
; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: cmp x8, x9
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: add x9, x10, x9
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: sub x8, x9, x8
; CHECK-NEXT: ldr z0, [x8]
; CHECK-NEXT: addvl sp, sp, #2
diff --git a/llvm/test/CodeGen/AArch64/overflow-vec.ll b/llvm/test/CodeGen/AArch64/overflow-vec.ll
index 3b7a50122cb1f..0c4ed6a9877ed 100644
--- a/llvm/test/CodeGen/AArch64/overflow-vec.ll
+++ b/llvm/test/CodeGen/AArch64/overflow-vec.ll
@@ -3233,9 +3233,9 @@ define <2 x i128> @umul_v2i128(<2 x i128> %a, <2 x i128> %b) {
; CHECK-GI-NEXT: mul x5, x2, x6
; CHECK-GI-NEXT: add x9, x12, x9
; CHECK-GI-NEXT: orr x9, x18, x9
-; CHECK-GI-NEXT: csel x1, x10, x1, ne
; CHECK-GI-NEXT: madd x16, x3, x6, x17
; CHECK-GI-NEXT: csel x0, x4, x0, ne
+; CHECK-GI-NEXT: csel x1, x10, x1, ne
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x2, x5, x2, ne
; CHECK-GI-NEXT: csel x3, x16, x3, ne
@@ -3750,11 +3750,11 @@ define <3 x i128> @umul_v3i128(<3 x i128> %a, <3 x i128> %b) {
; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: mul x22, x4, x12
; CHECK-GI-NEXT: ldp x26, x25, [sp, #64] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x3, x6, x3, ne
; CHECK-GI-NEXT: ldp x28, x27, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: madd x12, x5, x12, x17
; CHECK-GI-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x2, x10, x2, ne
+; CHECK-GI-NEXT: csel x3, x6, x3, ne
; CHECK-GI-NEXT: cmp x9, #0
; CHECK-GI-NEXT: csel x4, x22, x4, ne
; CHECK-GI-NEXT: ldp x22, x21, [sp, #96] // 16-byte Folded Reload
@@ -3873,13 +3873,13 @@ define <3 x i128> @smul_v3i128(<3 x i128> %a, <3 x i128> %b) {
; CHECK-SD-NEXT: orr x14, x14, x17
; CHECK-SD-NEXT: orr x13, x18, x15
; CHECK-SD-NEXT: cmp x14, #0
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x0, x6, x0, ne
; CHECK-SD-NEXT: csel x1, x12, x1, ne
; CHECK-SD-NEXT: cmp x13, #0
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x2, x9, x2, ne
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
; CHECK-SD-NEXT: csel x3, x16, x3, ne
+; CHECK-SD-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
; CHECK-SD-NEXT: cmp x11, #0
; CHECK-SD-NEXT: csel x4, x8, x4, ne
; CHECK-SD-NEXT: csel x5, x10, x5, ne
@@ -4064,8 +4064,8 @@ define <3 x i128> @smul_v3i128(<3 x i128> %a, <3 x i128> %b) {
; CHECK-GI-NEXT: add x8, x6, x8
; CHECK-GI-NEXT: add x11, x18, x11
; CHECK-GI-NEXT: eor x15, x15, x19, asr #63
-; CHECK-GI-NEXT: eor x8, x8, x7, asr #63
; CHECK-GI-NEXT: mul x10, x2, x10
+; CHECK-GI-NEXT: eor x8, x8, x7, asr #63
; CHECK-GI-NEXT: eor x11, x11, x19, asr #63
; CHECK-GI-NEXT: ldp x24, x23, [sp, #80] // 16-byte Folded Reload
; CHECK-GI-NEXT: mul x12, x4, x12
@@ -4077,13 +4077,13 @@ define <3 x i128> @smul_v3i128(<3 x i128> %a, <3 x i128> %b) {
; CHECK-GI-NEXT: csel x0, x17, x0, ne
; CHECK-GI-NEXT: csel x1, x7, x1, ne
; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: csel x2, x10, x2, ne
; CHECK-GI-NEXT: orr x9, x9, x14
; CHECK-GI-NEXT: csel x3, x19, x3, ne
-; CHECK-GI-NEXT: csel x2, x10, x2, ne
; CHECK-GI-NEXT: ldp x20, x19, [sp, #112] // 16-byte Folded Reload
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: ldp x26, x25, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x4, x12, x4, ne
+; CHECK-GI-NEXT: ldp x26, x25, [sp, #64] // 16-byte Folded Reload
; CHECK-GI-NEXT: ldp x28, x27, [sp, #48] // 16-byte Folded Reload
; CHECK-GI-NEXT: csel x5, x13, x5, ne
; CHECK-GI-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
@@ -4311,14 +4311,14 @@ define <4 x i128> @umul_v4i128(<4 x i128> %a, <4 x i128> %b) {
;
; CHECK-GI-LABEL: umul_v4i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #208
-; CHECK-GI-NEXT: stp x29, x30, [sp, #112] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x28, x27, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x26, x25, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #176] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #192] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 208
+; CHECK-GI-NEXT: sub sp, sp, #192
+; CHECK-GI-NEXT: stp x29, x30, [sp, #96] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x28, x27, [sp, #112] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x26, x25, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x24, x23, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 192
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
@@ -4331,189 +4331,191 @@ define <4 x i128> @umul_v4i128(<4 x i128> %a, <4 x i128> %b) {
; CHECK-GI-NEXT: .cfi_offset w28, -80
; CHECK-GI-NEXT: .cfi_offset w30, -88
; CHECK-GI-NEXT: .cfi_offset w29, -96
-; CHECK-GI-NEXT: ldp x11, x19, [sp, #208]
-; CHECK-GI-NEXT: mov x22, x2
-; CHECK-GI-NEXT: ldp x23, x25, [sp, #224]
-; CHECK-GI-NEXT: mov x27, x6
-; CHECK-GI-NEXT: mov x21, x0
+; CHECK-GI-NEXT: ldp x26, x27, [sp, #208]
+; CHECK-GI-NEXT: mov x30, x1
+; CHECK-GI-NEXT: ldp x12, x19, [sp, #192]
; CHECK-GI-NEXT: mov x24, x4
-; CHECK-GI-NEXT: mov x28, x1
-; CHECK-GI-NEXT: umulh x9, x11, xzr
-; CHECK-GI-NEXT: mov x17, x7
-; CHECK-GI-NEXT: umulh x8, x1, x19
-; CHECK-GI-NEXT: umulh x20, x2, x23
-; CHECK-GI-NEXT: mul x6, x2, x25
-; CHECK-GI-NEXT: stp x8, x9, [sp, #96] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mul x9, x3, x25
-; CHECK-GI-NEXT: umulh x8, x3, x25
-; CHECK-GI-NEXT: umulh x18, x2, x25
-; CHECK-GI-NEXT: ldp x2, x30, [sp, #240]
-; CHECK-GI-NEXT: umulh x14, x0, x11
-; CHECK-GI-NEXT: stp x9, x8, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mul x9, x4, x30
-; CHECK-GI-NEXT: umulh x8, x4, x30
+; CHECK-GI-NEXT: ldp x28, x29, [sp, #224]
+; CHECK-GI-NEXT: mov x22, x0
+; CHECK-GI-NEXT: mul x8, x2, x27
+; CHECK-GI-NEXT: mov x18, x7
+; CHECK-GI-NEXT: mov x23, x2
+; CHECK-GI-NEXT: mov x25, x6
+; CHECK-GI-NEXT: mov x6, x5
+; CHECK-GI-NEXT: umulh x9, x30, x19
+; CHECK-GI-NEXT: umulh x11, x0, x12
+; CHECK-GI-NEXT: str x8, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: mul x8, x3, x27
+; CHECK-GI-NEXT: umulh x21, x2, x26
+; CHECK-GI-NEXT: mul x13, x1, x12
+; CHECK-GI-NEXT: str x8, [sp, #56] // 8-byte Spill
+; CHECK-GI-NEXT: umulh x8, x26, xzr
+; CHECK-GI-NEXT: umulh x1, x1, x12
+; CHECK-GI-NEXT: umulh x20, x12, xzr
+; CHECK-GI-NEXT: stp x8, x9, [sp, #80] // 16-byte Folded Spill
+; CHECK-GI-NEXT: umulh x8, x3, x27
; CHECK-GI-NEXT: mul x15, x0, x19
-; CHECK-GI-NEXT: umulh x16, x0, x19
-; CHECK-GI-NEXT: stp x8, x9, [sp, #32] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mul x8, x21, x11
-; CHECK-GI-NEXT: mul x0, x1, x19
-; CHECK-GI-NEXT: madd x19, x21, x19, x14
-; CHECK-GI-NEXT: adds x14, x14, x15
-; CHECK-GI-NEXT: stp x3, x8, [sp, #48] // 16-byte Folded Spill
+; CHECK-GI-NEXT: umulh x10, x0, x19
+; CHECK-GI-NEXT: str x8, [sp, #72] // 8-byte Spill
+; CHECK-GI-NEXT: madd x8, x0, x19, x11
+; CHECK-GI-NEXT: adds x11, x11, x15
+; CHECK-GI-NEXT: mul x17, x30, x19
; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: madd x29, x22, x25, x20
+; CHECK-GI-NEXT: cmn x11, x13
+; CHECK-GI-NEXT: cset w11, hs
; CHECK-GI-NEXT: and x15, x15, #0x1
-; CHECK-GI-NEXT: madd x9, x1, x11, x19
-; CHECK-GI-NEXT: madd x8, x3, x23, x29
-; CHECK-GI-NEXT: mul x12, x1, x11
-; CHECK-GI-NEXT: umulh x26, x4, x2
-; CHECK-GI-NEXT: stp x8, x9, [sp, #64] // 16-byte Folded Spill
-; CHECK-GI-NEXT: umulh x8, x5, x30
-; CHECK-GI-NEXT: cmn x14, x12
-; CHECK-GI-NEXT: umulh x13, x1, x11
-; CHECK-GI-NEXT: mul x4, x5, x30
+; CHECK-GI-NEXT: madd x8, x30, x12, x8
+; CHECK-GI-NEXT: mul x12, x0, x12
+; CHECK-GI-NEXT: mul x4, x3, x26
+; CHECK-GI-NEXT: str x8, [sp, #48] // 8-byte Spill
+; CHECK-GI-NEXT: madd x8, x2, x27, x21
+; CHECK-GI-NEXT: umulh x16, x3, x26
+; CHECK-GI-NEXT: madd x8, x3, x26, x8
+; CHECK-GI-NEXT: umulh x14, x2, x27
+; CHECK-GI-NEXT: umulh x9, x24, x28
+; CHECK-GI-NEXT: stp x3, x8, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: mul x8, x2, x26
+; CHECK-GI-NEXT: mul x0, x24, x29
+; CHECK-GI-NEXT: umulh x3, x24, x29
+; CHECK-GI-NEXT: stp x12, x8, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: umulh x8, x5, x29
+; CHECK-GI-NEXT: mul x7, x5, x29
+; CHECK-GI-NEXT: madd x29, x24, x29, x9
+; CHECK-GI-NEXT: str x8, [sp] // 8-byte Spill
+; CHECK-GI-NEXT: and x8, x11, #0x1
+; CHECK-GI-NEXT: add x8, x15, x8
+; CHECK-GI-NEXT: adds x15, x1, x10
+; CHECK-GI-NEXT: umulh x13, x5, x28
+; CHECK-GI-NEXT: cset w12, hs
+; CHECK-GI-NEXT: adds x15, x15, x17
+; CHECK-GI-NEXT: cset w10, hs
+; CHECK-GI-NEXT: adds x8, x15, x8
+; CHECK-GI-NEXT: mul x17, x5, x28
; CHECK-GI-NEXT: str x8, [sp, #8] // 8-byte Spill
-; CHECK-GI-NEXT: madd x8, x24, x30, x26
-; CHECK-GI-NEXT: mul x9, x3, x23
-; CHECK-GI-NEXT: umulh x10, x3, x23
-; CHECK-GI-NEXT: umulh x30, x23, xzr
-; CHECK-GI-NEXT: mul x11, x22, x23
-; CHECK-GI-NEXT: cset w23, hs
-; CHECK-GI-NEXT: adds x16, x13, x16
-; CHECK-GI-NEXT: and x23, x23, #0x1
-; CHECK-GI-NEXT: madd x8, x5, x2, x8
-; CHECK-GI-NEXT: add x15, x15, x23
-; CHECK-GI-NEXT: cset w23, hs
-; CHECK-GI-NEXT: adds x16, x16, x0
-; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x29, x16, x15
-; CHECK-GI-NEXT: umulh x12, x5, x2
-; CHECK-GI-NEXT: cset w1, hs
-; CHECK-GI-NEXT: adds x16, x20, x6
-; CHECK-GI-NEXT: cset w20, hs
-; CHECK-GI-NEXT: cmn x16, x9
-; CHECK-GI-NEXT: umulh x3, x21, xzr
-; CHECK-GI-NEXT: stp x11, x8, [sp, #16] // 16-byte Folded Spill
-; CHECK-GI-NEXT: cset w9, hs
-; CHECK-GI-NEXT: ldr x8, [sp, #80] // 8-byte Reload
-; CHECK-GI-NEXT: adds x10, x10, x18
-; CHECK-GI-NEXT: and x18, x20, #0x1
-; CHECK-GI-NEXT: and x9, x9, #0x1
-; CHECK-GI-NEXT: mul x11, x5, x2
+; CHECK-GI-NEXT: ldr x8, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: cset w11, hs
+; CHECK-GI-NEXT: and x10, x10, #0x1
+; CHECK-GI-NEXT: umulh x2, x22, xzr
+; CHECK-GI-NEXT: adds x15, x21, x8
+; CHECK-GI-NEXT: ldr x8, [sp, #56] // 8-byte Reload
+; CHECK-GI-NEXT: cset w21, hs
+; CHECK-GI-NEXT: cmn x15, x4
+; CHECK-GI-NEXT: umulh x26, x23, xzr
; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: adds x10, x10, x8
-; CHECK-GI-NEXT: add x9, x18, x9
-; CHECK-GI-NEXT: cset w20, hs
-; CHECK-GI-NEXT: and x1, x1, #0x1
-; CHECK-GI-NEXT: adds x25, x10, x9
-; CHECK-GI-NEXT: ldp x10, x8, [sp, #32] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x16, x18, [sp, #256]
-; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: umulh x7, x22, xzr
+; CHECK-GI-NEXT: adds x14, x16, x14
+; CHECK-GI-NEXT: and x21, x21, #0x1
; CHECK-GI-NEXT: and x15, x15, #0x1
-; CHECK-GI-NEXT: and x20, x20, #0x1
-; CHECK-GI-NEXT: adds x26, x26, x8
-; CHECK-GI-NEXT: add x15, x15, x20
-; CHECK-GI-NEXT: and x13, x13, #0x1
-; CHECK-GI-NEXT: umulh x14, x27, x16
-; CHECK-GI-NEXT: cset w8, hs
-; CHECK-GI-NEXT: cmn x26, x11
-; CHECK-GI-NEXT: cset w26, hs
-; CHECK-GI-NEXT: and x8, x8, #0x1
-; CHECK-GI-NEXT: adds x12, x12, x10
-; CHECK-GI-NEXT: mul x11, x27, x18
-; CHECK-GI-NEXT: and x26, x26, #0x1
-; CHECK-GI-NEXT: add x8, x8, x26
-; CHECK-GI-NEXT: cset w26, hs
-; CHECK-GI-NEXT: adds x12, x12, x4
-; CHECK-GI-NEXT: mul x9, x17, x16
+; CHECK-GI-NEXT: cset w4, hs
+; CHECK-GI-NEXT: adds x16, x14, x8
+; CHECK-GI-NEXT: add x15, x21, x15
+; CHECK-GI-NEXT: cset w1, hs
+; CHECK-GI-NEXT: umulh x19, x28, xzr
+; CHECK-GI-NEXT: adds x27, x16, x15
+; CHECK-GI-NEXT: ldp x14, x16, [sp, #240]
+; CHECK-GI-NEXT: cset w15, hs
+; CHECK-GI-NEXT: adds x9, x9, x0
+; CHECK-GI-NEXT: umulh x5, x24, xzr
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: cmn x9, x17
+; CHECK-GI-NEXT: and x9, x12, #0x1
+; CHECK-GI-NEXT: add x9, x9, x10
+; CHECK-GI-NEXT: and x10, x11, #0x1
+; CHECK-GI-NEXT: umulh x21, x25, x14
+; CHECK-GI-NEXT: add x9, x9, x10
; CHECK-GI-NEXT: cset w10, hs
-; CHECK-GI-NEXT: adds x19, x12, x8
-; CHECK-GI-NEXT: cset w12, hs
+; CHECK-GI-NEXT: and x12, x0, #0x1
+; CHECK-GI-NEXT: mul x8, x25, x16
; CHECK-GI-NEXT: and x10, x10, #0x1
-; CHECK-GI-NEXT: umulh x4, x2, xzr
-; CHECK-GI-NEXT: and x12, x12, #0x1
-; CHECK-GI-NEXT: adds x11, x14, x11
-; CHECK-GI-NEXT: cset w8, hs
-; CHECK-GI-NEXT: umulh x6, x24, xzr
-; CHECK-GI-NEXT: cmn x11, x9
-; CHECK-GI-NEXT: and x9, x23, #0x1
-; CHECK-GI-NEXT: and x11, x0, #0x1
-; CHECK-GI-NEXT: add x9, x9, x11
-; CHECK-GI-NEXT: ldp x23, x11, [sp, #96] // 16-byte Folded Reload
-; CHECK-GI-NEXT: umulh x0, x17, x16
-; CHECK-GI-NEXT: add x9, x9, x1
-; CHECK-GI-NEXT: ldr x1, [sp, #88] // 8-byte Reload
-; CHECK-GI-NEXT: and x8, x8, #0x1
-; CHECK-GI-NEXT: add x11, x11, x23
-; CHECK-GI-NEXT: umulh x23, x27, x18
-; CHECK-GI-NEXT: add x1, x30, x1
-; CHECK-GI-NEXT: add x11, x11, x3
-; CHECK-GI-NEXT: mul x3, x17, x18
-; CHECK-GI-NEXT: add x9, x11, x9
-; CHECK-GI-NEXT: add x11, x15, x13
-; CHECK-GI-NEXT: add x13, x1, x7
-; CHECK-GI-NEXT: and x1, x26, #0x1
-; CHECK-GI-NEXT: orr x9, x29, x9
-; CHECK-GI-NEXT: add x11, x13, x11
-; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: add x10, x1, x10
-; CHECK-GI-NEXT: adds x0, x0, x23
-; CHECK-GI-NEXT: and x13, x13, #0x1
-; CHECK-GI-NEXT: madd x14, x27, x18, x14
-; CHECK-GI-NEXT: add x8, x8, x13
+; CHECK-GI-NEXT: ldr x0, [sp, #88] // 8-byte Reload
+; CHECK-GI-NEXT: add x10, x12, x10
+; CHECK-GI-NEXT: adds x12, x13, x3
+; CHECK-GI-NEXT: and x15, x15, #0x1
+; CHECK-GI-NEXT: mul x11, x18, x14
+; CHECK-GI-NEXT: add x0, x20, x0
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: add x10, x10, x12
-; CHECK-GI-NEXT: adds x0, x0, x3
-; CHECK-GI-NEXT: umulh x15, x16, xzr
-; CHECK-GI-NEXT: and x13, x13, #0x1
+; CHECK-GI-NEXT: adds x12, x12, x7
+; CHECK-GI-NEXT: add x0, x0, x2
+; CHECK-GI-NEXT: cset w2, hs
+; CHECK-GI-NEXT: adds x20, x12, x10
+; CHECK-GI-NEXT: umulh x17, x18, x14
; CHECK-GI-NEXT: cset w12, hs
-; CHECK-GI-NEXT: adds x8, x0, x8
-; CHECK-GI-NEXT: ldr x0, [sp, #8] // 8-byte Reload
-; CHECK-GI-NEXT: umulh x7, x17, x18
+; CHECK-GI-NEXT: adds x8, x21, x8
+; CHECK-GI-NEXT: cset w10, hs
+; CHECK-GI-NEXT: umulh x3, x25, x16
; CHECK-GI-NEXT: and x12, x12, #0x1
-; CHECK-GI-NEXT: orr x11, x25, x11
-; CHECK-GI-NEXT: add x12, x13, x12
-; CHECK-GI-NEXT: cset w13, hs
+; CHECK-GI-NEXT: cmn x8, x11
+; CHECK-GI-NEXT: add x8, x0, x9
+; CHECK-GI-NEXT: and x9, x4, #0x1
+; CHECK-GI-NEXT: and x11, x1, #0x1
+; CHECK-GI-NEXT: mul x7, x18, x16
+; CHECK-GI-NEXT: and x10, x10, #0x1
+; CHECK-GI-NEXT: add x9, x9, x11
+; CHECK-GI-NEXT: ldp x0, x11, [sp, #72] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add x9, x9, x15
+; CHECK-GI-NEXT: umulh x4, x14, xzr
+; CHECK-GI-NEXT: add x11, x11, x0
+; CHECK-GI-NEXT: umulh x15, x18, x16
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: add x11, x11, x26
+; CHECK-GI-NEXT: and x0, x0, #0x1
+; CHECK-GI-NEXT: adds x17, x17, x3
+; CHECK-GI-NEXT: add x9, x11, x9
+; CHECK-GI-NEXT: and x11, x13, #0x1
+; CHECK-GI-NEXT: and x13, x2, #0x1
+; CHECK-GI-NEXT: add x11, x11, x13
+; CHECK-GI-NEXT: umulh x13, x25, xzr
+; CHECK-GI-NEXT: add x10, x10, x0
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: adds x17, x17, x7
+; CHECK-GI-NEXT: add x11, x11, x12
+; CHECK-GI-NEXT: ldr x12, [sp] // 8-byte Reload
+; CHECK-GI-NEXT: cset w1, hs
+; CHECK-GI-NEXT: adds x10, x17, x10
+; CHECK-GI-NEXT: and x0, x0, #0x1
+; CHECK-GI-NEXT: and x17, x1, #0x1
+; CHECK-GI-NEXT: cset w1, hs
+; CHECK-GI-NEXT: add x12, x19, x12
+; CHECK-GI-NEXT: add x17, x0, x17
+; CHECK-GI-NEXT: and x0, x1, #0x1
+; CHECK-GI-NEXT: add x15, x4, x15
+; CHECK-GI-NEXT: add x12, x12, x5
+; CHECK-GI-NEXT: add x17, x17, x0
+; CHECK-GI-NEXT: add x13, x15, x13
+; CHECK-GI-NEXT: add x11, x12, x11
+; CHECK-GI-NEXT: orr x9, x27, x9
+; CHECK-GI-NEXT: add x12, x13, x17
+; CHECK-GI-NEXT: ldr x13, [sp, #8] // 8-byte Reload
+; CHECK-GI-NEXT: madd x16, x25, x16, x21
+; CHECK-GI-NEXT: orr x11, x20, x11
+; CHECK-GI-NEXT: orr x10, x10, x12
+; CHECK-GI-NEXT: orr x8, x13, x8
+; CHECK-GI-NEXT: mul x19, x24, x28
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: ldr x8, [sp, #16] // 8-byte Reload
+; CHECK-GI-NEXT: madd x5, x6, x28, x29
+; CHECK-GI-NEXT: ldp x28, x27, [sp, #112] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x0, x8, x22, ne
+; CHECK-GI-NEXT: ldr x8, [sp, #48] // 8-byte Reload
+; CHECK-GI-NEXT: mul x15, x25, x14
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x1, x8, x30, ne
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: umulh x1, x27, xzr
-; CHECK-GI-NEXT: add x0, x4, x0
-; CHECK-GI-NEXT: and x13, x13, #0x1
-; CHECK-GI-NEXT: add x18, x0, x6
-; CHECK-GI-NEXT: add x12, x12, x13
-; CHECK-GI-NEXT: madd x9, x17, x16, x14
-; CHECK-GI-NEXT: ldr x14, [sp, #56] // 8-byte Reload
-; CHECK-GI-NEXT: add x10, x18, x10
-; CHECK-GI-NEXT: add x15, x15, x7
-; CHECK-GI-NEXT: orr x10, x19, x10
-; CHECK-GI-NEXT: csel x0, x14, x21, ne
-; CHECK-GI-NEXT: ldr x14, [sp, #72] // 8-byte Reload
-; CHECK-GI-NEXT: mul x20, x24, x2
-; CHECK-GI-NEXT: add x13, x15, x1
-; CHECK-GI-NEXT: ldp x26, x25, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x1, x14, x28, ne
+; CHECK-GI-NEXT: ldp x8, x9, [sp, #24] // 16-byte Folded Reload
+; CHECK-GI-NEXT: madd x13, x18, x14, x16
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #96] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x2, x8, x23, ne
+; CHECK-GI-NEXT: ldr x8, [sp, #40] // 8-byte Reload
+; CHECK-GI-NEXT: csel x3, x8, x9, ne
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: ldr x11, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: add x12, x13, x12
-; CHECK-GI-NEXT: mul x13, x27, x16
-; CHECK-GI-NEXT: ldr x14, [sp, #48] // 8-byte Reload
-; CHECK-GI-NEXT: csel x2, x11, x22, ne
-; CHECK-GI-NEXT: ldr x11, [sp, #64] // 8-byte Reload
-; CHECK-GI-NEXT: orr x8, x8, x12
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x3, x11, x14, ne
+; CHECK-GI-NEXT: csel x4, x19, x24, ne
+; CHECK-GI-NEXT: csel x5, x5, x6, ne
; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: ldr x10, [sp, #24] // 8-byte Reload
-; CHECK-GI-NEXT: csel x4, x20, x24, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #192] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x5, x10, x5, ne
-; CHECK-GI-NEXT: cmp x8, #0
-; CHECK-GI-NEXT: csel x6, x13, x27, ne
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #160] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x28, x27, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x7, x9, x17, ne
-; CHECK-GI-NEXT: ldp x29, x30, [sp, #112] // 16-byte Folded Reload
-; CHECK-GI-NEXT: add sp, sp, #208
+; CHECK-GI-NEXT: csel x6, x15, x25, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x7, x13, x18, ne
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x26, x25, [sp, #128] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #192
; CHECK-GI-NEXT: ret
%o = call {<4 x i128>, <4 x i1>} @llvm.umul.with.overflow(<4 x i128> %a, <4 x i128> %b)
%e0 = extractvalue {<4 x i128>, <4 x i1>} %o, 0
@@ -4525,14 +4527,14 @@ define <4 x i128> @umul_v4i128(<4 x i128> %a, <4 x i128> %b) {
define <4 x i128> @smul_v4i128(<4 x i128> %a, <4 x i128> %b) {
; CHECK-SD-LABEL: smul_v4i128:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sub sp, sp, #160
-; CHECK-SD-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x28, x27, [sp, #80] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x26, x25, [sp, #96] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x24, x23, [sp, #112] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x22, x21, [sp, #128] // 16-byte Folded Spill
-; CHECK-SD-NEXT: stp x20, x19, [sp, #144] // 16-byte Folded Spill
-; CHECK-SD-NEXT: .cfi_def_cfa_offset 160
+; CHECK-SD-NEXT: sub sp, sp, #176
+; CHECK-SD-NEXT: stp x29, x30, [sp, #80] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x28, x27, [sp, #96] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x26, x25, [sp, #112] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x24, x23, [sp, #128] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 176
; CHECK-SD-NEXT: .cfi_offset w19, -8
; CHECK-SD-NEXT: .cfi_offset w20, -16
; CHECK-SD-NEXT: .cfi_offset w21, -24
@@ -4545,168 +4547,169 @@ define <4 x i128> @smul_v4i128(<4 x i128> %a, <4 x i128> %b) {
; CHECK-SD-NEXT: .cfi_offset w28, -80
; CHECK-SD-NEXT: .cfi_offset w30, -88
; CHECK-SD-NEXT: .cfi_offset w29, -96
-; CHECK-SD-NEXT: mov x19, x7
-; CHECK-SD-NEXT: ldp x23, x20, [sp, #200]
-; CHECK-SD-NEXT: asr x9, x19, #63
-; CHECK-SD-NEXT: mov x7, x6
-; CHECK-SD-NEXT: mov x6, x5
-; CHECK-SD-NEXT: ldp x26, x17, [sp, #184]
-; CHECK-SD-NEXT: mov x5, x4
-; CHECK-SD-NEXT: mul x21, x9, x20
-; CHECK-SD-NEXT: ldr x9, [sp, #216]
-; CHECK-SD-NEXT: mov x4, x3
-; CHECK-SD-NEXT: mov x3, x2
-; CHECK-SD-NEXT: mov x2, x1
-; CHECK-SD-NEXT: mov x1, x0
-; CHECK-SD-NEXT: mul x8, x19, x9
-; CHECK-SD-NEXT: asr x10, x9, #63
-; CHECK-SD-NEXT: asr x25, x4, #63
-; CHECK-SD-NEXT: ldr x14, [sp, #176]
-; CHECK-SD-NEXT: asr x28, x26, #63
-; CHECK-SD-NEXT: mul x15, x7, x10
-; CHECK-SD-NEXT: asr x10, x6, #63
-; CHECK-SD-NEXT: umulh x13, x7, x9
-; CHECK-SD-NEXT: str x8, [sp, #48] // 8-byte Spill
-; CHECK-SD-NEXT: mul x8, x10, x17
-; CHECK-SD-NEXT: asr x10, x23, #63
-; CHECK-SD-NEXT: mul x18, x7, x9
-; CHECK-SD-NEXT: smulh x30, x19, x9
-; CHECK-SD-NEXT: str x8, [sp, #56] // 8-byte Spill
-; CHECK-SD-NEXT: umulh x9, x5, x23
-; CHECK-SD-NEXT: smulh x8, x6, x23
-; CHECK-SD-NEXT: umulh x11, x7, x20
-; CHECK-SD-NEXT: umulh x0, x19, x20
-; CHECK-SD-NEXT: stp x9, x8, [sp, #32] // 16-byte Folded Spill
-; CHECK-SD-NEXT: mul x9, x6, x23
-; CHECK-SD-NEXT: umulh x8, x3, x26
-; CHECK-SD-NEXT: mul x27, x25, x14
-; CHECK-SD-NEXT: umulh x12, x5, x17
-; CHECK-SD-NEXT: stp x8, x9, [sp, #16] // 16-byte Folded Spill
-; CHECK-SD-NEXT: smulh x8, x4, x26
-; CHECK-SD-NEXT: mul x22, x5, x10
-; CHECK-SD-NEXT: umulh x16, x6, x17
-; CHECK-SD-NEXT: str x8, [sp, #8] // 8-byte Spill
-; CHECK-SD-NEXT: mul x8, x19, x20
-; CHECK-SD-NEXT: mul x24, x5, x23
-; CHECK-SD-NEXT: mul x29, x3, x26
-; CHECK-SD-NEXT: adds x9, x8, x11
-; CHECK-SD-NEXT: adc x8, x0, x21
-; CHECK-SD-NEXT: adds x25, x18, x9
-; CHECK-SD-NEXT: mul x11, x6, x17
-; CHECK-SD-NEXT: adc x9, x13, x15
-; CHECK-SD-NEXT: asr x13, x8, #63
+; CHECK-SD-NEXT: mov x21, x7
+; CHECK-SD-NEXT: ldp x23, x10, [sp, #224]
+; CHECK-SD-NEXT: asr x9, x21, #63
+; CHECK-SD-NEXT: mov x20, x6
+; CHECK-SD-NEXT: mov x19, x5
+; CHECK-SD-NEXT: mov x7, x4
+; CHECK-SD-NEXT: mov x4, x2
+; CHECK-SD-NEXT: mov x2, x0
+; CHECK-SD-NEXT: ldp x0, x15, [sp, #208]
+; CHECK-SD-NEXT: mul x16, x9, x23
+; CHECK-SD-NEXT: asr x9, x10, #63
+; CHECK-SD-NEXT: mov x5, x3
+; CHECK-SD-NEXT: asr x11, x1, #63
+; CHECK-SD-NEXT: umulh x17, x6, x10
+; CHECK-SD-NEXT: ldp x18, x28, [sp, #192]
+; CHECK-SD-NEXT: mov x3, x1
+; CHECK-SD-NEXT: mul x26, x20, x10
+; CHECK-SD-NEXT: smulh x22, x21, x10
+; CHECK-SD-NEXT: mul x25, x21, x10
+; CHECK-SD-NEXT: asr x10, x19, #63
+; CHECK-SD-NEXT: mul x6, x6, x9
+; CHECK-SD-NEXT: mul x9, x10, x0
+; CHECK-SD-NEXT: asr x10, x15, #63
+; CHECK-SD-NEXT: umulh x8, x7, x15
+; CHECK-SD-NEXT: umulh x13, x7, x0
+; CHECK-SD-NEXT: mul x12, x19, x0
+; CHECK-SD-NEXT: stp x8, x9, [sp, #64] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mul x9, x7, x10
+; CHECK-SD-NEXT: smulh x8, x19, x15
+; CHECK-SD-NEXT: mul x10, x7, x15
+; CHECK-SD-NEXT: umulh x14, x19, x0
+; CHECK-SD-NEXT: stp x9, x8, [sp, #48] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mul x8, x19, x15
+; CHECK-SD-NEXT: asr x15, x5, #63
+; CHECK-SD-NEXT: mul x9, x15, x18
+; CHECK-SD-NEXT: asr x15, x28, #63
+; CHECK-SD-NEXT: mul x29, x4, x15
+; CHECK-SD-NEXT: ldp x15, x24, [sp, #176]
+; CHECK-SD-NEXT: stp x10, x8, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: umulh x8, x4, x28
+; CHECK-SD-NEXT: umulh x1, x5, x18
+; CHECK-SD-NEXT: mul x30, x4, x28
+; CHECK-SD-NEXT: stp x8, x9, [sp, #8] // 16-byte Folded Spill
+; CHECK-SD-NEXT: smulh x8, x5, x28
+; CHECK-SD-NEXT: umulh x9, x20, x23
+; CHECK-SD-NEXT: mul x28, x5, x28
+; CHECK-SD-NEXT: str x8, [sp, #24] // 8-byte Spill
+; CHECK-SD-NEXT: mul x8, x11, x15
+; CHECK-SD-NEXT: asr x11, x24, #63
+; CHECK-SD-NEXT: mul x27, x2, x11
+; CHECK-SD-NEXT: umulh x11, x21, x23
+; CHECK-SD-NEXT: str x8, [sp] // 8-byte Spill
+; CHECK-SD-NEXT: mul x8, x21, x23
+; CHECK-SD-NEXT: adds x9, x8, x9
+; CHECK-SD-NEXT: adc x8, x11, x16
+; CHECK-SD-NEXT: adds x26, x26, x9
+; CHECK-SD-NEXT: mul x16, x5, x18
+; CHECK-SD-NEXT: adc x9, x17, x6
+; CHECK-SD-NEXT: asr x11, x8, #63
; CHECK-SD-NEXT: asr x10, x9, #63
; CHECK-SD-NEXT: adds x8, x8, x9
+; CHECK-SD-NEXT: ldr x9, [sp, #72] // 8-byte Reload
+; CHECK-SD-NEXT: umulh x17, x4, x18
+; CHECK-SD-NEXT: adc x10, x11, x10
+; CHECK-SD-NEXT: adds x6, x25, x8
+; CHECK-SD-NEXT: adc x11, x22, x10
+; CHECK-SD-NEXT: adds x8, x12, x13
+; CHECK-SD-NEXT: umulh x10, x2, x15
+; CHECK-SD-NEXT: adc x13, x14, x9
+; CHECK-SD-NEXT: ldr x9, [sp, #32] // 8-byte Reload
+; CHECK-SD-NEXT: umulh x12, x3, x15
+; CHECK-SD-NEXT: adds x22, x9, x8
+; CHECK-SD-NEXT: ldr x8, [sp, #64] // 8-byte Reload
; CHECK-SD-NEXT: ldr x9, [sp, #48] // 8-byte Reload
-; CHECK-SD-NEXT: umulh x18, x3, x14
-; CHECK-SD-NEXT: adc x10, x13, x10
-; CHECK-SD-NEXT: adds x8, x9, x8
-; CHECK-SD-NEXT: ldr x13, [sp, #160]
-; CHECK-SD-NEXT: str x8, [sp, #48] // 8-byte Spill
-; CHECK-SD-NEXT: ldr x8, [sp, #56] // 8-byte Reload
-; CHECK-SD-NEXT: adc x23, x30, x10
-; CHECK-SD-NEXT: adds x10, x11, x12
-; CHECK-SD-NEXT: mul x15, x4, x14
-; CHECK-SD-NEXT: asr x11, x2, #63
-; CHECK-SD-NEXT: adc x16, x16, x8
-; CHECK-SD-NEXT: ldp x9, x8, [sp, #24] // 16-byte Folded Reload
-; CHECK-SD-NEXT: adds x21, x24, x10
-; CHECK-SD-NEXT: umulh x0, x4, x14
-; CHECK-SD-NEXT: asr x24, x16, #63
-; CHECK-SD-NEXT: ldr x10, [sp, #40] // 8-byte Reload
-; CHECK-SD-NEXT: adc x22, x8, x22
-; CHECK-SD-NEXT: mul x28, x3, x28
-; CHECK-SD-NEXT: asr x8, x22, #63
-; CHECK-SD-NEXT: adds x16, x16, x22
-; CHECK-SD-NEXT: mul x26, x4, x26
-; CHECK-SD-NEXT: adc x8, x24, x8
-; CHECK-SD-NEXT: adds x30, x9, x16
-; CHECK-SD-NEXT: ldr x24, [sp, #168]
-; CHECK-SD-NEXT: adc x16, x10, x8
-; CHECK-SD-NEXT: adds x8, x15, x18
-; CHECK-SD-NEXT: umulh x22, x1, x13
-; CHECK-SD-NEXT: adc x15, x0, x27
-; CHECK-SD-NEXT: adds x10, x29, x8
+; CHECK-SD-NEXT: mul x18, x4, x18
+; CHECK-SD-NEXT: adc x14, x8, x9
+; CHECK-SD-NEXT: asr x9, x13, #63
+; CHECK-SD-NEXT: asr x8, x14, #63
+; CHECK-SD-NEXT: adds x13, x13, x14
+; CHECK-SD-NEXT: mul x14, x3, x15
+; CHECK-SD-NEXT: adc x8, x9, x8
+; CHECK-SD-NEXT: ldr x9, [sp, #40] // 8-byte Reload
+; CHECK-SD-NEXT: mul x15, x2, x15
+; CHECK-SD-NEXT: adds x25, x9, x13
+; CHECK-SD-NEXT: ldr x9, [sp, #56] // 8-byte Reload
+; CHECK-SD-NEXT: adc x9, x9, x8
; CHECK-SD-NEXT: ldr x8, [sp, #16] // 8-byte Reload
-; CHECK-SD-NEXT: mul x9, x2, x13
-; CHECK-SD-NEXT: asr x0, x15, #63
-; CHECK-SD-NEXT: asr x29, x24, #63
-; CHECK-SD-NEXT: adc x27, x8, x28
-; CHECK-SD-NEXT: umulh x12, x2, x13
-; CHECK-SD-NEXT: asr x28, x27, #63
-; CHECK-SD-NEXT: adds x15, x15, x27
-; CHECK-SD-NEXT: ldr x27, [sp, #8] // 8-byte Reload
-; CHECK-SD-NEXT: mul x11, x11, x13
-; CHECK-SD-NEXT: adc x0, x0, x28
-; CHECK-SD-NEXT: adds x15, x26, x15
-; CHECK-SD-NEXT: adc x0, x27, x0
-; CHECK-SD-NEXT: asr x27, x25, #63
-; CHECK-SD-NEXT: adds x9, x9, x22
-; CHECK-SD-NEXT: mul x8, x1, x24
-; CHECK-SD-NEXT: umulh x18, x1, x24
-; CHECK-SD-NEXT: adc x11, x12, x11
-; CHECK-SD-NEXT: eor x12, x23, x27
-; CHECK-SD-NEXT: ldr x23, [sp, #48] // 8-byte Reload
-; CHECK-SD-NEXT: mul x26, x1, x29
-; CHECK-SD-NEXT: adds x8, x8, x9
-; CHECK-SD-NEXT: eor x23, x23, x27
-; CHECK-SD-NEXT: mul x9, x2, x24
-; CHECK-SD-NEXT: orr x12, x23, x12
-; CHECK-SD-NEXT: asr x23, x10, #63
-; CHECK-SD-NEXT: smulh x22, x2, x24
-; CHECK-SD-NEXT: asr x24, x21, #63
-; CHECK-SD-NEXT: eor x0, x0, x23
-; CHECK-SD-NEXT: adc x18, x18, x26
-; CHECK-SD-NEXT: asr x26, x11, #63
-; CHECK-SD-NEXT: asr x27, x18, #63
-; CHECK-SD-NEXT: adds x11, x11, x18
-; CHECK-SD-NEXT: mul x13, x1, x13
-; CHECK-SD-NEXT: eor x16, x16, x24
-; CHECK-SD-NEXT: eor x24, x30, x24
-; CHECK-SD-NEXT: adc x18, x26, x27
-; CHECK-SD-NEXT: adds x9, x9, x11
-; CHECK-SD-NEXT: asr x11, x8, #63
-; CHECK-SD-NEXT: adc x18, x22, x18
-; CHECK-SD-NEXT: mul x14, x3, x14
-; CHECK-SD-NEXT: orr x16, x24, x16
-; CHECK-SD-NEXT: eor x18, x18, x11
-; CHECK-SD-NEXT: eor x9, x9, x11
-; CHECK-SD-NEXT: eor x11, x15, x23
-; CHECK-SD-NEXT: mul x17, x5, x17
-; CHECK-SD-NEXT: orr x9, x9, x18
-; CHECK-SD-NEXT: orr x11, x11, x0
+; CHECK-SD-NEXT: adds x13, x16, x17
+; CHECK-SD-NEXT: umulh x16, x2, x24
+; CHECK-SD-NEXT: adc x17, x1, x8
+; CHECK-SD-NEXT: ldr x8, [sp, #8] // 8-byte Reload
+; CHECK-SD-NEXT: adds x13, x30, x13
+; CHECK-SD-NEXT: asr x30, x17, #63
+; CHECK-SD-NEXT: adc x1, x8, x29
+; CHECK-SD-NEXT: mul x29, x2, x24
+; CHECK-SD-NEXT: asr x8, x1, #63
+; CHECK-SD-NEXT: adds x17, x17, x1
+; CHECK-SD-NEXT: smulh x1, x3, x24
+; CHECK-SD-NEXT: adc x8, x30, x8
+; CHECK-SD-NEXT: adds x17, x28, x17
+; CHECK-SD-NEXT: ldr x28, [sp, #24] // 8-byte Reload
+; CHECK-SD-NEXT: asr x30, x26, #63
+; CHECK-SD-NEXT: adc x8, x28, x8
+; CHECK-SD-NEXT: adds x10, x14, x10
+; CHECK-SD-NEXT: mul x14, x3, x24
+; CHECK-SD-NEXT: ldr x24, [sp] // 8-byte Reload
+; CHECK-SD-NEXT: eor x11, x11, x30
+; CHECK-SD-NEXT: eor x6, x6, x30
+; CHECK-SD-NEXT: orr x11, x6, x11
+; CHECK-SD-NEXT: adc x12, x12, x24
+; CHECK-SD-NEXT: adds x10, x29, x10
+; CHECK-SD-NEXT: mul x24, x7, x0
+; CHECK-SD-NEXT: adc x16, x16, x27
+; CHECK-SD-NEXT: asr x0, x22, #63
+; CHECK-SD-NEXT: asr x27, x12, #63
+; CHECK-SD-NEXT: asr x28, x16, #63
+; CHECK-SD-NEXT: adds x12, x12, x16
+; CHECK-SD-NEXT: eor x9, x9, x0
+; CHECK-SD-NEXT: eor x16, x25, x0
+; CHECK-SD-NEXT: adc x0, x27, x28
+; CHECK-SD-NEXT: adds x12, x14, x12
+; CHECK-SD-NEXT: asr x14, x10, #63
+; CHECK-SD-NEXT: orr x9, x16, x9
+; CHECK-SD-NEXT: asr x16, x13, #63
+; CHECK-SD-NEXT: adc x0, x1, x0
+; CHECK-SD-NEXT: eor x0, x0, x14
+; CHECK-SD-NEXT: eor x12, x12, x14
+; CHECK-SD-NEXT: mul x14, x20, x23
+; CHECK-SD-NEXT: eor x8, x8, x16
+; CHECK-SD-NEXT: eor x16, x17, x16
+; CHECK-SD-NEXT: orr x12, x12, x0
+; CHECK-SD-NEXT: orr x8, x16, x8
+; CHECK-SD-NEXT: cmp x12, #0
+; CHECK-SD-NEXT: csel x0, x15, x2, ne
+; CHECK-SD-NEXT: csel x1, x10, x3, ne
+; CHECK-SD-NEXT: cmp x8, #0
+; CHECK-SD-NEXT: csel x2, x18, x4, ne
+; CHECK-SD-NEXT: csel x3, x13, x5, ne
; CHECK-SD-NEXT: cmp x9, #0
-; CHECK-SD-NEXT: ldp x24, x23, [sp, #112] // 16-byte Folded Reload
-; CHECK-SD-NEXT: mul x15, x7, x20
-; CHECK-SD-NEXT: csel x0, x13, x1, ne
-; CHECK-SD-NEXT: csel x1, x8, x2, ne
+; CHECK-SD-NEXT: csel x4, x24, x7, ne
+; CHECK-SD-NEXT: csel x5, x22, x19, ne
; CHECK-SD-NEXT: cmp x11, #0
-; CHECK-SD-NEXT: ldp x28, x27, [sp, #80] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x2, x14, x3, ne
-; CHECK-SD-NEXT: csel x3, x10, x4, ne
-; CHECK-SD-NEXT: cmp x16, #0
-; CHECK-SD-NEXT: csel x4, x17, x5, ne
-; CHECK-SD-NEXT: csel x5, x21, x6, ne
-; CHECK-SD-NEXT: cmp x12, #0
-; CHECK-SD-NEXT: ldp x22, x21, [sp, #128] // 16-byte Folded Reload
-; CHECK-SD-NEXT: csel x6, x15, x7, ne
-; CHECK-SD-NEXT: csel x7, x25, x19, ne
-; CHECK-SD-NEXT: ldp x20, x19, [sp, #144] // 16-byte Folded Reload
-; CHECK-SD-NEXT: ldp x26, x25, [sp, #96] // 16-byte Folded Reload
-; CHECK-SD-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-SD-NEXT: add sp, sp, #160
+; CHECK-SD-NEXT: csel x6, x14, x20, ne
+; CHECK-SD-NEXT: csel x7, x26, x21, ne
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x24, x23, [sp, #128] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x26, x25, [sp, #112] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x28, x27, [sp, #96] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ldp x29, x30, [sp, #80] // 16-byte Folded Reload
+; CHECK-SD-NEXT: add sp, sp, #176
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: smul_v4i128:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sub sp, sp, #224
-; CHECK-GI-NEXT: stp x29, x30, [sp, #128] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x28, x27, [sp, #144] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x26, x25, [sp, #160] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x24, x23, [sp, #176] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x22, x21, [sp, #192] // 16-byte Folded Spill
-; CHECK-GI-NEXT: stp x20, x19, [sp, #208] // 16-byte Folded Spill
-; CHECK-GI-NEXT: .cfi_def_cfa_offset 224
+; CHECK-GI-NEXT: sub sp, sp, #240
+; CHECK-GI-NEXT: stp x29, x30, [sp, #144] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x28, x27, [sp, #160] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x26, x25, [sp, #176] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x24, x23, [sp, #192] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #208] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #224] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 240
; CHECK-GI-NEXT: .cfi_offset w19, -8
; CHECK-GI-NEXT: .cfi_offset w20, -16
; CHECK-GI-NEXT: .cfi_offset w21, -24
@@ -4719,275 +4722,274 @@ define <4 x i128> @smul_v4i128(<4 x i128> %a, <4 x i128> %b) {
; CHECK-GI-NEXT: .cfi_offset w28, -80
; CHECK-GI-NEXT: .cfi_offset w30, -88
; CHECK-GI-NEXT: .cfi_offset w29, -96
-; CHECK-GI-NEXT: ldp x25, x8, [sp, #224]
+; CHECK-GI-NEXT: ldp x26, x8, [sp, #240]
; CHECK-GI-NEXT: asr x10, x1, #63
-; CHECK-GI-NEXT: mov x17, x5
-; CHECK-GI-NEXT: ldp x5, x19, [sp, #240]
-; CHECK-GI-NEXT: mov x18, x1
-; CHECK-GI-NEXT: asr x26, x17, #63
-; CHECK-GI-NEXT: mov x11, x6
+; CHECK-GI-NEXT: ldp x22, x18, [sp, #256]
+; CHECK-GI-NEXT: mov x16, x1
+; CHECK-GI-NEXT: asr x25, x5, #63
+; CHECK-GI-NEXT: str x2, [sp, #88] // 8-byte Spill
; CHECK-GI-NEXT: asr x12, x8, #63
-; CHECK-GI-NEXT: umulh x9, x10, x25
-; CHECK-GI-NEXT: asr x6, x7, #63
-; CHECK-GI-NEXT: asr x16, x19, #63
-; CHECK-GI-NEXT: str x2, [sp, #72] // 8-byte Spill
+; CHECK-GI-NEXT: umulh x9, x10, x26
+; CHECK-GI-NEXT: asr x20, x18, #63
; CHECK-GI-NEXT: umulh x13, x1, x8
-; CHECK-GI-NEXT: stp x18, x3, [sp, #8] // 16-byte Folded Spill
-; CHECK-GI-NEXT: str x0, [sp, #48] // 8-byte Spill
; CHECK-GI-NEXT: umulh x14, x0, x12
-; CHECK-GI-NEXT: umulh x20, x3, x19
+; CHECK-GI-NEXT: umulh x19, x3, x18
; CHECK-GI-NEXT: add x9, x9, x13
-; CHECK-GI-NEXT: asr x13, x3, #63
-; CHECK-GI-NEXT: umulh x22, x2, x16
+; CHECK-GI-NEXT: mul x13, x0, x12
; CHECK-GI-NEXT: add x9, x9, x14
; CHECK-GI-NEXT: madd x9, x0, x12, x9
-; CHECK-GI-NEXT: mul x14, x0, x12
+; CHECK-GI-NEXT: mul x14, x10, x26
+; CHECK-GI-NEXT: str x13, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: asr x13, x3, #63
; CHECK-GI-NEXT: madd x9, x1, x12, x9
-; CHECK-GI-NEXT: mul x12, x10, x25
-; CHECK-GI-NEXT: umulh x15, x13, x5
-; CHECK-GI-NEXT: umulh x21, x0, x25
-; CHECK-GI-NEXT: str x12, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: umulh x15, x13, x22
; CHECK-GI-NEXT: madd x12, x10, x8, x9
-; CHECK-GI-NEXT: madd x9, x10, x25, x12
-; CHECK-GI-NEXT: add x10, x15, x20
-; CHECK-GI-NEXT: add x10, x10, x22
-; CHECK-GI-NEXT: ldp x1, x22, [sp, #256]
-; CHECK-GI-NEXT: madd x15, x2, x16, x10
-; CHECK-GI-NEXT: asr x23, x22, #63
-; CHECK-GI-NEXT: umulh x20, x26, x1
-; CHECK-GI-NEXT: str x9, [sp, #120] // 8-byte Spill
-; CHECK-GI-NEXT: madd x15, x3, x16, x15
-; CHECK-GI-NEXT: mul x9, x2, x16
-; CHECK-GI-NEXT: umulh x24, x17, x22
+; CHECK-GI-NEXT: umulh x21, x2, x20
+; CHECK-GI-NEXT: madd x9, x10, x26, x12
+; CHECK-GI-NEXT: add x10, x15, x19
+; CHECK-GI-NEXT: ldp x1, x19, [sp, #272]
+; CHECK-GI-NEXT: umulh x17, x0, x26
+; CHECK-GI-NEXT: add x10, x10, x21
+; CHECK-GI-NEXT: madd x15, x2, x20, x10
+; CHECK-GI-NEXT: asr x23, x19, #63
+; CHECK-GI-NEXT: stp x14, x9, [sp, #128] // 16-byte Folded Spill
+; CHECK-GI-NEXT: mul x9, x2, x20
+; CHECK-GI-NEXT: mov x12, x17
+; CHECK-GI-NEXT: madd x15, x3, x20, x15
+; CHECK-GI-NEXT: umulh x21, x25, x1
+; CHECK-GI-NEXT: str x9, [sp, #96] // 8-byte Spill
+; CHECK-GI-NEXT: umulh x24, x5, x19
+; CHECK-GI-NEXT: mul x9, x13, x22
; CHECK-GI-NEXT: umulh x27, x4, x23
-; CHECK-GI-NEXT: stp x9, x14, [sp, #80] // 16-byte Folded Spill
-; CHECK-GI-NEXT: madd x15, x13, x19, x15
-; CHECK-GI-NEXT: add x16, x20, x24
-; CHECK-GI-NEXT: mov x24, x17
-; CHECK-GI-NEXT: mov x20, x4
-; CHECK-GI-NEXT: mul x10, x13, x5
-; CHECK-GI-NEXT: add x16, x16, x27
-; CHECK-GI-NEXT: madd x9, x13, x5, x15
-; CHECK-GI-NEXT: madd x16, x4, x23, x16
-; CHECK-GI-NEXT: mul x15, x2, x19
+; CHECK-GI-NEXT: add x20, x21, x24
+; CHECK-GI-NEXT: mov x24, x5
+; CHECK-GI-NEXT: madd x15, x13, x18, x15
+; CHECK-GI-NEXT: str x9, [sp, #64] // 8-byte Spill
+; CHECK-GI-NEXT: mul x10, x0, x8
+; CHECK-GI-NEXT: add x20, x20, x27
+; CHECK-GI-NEXT: madd x9, x13, x22, x15
+; CHECK-GI-NEXT: madd x20, x4, x23, x20
+; CHECK-GI-NEXT: adds x10, x12, x10
+; CHECK-GI-NEXT: umulh x14, x0, x8
; CHECK-GI-NEXT: str x9, [sp, #104] // 8-byte Spill
-; CHECK-GI-NEXT: madd x16, x17, x23, x16
+; CHECK-GI-NEXT: madd x21, x5, x23, x20
+; CHECK-GI-NEXT: asr x20, x7, #63
+; CHECK-GI-NEXT: mov x5, x4
; CHECK-GI-NEXT: mul x9, x4, x23
-; CHECK-GI-NEXT: ldp x14, x23, [sp, #272]
-; CHECK-GI-NEXT: madd x13, x26, x22, x16
-; CHECK-GI-NEXT: ldr x16, [sp, #88] // 8-byte Reload
-; CHECK-GI-NEXT: asr x29, x23, #63
-; CHECK-GI-NEXT: umulh x27, x6, x14
-; CHECK-GI-NEXT: stp x10, x9, [sp, #56] // 16-byte Folded Spill
-; CHECK-GI-NEXT: umulh x28, x7, x23
-; CHECK-GI-NEXT: umulh x30, x11, x29
-; CHECK-GI-NEXT: madd x9, x26, x1, x13
-; CHECK-GI-NEXT: add x27, x27, x28
-; CHECK-GI-NEXT: mul x10, x0, x8
+; CHECK-GI-NEXT: ldp x15, x23, [sp, #288]
+; CHECK-GI-NEXT: madd x13, x25, x19, x21
+; CHECK-GI-NEXT: mov x21, x7
+; CHECK-GI-NEXT: asr x28, x23, #63
+; CHECK-GI-NEXT: umulh x27, x20, x15
+; CHECK-GI-NEXT: str x9, [sp, #80] // 8-byte Spill
+; CHECK-GI-NEXT: umulh x29, x7, x23
+; CHECK-GI-NEXT: umulh x30, x6, x28
+; CHECK-GI-NEXT: madd x9, x25, x1, x13
+; CHECK-GI-NEXT: add x27, x27, x29
+; CHECK-GI-NEXT: umulh x11, x2, x22
; CHECK-GI-NEXT: add x27, x27, x30
-; CHECK-GI-NEXT: madd x27, x11, x29, x27
-; CHECK-GI-NEXT: str x9, [sp, #96] // 8-byte Spill
-; CHECK-GI-NEXT: umulh x13, x0, x8
-; CHECK-GI-NEXT: adds x10, x21, x10
-; CHECK-GI-NEXT: madd x30, x7, x29, x27
-; CHECK-GI-NEXT: mul x9, x11, x29
-; CHECK-GI-NEXT: mul x29, x18, x8
-; CHECK-GI-NEXT: madd x8, x0, x8, x21
-; CHECK-GI-NEXT: mul x28, x26, x1
-; CHECK-GI-NEXT: mov x26, x7
-; CHECK-GI-NEXT: mov x7, x11
-; CHECK-GI-NEXT: umulh x11, x2, x5
-; CHECK-GI-NEXT: stp x8, x9, [sp, #24] // 16-byte Folded Spill
-; CHECK-GI-NEXT: mov x8, x2
+; CHECK-GI-NEXT: madd x27, x6, x28, x27
+; CHECK-GI-NEXT: str x9, [sp, #120] // 8-byte Spill
+; CHECK-GI-NEXT: mul x9, x6, x28
+; CHECK-GI-NEXT: madd x27, x7, x28, x27
+; CHECK-GI-NEXT: mul x30, x16, x8
+; CHECK-GI-NEXT: str x9, [sp, #72] // 8-byte Spill
+; CHECK-GI-NEXT: madd x8, x0, x8, x17
+; CHECK-GI-NEXT: madd x9, x20, x23, x27
+; CHECK-GI-NEXT: umulh x17, x2, x18
+; CHECK-GI-NEXT: stp x8, x0, [sp, #40] // 16-byte Folded Spill
+; CHECK-GI-NEXT: madd x8, x2, x18, x11
+; CHECK-GI-NEXT: stp x9, x3, [sp, #24] // 16-byte Folded Spill
+; CHECK-GI-NEXT: mov x9, x16
+; CHECK-GI-NEXT: mul x16, x2, x18
+; CHECK-GI-NEXT: str x9, [sp, #16] // 8-byte Spill
+; CHECK-GI-NEXT: mul x0, x3, x18
+; CHECK-GI-NEXT: str x8, [sp, #56] // 8-byte Spill
+; CHECK-GI-NEXT: mul x18, x9, x26
+; CHECK-GI-NEXT: umulh x8, x9, x26
; CHECK-GI-NEXT: cset w9, hs
-; CHECK-GI-NEXT: umulh x17, x2, x19
; CHECK-GI-NEXT: and x9, x9, #0x1
-; CHECK-GI-NEXT: madd x8, x8, x19, x11
-; CHECK-GI-NEXT: mul x2, x3, x19
-; CHECK-GI-NEXT: mul x19, x18, x25
-; CHECK-GI-NEXT: str x8, [sp, #40] // 8-byte Spill
-; CHECK-GI-NEXT: umulh x8, x18, x25
-; CHECK-GI-NEXT: ldr x18, [sp, #112] // 8-byte Reload
-; CHECK-GI-NEXT: mul x12, x3, x5
-; CHECK-GI-NEXT: cmn x10, x19
-; CHECK-GI-NEXT: cset w10, hs
-; CHECK-GI-NEXT: umulh x21, x3, x5
-; CHECK-GI-NEXT: adds x8, x8, x13
-; CHECK-GI-NEXT: and x10, x10, #0x1
-; CHECK-GI-NEXT: cset w19, hs
-; CHECK-GI-NEXT: adds x8, x8, x16
-; CHECK-GI-NEXT: add x9, x9, x10
-; CHECK-GI-NEXT: cset w10, hs
-; CHECK-GI-NEXT: adds x8, x8, x29
-; CHECK-GI-NEXT: umulh x13, x4, x1
-; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: mul x13, x3, x22
+; CHECK-GI-NEXT: cmn x10, x18
+; CHECK-GI-NEXT: ldr x10, [sp, #112] // 8-byte Reload
+; CHECK-GI-NEXT: cset w18, hs
+; CHECK-GI-NEXT: umulh x12, x3, x22
+; CHECK-GI-NEXT: adds x8, x8, x14
+; CHECK-GI-NEXT: and x18, x18, #0x1
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x8, x8, x10
+; CHECK-GI-NEXT: add x9, x9, x18
+; CHECK-GI-NEXT: ldr x18, [sp, #128] // 8-byte Reload
+; CHECK-GI-NEXT: cset w2, hs
+; CHECK-GI-NEXT: adds x8, x8, x30
+; CHECK-GI-NEXT: cset w7, hs
+; CHECK-GI-NEXT: mul x29, x25, x1
+; CHECK-GI-NEXT: and x2, x2, #0x1
; CHECK-GI-NEXT: adds x8, x8, x18
-; CHECK-GI-NEXT: and x10, x10, #0x1
-; CHECK-GI-NEXT: mul x16, x4, x22
-; CHECK-GI-NEXT: and x0, x0, #0x1
-; CHECK-GI-NEXT: umulh x18, x4, x22
-; CHECK-GI-NEXT: cset w4, hs
+; CHECK-GI-NEXT: cset w25, hs
; CHECK-GI-NEXT: adds x8, x8, x9
-; CHECK-GI-NEXT: str x8, [sp, #112] // 8-byte Spill
-; CHECK-GI-NEXT: cset w29, hs
-; CHECK-GI-NEXT: adds x8, x11, x15
-; CHECK-GI-NEXT: cset w9, hs
-; CHECK-GI-NEXT: cmn x8, x12
-; CHECK-GI-NEXT: ldr x11, [sp, #80] // 8-byte Reload
-; CHECK-GI-NEXT: cset w8, hs
-; CHECK-GI-NEXT: adds x12, x21, x17
-; CHECK-GI-NEXT: and x9, x9, #0x1
+; CHECK-GI-NEXT: umulh x10, x4, x1
+; CHECK-GI-NEXT: cset w27, hs
+; CHECK-GI-NEXT: adds x11, x11, x16
+; CHECK-GI-NEXT: str x8, [sp, #128] // 8-byte Spill
+; CHECK-GI-NEXT: cset w16, hs
+; CHECK-GI-NEXT: cmn x11, x13
+; CHECK-GI-NEXT: ldr x8, [sp, #96] // 8-byte Reload
+; CHECK-GI-NEXT: mul x14, x4, x19
+; CHECK-GI-NEXT: cset w11, hs
+; CHECK-GI-NEXT: adds x12, x12, x17
+; CHECK-GI-NEXT: cset w18, hs
+; CHECK-GI-NEXT: adds x12, x12, x8
+; CHECK-GI-NEXT: and x16, x16, #0x1
+; CHECK-GI-NEXT: mul x9, x24, x1
; CHECK-GI-NEXT: cset w17, hs
-; CHECK-GI-NEXT: adds x12, x12, x11
-; CHECK-GI-NEXT: and x8, x8, #0x1
-; CHECK-GI-NEXT: mul x21, x24, x1
-; CHECK-GI-NEXT: ldr x11, [sp, #56] // 8-byte Reload
-; CHECK-GI-NEXT: add x8, x9, x8
-; CHECK-GI-NEXT: cset w9, hs
-; CHECK-GI-NEXT: adds x12, x12, x2
+; CHECK-GI-NEXT: adds x12, x12, x0
+; CHECK-GI-NEXT: and x11, x11, #0x1
+; CHECK-GI-NEXT: and x18, x18, #0x1
; CHECK-GI-NEXT: and x17, x17, #0x1
-; CHECK-GI-NEXT: mul x15, x24, x22
+; CHECK-GI-NEXT: umulh x8, x4, x19
+; CHECK-GI-NEXT: ldr x4, [sp, #64] // 8-byte Reload
+; CHECK-GI-NEXT: add x11, x16, x11
+; CHECK-GI-NEXT: cset w16, hs
+; CHECK-GI-NEXT: umulh x13, x24, x1
+; CHECK-GI-NEXT: adds x12, x12, x4
+; CHECK-GI-NEXT: and x16, x16, #0x1
+; CHECK-GI-NEXT: cset w4, hs
+; CHECK-GI-NEXT: adds x11, x12, x11
+; CHECK-GI-NEXT: mul x0, x24, x19
+; CHECK-GI-NEXT: str x11, [sp, #112] // 8-byte Spill
+; CHECK-GI-NEXT: ldr x11, [sp, #80] // 8-byte Reload
+; CHECK-GI-NEXT: madd x28, x5, x19, x10
+; CHECK-GI-NEXT: cset w19, hs
+; CHECK-GI-NEXT: adds x10, x10, x14
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: cmn x10, x9
+; CHECK-GI-NEXT: umulh x9, x6, x15
+; CHECK-GI-NEXT: cset w10, hs
+; CHECK-GI-NEXT: adds x8, x13, x8
+; CHECK-GI-NEXT: and x13, x3, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
+; CHECK-GI-NEXT: and x10, x10, #0x1
+; CHECK-GI-NEXT: mul x3, x6, x23
+; CHECK-GI-NEXT: add x13, x13, x2
; CHECK-GI-NEXT: cset w2, hs
-; CHECK-GI-NEXT: adds x12, x12, x11
-; CHECK-GI-NEXT: cset w3, hs
-; CHECK-GI-NEXT: adds x8, x12, x8
-; CHECK-GI-NEXT: and x9, x9, #0x1
-; CHECK-GI-NEXT: madd x27, x20, x22, x13
+; CHECK-GI-NEXT: adds x8, x8, x11
+; CHECK-GI-NEXT: add x10, x14, x10
+; CHECK-GI-NEXT: mul x11, x21, x15
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x8, x8, x0
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: adds x8, x8, x29
+; CHECK-GI-NEXT: and x14, x14, #0x1
; CHECK-GI-NEXT: cset w12, hs
-; CHECK-GI-NEXT: adds x13, x13, x16
-; CHECK-GI-NEXT: str x8, [sp, #88] // 8-byte Spill
-; CHECK-GI-NEXT: ldr x8, [sp, #64] // 8-byte Reload
-; CHECK-GI-NEXT: add x9, x17, x9
-; CHECK-GI-NEXT: umulh x22, x24, x1
-; CHECK-GI-NEXT: and x4, x4, #0x1
-; CHECK-GI-NEXT: and x2, x2, #0x1
-; CHECK-GI-NEXT: add x9, x9, x2
-; CHECK-GI-NEXT: and x2, x3, #0x1
-; CHECK-GI-NEXT: madd x16, x6, x23, x30
-; CHECK-GI-NEXT: cset w30, hs
-; CHECK-GI-NEXT: cmn x13, x21
-; CHECK-GI-NEXT: and x13, x19, #0x1
-; CHECK-GI-NEXT: mov x19, x26
-; CHECK-GI-NEXT: add x9, x9, x2
-; CHECK-GI-NEXT: umulh x21, x7, x14
-; CHECK-GI-NEXT: add x10, x13, x10
+; CHECK-GI-NEXT: adds x30, x8, x10
+; CHECK-GI-NEXT: and x8, x7, #0x1
+; CHECK-GI-NEXT: add x8, x13, x8
; CHECK-GI-NEXT: cset w13, hs
-; CHECK-GI-NEXT: adds x18, x22, x18
-; CHECK-GI-NEXT: add x11, x10, x0
+; CHECK-GI-NEXT: madd x10, x6, x23, x9
+; CHECK-GI-NEXT: adds x9, x9, x3
+; CHECK-GI-NEXT: and x3, x25, #0x1
+; CHECK-GI-NEXT: and x12, x12, #0x1
+; CHECK-GI-NEXT: umulh x29, x6, x23
+; CHECK-GI-NEXT: add x8, x8, x3
+; CHECK-GI-NEXT: ldr x3, [sp, #72] // 8-byte Reload
; CHECK-GI-NEXT: and x13, x13, #0x1
-; CHECK-GI-NEXT: mul x22, x7, x23
-; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x18, x18, x8
-; CHECK-GI-NEXT: cset w17, hs
-; CHECK-GI-NEXT: adds x15, x18, x15
-; CHECK-GI-NEXT: and x18, x30, #0x1
-; CHECK-GI-NEXT: mul x10, x26, x14
-; CHECK-GI-NEXT: add x13, x18, x13
-; CHECK-GI-NEXT: cset w18, hs
-; CHECK-GI-NEXT: adds x15, x15, x28
-; CHECK-GI-NEXT: and x17, x17, #0x1
-; CHECK-GI-NEXT: ldr x2, [sp, #32] // 8-byte Reload
-; CHECK-GI-NEXT: umulh x30, x26, x14
-; CHECK-GI-NEXT: cset w28, hs
-; CHECK-GI-NEXT: adds x26, x15, x13
-; CHECK-GI-NEXT: cset w15, hs
-; CHECK-GI-NEXT: and x18, x18, #0x1
-; CHECK-GI-NEXT: umulh x8, x7, x23
-; CHECK-GI-NEXT: and x15, x15, #0x1
-; CHECK-GI-NEXT: madd x13, x7, x23, x21
-; CHECK-GI-NEXT: adds x21, x21, x22
-; CHECK-GI-NEXT: cset w22, hs
-; CHECK-GI-NEXT: cmn x21, x10
-; CHECK-GI-NEXT: add x10, x11, x4
-; CHECK-GI-NEXT: and x11, x29, #0x1
-; CHECK-GI-NEXT: mul x3, x19, x23
-; CHECK-GI-NEXT: ldr x23, [sp, #8] // 8-byte Reload
-; CHECK-GI-NEXT: add x10, x10, x11
-; CHECK-GI-NEXT: and x11, x12, #0x1
-; CHECK-GI-NEXT: and x12, x0, #0x1
-; CHECK-GI-NEXT: ldr x0, [sp, #120] // 8-byte Reload
+; CHECK-GI-NEXT: mul x7, x21, x23
+; CHECK-GI-NEXT: cset w23, hs
+; CHECK-GI-NEXT: cmn x9, x11
+; CHECK-GI-NEXT: add x9, x18, x17
+; CHECK-GI-NEXT: and x11, x27, #0x1
+; CHECK-GI-NEXT: add x8, x8, x11
+; CHECK-GI-NEXT: add x9, x9, x16
+; CHECK-GI-NEXT: and x11, x4, #0x1
; CHECK-GI-NEXT: add x9, x9, x11
-; CHECK-GI-NEXT: add x11, x12, x17
-; CHECK-GI-NEXT: cset w12, hs
-; CHECK-GI-NEXT: adds x8, x30, x8
-; CHECK-GI-NEXT: mul x17, x6, x14
-; CHECK-GI-NEXT: add x10, x0, x10
-; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: adds x8, x8, x2
-; CHECK-GI-NEXT: cset w2, hs
-; CHECK-GI-NEXT: adds x8, x8, x3
-; CHECK-GI-NEXT: and x0, x0, #0x1
-; CHECK-GI-NEXT: and x2, x2, #0x1
-; CHECK-GI-NEXT: and x3, x22, #0x1
-; CHECK-GI-NEXT: and x12, x12, #0x1
-; CHECK-GI-NEXT: add x0, x0, x2
-; CHECK-GI-NEXT: cset w2, hs
-; CHECK-GI-NEXT: madd x16, x6, x14, x16
-; CHECK-GI-NEXT: adds x8, x8, x17
-; CHECK-GI-NEXT: and x17, x2, #0x1
-; CHECK-GI-NEXT: add x12, x3, x12
-; CHECK-GI-NEXT: add x17, x0, x17
+; CHECK-GI-NEXT: and x11, x19, #0x1
+; CHECK-GI-NEXT: umulh x17, x21, x15
+; CHECK-GI-NEXT: add x9, x9, x11
+; CHECK-GI-NEXT: and x11, x2, #0x1
+; CHECK-GI-NEXT: and x4, x23, #0x1
+; CHECK-GI-NEXT: add x11, x11, x14
+; CHECK-GI-NEXT: and x14, x0, #0x1
+; CHECK-GI-NEXT: ldr x0, [sp, #136] // 8-byte Reload
+; CHECK-GI-NEXT: ldp x27, x16, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mul x18, x20, x15
+; CHECK-GI-NEXT: add x8, x0, x8
+; CHECK-GI-NEXT: ldr x0, [sp, #104] // 8-byte Reload
+; CHECK-GI-NEXT: add x11, x11, x14
+; CHECK-GI-NEXT: cset w14, hs
+; CHECK-GI-NEXT: adds x17, x17, x29
+; CHECK-GI-NEXT: madd x16, x20, x15, x16
+; CHECK-GI-NEXT: add x9, x0, x9
+; CHECK-GI-NEXT: ldp x0, x25, [sp, #40] // 16-byte Folded Reload
+; CHECK-GI-NEXT: madd x2, x27, x26, x0
; CHECK-GI-NEXT: cset w0, hs
-; CHECK-GI-NEXT: add x11, x11, x18
-; CHECK-GI-NEXT: ldr x18, [sp, #24] // 8-byte Reload
-; CHECK-GI-NEXT: ldr x22, [sp, #16] // 8-byte Reload
-; CHECK-GI-NEXT: adds x8, x8, x12
-; CHECK-GI-NEXT: and x12, x28, #0x1
+; CHECK-GI-NEXT: adds x17, x17, x3
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: adds x17, x17, x7
; CHECK-GI-NEXT: and x0, x0, #0x1
-; CHECK-GI-NEXT: madd x18, x23, x25, x18
+; CHECK-GI-NEXT: and x3, x3, #0x1
+; CHECK-GI-NEXT: and x14, x14, #0x1
+; CHECK-GI-NEXT: ldr x23, [sp, #32] // 8-byte Reload
+; CHECK-GI-NEXT: add x0, x0, x3
+; CHECK-GI-NEXT: cset w3, hs
+; CHECK-GI-NEXT: add x14, x4, x14
+; CHECK-GI-NEXT: adds x17, x17, x18
+; CHECK-GI-NEXT: and x18, x3, #0x1
; CHECK-GI-NEXT: add x11, x11, x12
-; CHECK-GI-NEXT: add x12, x17, x0
-; CHECK-GI-NEXT: cset w17, hs
-; CHECK-GI-NEXT: ldr x2, [sp, #40] // 8-byte Reload
-; CHECK-GI-NEXT: madd x3, x22, x5, x2
-; CHECK-GI-NEXT: and x17, x17, #0x1
-; CHECK-GI-NEXT: ldr x21, [sp, #48] // 8-byte Reload
-; CHECK-GI-NEXT: add x11, x11, x15
-; CHECK-GI-NEXT: add x12, x12, x17
-; CHECK-GI-NEXT: madd x6, x24, x1, x27
-; CHECK-GI-NEXT: ldp x17, x15, [sp, #88] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldr x0, [sp, #104] // 8-byte Reload
-; CHECK-GI-NEXT: add x12, x16, x12
-; CHECK-GI-NEXT: ldr x2, [sp, #72] // 8-byte Reload
-; CHECK-GI-NEXT: madd x13, x19, x14, x13
-; CHECK-GI-NEXT: ldr x16, [sp, #112] // 8-byte Reload
-; CHECK-GI-NEXT: eor x10, x10, x18, asr #63
-; CHECK-GI-NEXT: add x9, x0, x9
-; CHECK-GI-NEXT: add x11, x15, x11
-; CHECK-GI-NEXT: eor x17, x17, x3, asr #63
-; CHECK-GI-NEXT: mul x4, x21, x25
-; CHECK-GI-NEXT: eor x16, x16, x18, asr #63
-; CHECK-GI-NEXT: eor x9, x9, x3, asr #63
-; CHECK-GI-NEXT: eor x0, x26, x6, asr #63
-; CHECK-GI-NEXT: eor x11, x11, x6, asr #63
-; CHECK-GI-NEXT: mul x15, x2, x5
-; CHECK-GI-NEXT: orr x10, x16, x10
-; CHECK-GI-NEXT: orr x9, x17, x9
-; CHECK-GI-NEXT: eor x8, x8, x13, asr #63
-; CHECK-GI-NEXT: eor x12, x12, x13, asr #63
-; CHECK-GI-NEXT: cmp x10, #0
-; CHECK-GI-NEXT: mul x5, x20, x1
-; CHECK-GI-NEXT: orr x11, x0, x11
-; CHECK-GI-NEXT: csel x1, x18, x23, ne
-; CHECK-GI-NEXT: csel x0, x4, x21, ne
+; CHECK-GI-NEXT: ldr x7, [sp, #56] // 8-byte Reload
+; CHECK-GI-NEXT: add x18, x0, x18
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: adds x14, x17, x14
+; CHECK-GI-NEXT: madd x20, x21, x15, x10
+; CHECK-GI-NEXT: ldr x10, [sp, #120] // 8-byte Reload
+; CHECK-GI-NEXT: and x17, x0, #0x1
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: add x11, x11, x13
+; CHECK-GI-NEXT: madd x7, x23, x22, x7
+; CHECK-GI-NEXT: add x17, x18, x17
+; CHECK-GI-NEXT: and x18, x0, #0x1
+; CHECK-GI-NEXT: add x11, x10, x11
+; CHECK-GI-NEXT: ldr x10, [sp, #128] // 8-byte Reload
+; CHECK-GI-NEXT: add x13, x17, x18
+; CHECK-GI-NEXT: madd x19, x24, x1, x28
+; CHECK-GI-NEXT: ldr x3, [sp, #88] // 8-byte Reload
+; CHECK-GI-NEXT: add x13, x16, x13
+; CHECK-GI-NEXT: eor x16, x10, x2, asr #63
+; CHECK-GI-NEXT: ldr x10, [sp, #112] // 8-byte Reload
+; CHECK-GI-NEXT: eor x8, x8, x2, asr #63
+; CHECK-GI-NEXT: mul x12, x25, x26
+; CHECK-GI-NEXT: eor x14, x14, x20, asr #63
+; CHECK-GI-NEXT: eor x13, x13, x20, asr #63
+; CHECK-GI-NEXT: eor x18, x10, x7, asr #63
+; CHECK-GI-NEXT: eor x9, x9, x7, asr #63
+; CHECK-GI-NEXT: orr x8, x16, x8
+; CHECK-GI-NEXT: mul x17, x3, x22
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: eor x10, x30, x19, asr #63
+; CHECK-GI-NEXT: eor x11, x11, x19, asr #63
+; CHECK-GI-NEXT: orr x9, x18, x9
+; CHECK-GI-NEXT: mul x4, x5, x1
+; CHECK-GI-NEXT: ldp x29, x30, [sp, #144] // 16-byte Folded Reload
+; CHECK-GI-NEXT: orr x10, x10, x11
+; CHECK-GI-NEXT: csel x0, x12, x25, ne
+; CHECK-GI-NEXT: csel x1, x2, x27, ne
+; CHECK-GI-NEXT: mul x15, x6, x15
; CHECK-GI-NEXT: cmp x9, #0
-; CHECK-GI-NEXT: orr x8, x8, x12
-; CHECK-GI-NEXT: mul x14, x7, x14
-; CHECK-GI-NEXT: csel x3, x3, x22, ne
-; CHECK-GI-NEXT: csel x2, x15, x2, ne
+; CHECK-GI-NEXT: orr x11, x14, x13
+; CHECK-GI-NEXT: csel x2, x17, x3, ne
+; CHECK-GI-NEXT: csel x3, x7, x23, ne
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: ldp x26, x25, [sp, #176] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x4, x4, x5, ne
+; CHECK-GI-NEXT: csel x5, x19, x24, ne
; CHECK-GI-NEXT: cmp x11, #0
-; CHECK-GI-NEXT: ldp x22, x21, [sp, #192] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x4, x5, x20, ne
-; CHECK-GI-NEXT: csel x5, x6, x24, ne
-; CHECK-GI-NEXT: cmp x8, #0
-; CHECK-GI-NEXT: ldp x24, x23, [sp, #176] // 16-byte Folded Reload
-; CHECK-GI-NEXT: csel x6, x14, x7, ne
-; CHECK-GI-NEXT: csel x7, x13, x19, ne
-; CHECK-GI-NEXT: ldp x20, x19, [sp, #208] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x26, x25, [sp, #160] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x28, x27, [sp, #144] // 16-byte Folded Reload
-; CHECK-GI-NEXT: ldp x29, x30, [sp, #128] // 16-byte Folded Reload
-; CHECK-GI-NEXT: add sp, sp, #224
+; CHECK-GI-NEXT: ldp x24, x23, [sp, #192] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x6, x15, x6, ne
+; CHECK-GI-NEXT: csel x7, x20, x21, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #224] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #208] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x28, x27, [sp, #160] // 16-byte Folded Reload
+; CHECK-GI-NEXT: add sp, sp, #240
; CHECK-GI-NEXT: ret
%o = call {<4 x i128>, <4 x i1>} @llvm.smul.with.overflow(<4 x i128> %a, <4 x i128> %b)
%e0 = extractvalue {<4 x i128>, <4 x i1>} %o, 0
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat.ll b/llvm/test/CodeGen/AArch64/sadd_sat.ll
index 290031ac50ea7..af42458c40b6a 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat.ll
@@ -63,11 +63,11 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sxth w8, w1
; CHECK-GI-NEXT: add w8, w8, w0, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -76,11 +76,11 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: func8:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sxtb w9, w0
-; CHECK-SD-NEXT: mov w8, #127 // =0x7f
-; CHECK-SD-NEXT: add w9, w9, w1, sxtb
-; CHECK-SD-NEXT: cmp w9, #127
-; CHECK-SD-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-NEXT: sxtb w8, w0
+; CHECK-SD-NEXT: mov w9, #127 // =0x7f
+; CHECK-SD-NEXT: add w8, w8, w1, sxtb
+; CHECK-SD-NEXT: cmp w8, #127
+; CHECK-SD-NEXT: csel w8, w8, w9, lt
; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-SD-NEXT: cmn w8, #128
; CHECK-SD-NEXT: csel w0, w8, w9, gt
@@ -90,11 +90,11 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sxtb w8, w1
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -103,12 +103,12 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-SD-LABEL: func3:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: lsl w9, w1, #28
-; CHECK-SD-NEXT: sbfx w10, w0, #0, #4
-; CHECK-SD-NEXT: mov w8, #7 // =0x7
-; CHECK-SD-NEXT: add w9, w10, w9, asr #28
-; CHECK-SD-NEXT: cmp w9, #7
-; CHECK-SD-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-NEXT: lsl w8, w1, #28
+; CHECK-SD-NEXT: sbfx w9, w0, #0, #4
+; CHECK-SD-NEXT: add w8, w9, w8, asr #28
+; CHECK-SD-NEXT: mov w9, #7 // =0x7
+; CHECK-SD-NEXT: cmp w8, #7
+; CHECK-SD-NEXT: csel w8, w8, w9, lt
; CHECK-SD-NEXT: mov w9, #-8 // =0xfffffff8
; CHECK-SD-NEXT: cmn w8, #8
; CHECK-SD-NEXT: csel w0, w8, w9, gt
@@ -121,8 +121,8 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-GI-NEXT: add w8, w8, w9
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
+; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll b/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
index 4a0e49518517b..967ccb9364f0a 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
@@ -75,11 +75,11 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxth w8, w8
; CHECK-GI-NEXT: add w8, w8, w0, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i16 %y, %z
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
@@ -105,11 +105,11 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxtb w8, w8
; CHECK-GI-NEXT: add w8, w8, w0, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i8 %y, %z
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
@@ -139,8 +139,8 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-GI-NEXT: add w8, w9, w8
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
+; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i4 %y, %z
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 8d3a9ee8beba4..60034657c69fb 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -280,11 +280,11 @@ define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: ldrsb w8, [x0]
; CHECK-GI-NEXT: ldrsb w9, [x1]
; CHECK-GI-NEXT: add w8, w8, w9
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w8, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w8, w9, w8, ne
; CHECK-GI-NEXT: strb w8, [x2]
; CHECK-GI-NEXT: ret
%x = load <1 x i8>, ptr %px
@@ -308,11 +308,11 @@ define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: ldrsh w8, [x0]
; CHECK-GI-NEXT: ldrsh w9, [x1]
; CHECK-GI-NEXT: add w8, w8, w9
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w8, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w8, w9, w8, ne
; CHECK-GI-NEXT: strh w8, [x2]
; CHECK-GI-NEXT: ret
%x = load <1 x i16>, ptr %px
diff --git a/llvm/test/CodeGen/AArch64/sat-add.ll b/llvm/test/CodeGen/AArch64/sat-add.ll
index 39f0ca57863b9..dfa260cb773cc 100644
--- a/llvm/test/CodeGen/AArch64/sat-add.ll
+++ b/llvm/test/CodeGen/AArch64/sat-add.ll
@@ -9,8 +9,8 @@
define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
; CHECK: // %bb.0:
-; CHECK-NEXT: and w9, w0, #0xff
; CHECK-NEXT: mov w8, #-43 // =0xffffffd5
+; CHECK-NEXT: and w9, w0, #0xff
; CHECK-NEXT: cmp w9, #213
; CHECK-NEXT: csel w8, w0, w8, lo
; CHECK-NEXT: add w0, w8, #42
diff --git a/llvm/test/CodeGen/AArch64/sbc.ll b/llvm/test/CodeGen/AArch64/sbc.ll
index 92b280f0ea55f..78dc839386217 100644
--- a/llvm/test/CodeGen/AArch64/sbc.ll
+++ b/llvm/test/CodeGen/AArch64/sbc.ll
@@ -177,8 +177,8 @@ define i32 @test_ugt_multi_use_flags(i32 %a, i32 %b, i32 %x, i32 %y, i32 %z) {
; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: sub w8, w2, w3
; CHECK-SD-NEXT: cset w9, hi
-; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: sub w8, w8, w9
+; CHECK-SD-NEXT: cmp w0, w1
; CHECK-SD-NEXT: csel w0, w8, w4, eq
; CHECK-SD-NEXT: ret
;
@@ -576,5 +576,3 @@ define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32>
}
declare void @use()
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/sdivpow2.ll b/llvm/test/CodeGen/AArch64/sdivpow2.ll
index bb18ceb3fe69c..68615716dd34e 100644
--- a/llvm/test/CodeGen/AArch64/sdivpow2.ll
+++ b/llvm/test/CodeGen/AArch64/sdivpow2.ll
@@ -126,8 +126,8 @@ define i64 @test7(i64 %x) {
; ISEL-LABEL: test7:
; ISEL: // %bb.0:
; ISEL-NEXT: mov x8, #281474976710655 // =0xffffffffffff
-; ISEL-NEXT: cmp x0, #0
; ISEL-NEXT: add x8, x0, x8
+; ISEL-NEXT: cmp x0, #0
; ISEL-NEXT: csel x8, x8, x0, mi
; ISEL-NEXT: asr x0, x8, #48
; ISEL-NEXT: ret
@@ -135,8 +135,8 @@ define i64 @test7(i64 %x) {
; FAST-LABEL: test7:
; FAST: // %bb.0:
; FAST-NEXT: mov x8, #281474976710655 // =0xffffffffffff
-; FAST-NEXT: cmp x0, #0
; FAST-NEXT: add x8, x0, x8
+; FAST-NEXT: cmp x0, #0
; FAST-NEXT: csel x8, x8, x0, lt
; FAST-NEXT: asr x0, x8, #48
; FAST-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/select_const.ll b/llvm/test/CodeGen/AArch64/select_const.ll
index daa9971dbcd58..b6487fba4559a 100644
--- a/llvm/test/CodeGen/AArch64/select_const.ll
+++ b/llvm/test/CodeGen/AArch64/select_const.ll
@@ -284,8 +284,8 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
; CHECK-SD-LABEL: select_C1_C2_zeroext:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #42 // =0x2a
-; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: mov w9, #421 // =0x1a5
+; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: csel w0, w9, w8, ne
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
index 5d7935474c903..814bc0fd9aedd 100644
--- a/llvm/test/CodeGen/AArch64/shift.ll
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -191,11 +191,11 @@ define i128 @ashr_i128(i128 %0, i128 %1){
; CHECK-GI-NEXT: lsr x10, x0, x2
; CHECK-GI-NEXT: sub x8, x8, x2
; CHECK-GI-NEXT: asr x9, x1, x9
-; CHECK-GI-NEXT: cmp x2, #64
-; CHECK-GI-NEXT: lsl x8, x1, x8
; CHECK-GI-NEXT: asr x11, x1, x2
+; CHECK-GI-NEXT: lsl x8, x1, x8
; CHECK-GI-NEXT: orr x8, x10, x8
; CHECK-GI-NEXT: asr x10, x1, #63
+; CHECK-GI-NEXT: cmp x2, #64
; CHECK-GI-NEXT: csel x8, x8, x9, lo
; CHECK-GI-NEXT: cmp x2, #0
; CHECK-GI-NEXT: csel x0, x0, x8, eq
@@ -295,15 +295,15 @@ define i128 @lshr_i128(i128 %0, i128 %1){
; CHECK-GI-NEXT: lsr x10, x0, x2
; CHECK-GI-NEXT: sub x8, x8, x2
; CHECK-GI-NEXT: lsr x9, x1, x9
-; CHECK-GI-NEXT: cmp x2, #64
+; CHECK-GI-NEXT: lsr x11, x1, x2
; CHECK-GI-NEXT: lsl x8, x1, x8
; CHECK-GI-NEXT: orr x8, x10, x8
-; CHECK-GI-NEXT: lsr x10, x1, x2
+; CHECK-GI-NEXT: cmp x2, #64
; CHECK-GI-NEXT: csel x8, x8, x9, lo
; CHECK-GI-NEXT: cmp x2, #0
; CHECK-GI-NEXT: csel x0, x0, x8, eq
; CHECK-GI-NEXT: cmp x2, #64
-; CHECK-GI-NEXT: csel x1, x10, xzr, lo
+; CHECK-GI-NEXT: csel x1, x11, xzr, lo
; CHECK-GI-NEXT: ret
%3 = lshr i128 %0, %1
ret i128 %3
@@ -663,21 +663,21 @@ define <2 x i128> @shl_v2i128(<2 x i128> %0, <2 x i128> %1){
; CHECK-GI-NEXT: sub x10, x4, #64
; CHECK-GI-NEXT: lsl x11, x1, x4
; CHECK-GI-NEXT: sub x9, x8, x4
-; CHECK-GI-NEXT: lsl x10, x0, x10
; CHECK-GI-NEXT: lsl x12, x0, x4
+; CHECK-GI-NEXT: lsl x10, x0, x10
; CHECK-GI-NEXT: lsr x9, x0, x9
; CHECK-GI-NEXT: cmp x4, #64
; CHECK-GI-NEXT: sub x8, x8, x6
-; CHECK-GI-NEXT: lsr x8, x2, x8
; CHECK-GI-NEXT: csel x0, x12, xzr, lo
+; CHECK-GI-NEXT: lsr x8, x2, x8
; CHECK-GI-NEXT: lsl x12, x2, x6
; CHECK-GI-NEXT: orr x9, x9, x11
; CHECK-GI-NEXT: lsl x11, x3, x6
; CHECK-GI-NEXT: csel x9, x9, x10, lo
; CHECK-GI-NEXT: sub x10, x6, #64
; CHECK-GI-NEXT: cmp x4, #0
-; CHECK-GI-NEXT: lsl x10, x2, x10
; CHECK-GI-NEXT: csel x1, x1, x9, eq
+; CHECK-GI-NEXT: lsl x10, x2, x10
; CHECK-GI-NEXT: orr x8, x8, x11
; CHECK-GI-NEXT: cmp x6, #64
; CHECK-GI-NEXT: csel x2, x12, xzr, lo
@@ -832,25 +832,25 @@ define <2 x i128> @ashr_v2i128(<2 x i128> %0, <2 x i128> %1){
; CHECK-GI-NEXT: lsr x11, x0, x4
; CHECK-GI-NEXT: sub x9, x8, x4
; CHECK-GI-NEXT: asr x10, x1, x10
-; CHECK-GI-NEXT: cmp x4, #64
-; CHECK-GI-NEXT: lsl x9, x1, x9
; CHECK-GI-NEXT: sub x8, x8, x6
+; CHECK-GI-NEXT: lsl x9, x1, x9
; CHECK-GI-NEXT: asr x12, x1, x4
+; CHECK-GI-NEXT: asr x13, x1, #63
; CHECK-GI-NEXT: lsl x8, x3, x8
; CHECK-GI-NEXT: orr x9, x11, x9
-; CHECK-GI-NEXT: asr x11, x1, #63
+; CHECK-GI-NEXT: cmp x4, #64
+; CHECK-GI-NEXT: sub x11, x6, #64
; CHECK-GI-NEXT: csel x9, x9, x10, lo
-; CHECK-GI-NEXT: cmp x4, #0
; CHECK-GI-NEXT: lsr x10, x2, x6
+; CHECK-GI-NEXT: cmp x4, #0
; CHECK-GI-NEXT: csel x0, x0, x9, eq
-; CHECK-GI-NEXT: sub x9, x6, #64
+; CHECK-GI-NEXT: asr x9, x3, x11
; CHECK-GI-NEXT: cmp x4, #64
-; CHECK-GI-NEXT: asr x9, x3, x9
-; CHECK-GI-NEXT: csel x1, x12, x11, lo
-; CHECK-GI-NEXT: orr x8, x10, x8
-; CHECK-GI-NEXT: cmp x6, #64
+; CHECK-GI-NEXT: csel x1, x12, x13, lo
; CHECK-GI-NEXT: asr x11, x3, x6
+; CHECK-GI-NEXT: orr x8, x10, x8
; CHECK-GI-NEXT: asr x10, x3, #63
+; CHECK-GI-NEXT: cmp x6, #64
; CHECK-GI-NEXT: csel x8, x8, x9, lo
; CHECK-GI-NEXT: cmp x6, #0
; CHECK-GI-NEXT: csel x2, x2, x8, eq
@@ -1000,23 +1000,23 @@ define <2 x i128> @lshr_v2i128(<2 x i128> %0, <2 x i128> %1){
; CHECK-GI-NEXT: lsr x11, x0, x4
; CHECK-GI-NEXT: sub x9, x8, x4
; CHECK-GI-NEXT: lsr x10, x1, x10
-; CHECK-GI-NEXT: cmp x4, #64
-; CHECK-GI-NEXT: lsl x9, x1, x9
; CHECK-GI-NEXT: sub x8, x8, x6
+; CHECK-GI-NEXT: lsl x9, x1, x9
; CHECK-GI-NEXT: lsr x12, x1, x4
+; CHECK-GI-NEXT: sub x13, x6, #64
; CHECK-GI-NEXT: lsl x8, x3, x8
; CHECK-GI-NEXT: orr x9, x11, x9
-; CHECK-GI-NEXT: lsr x11, x2, x6
+; CHECK-GI-NEXT: cmp x4, #64
; CHECK-GI-NEXT: csel x9, x9, x10, lo
+; CHECK-GI-NEXT: lsr x10, x2, x6
; CHECK-GI-NEXT: cmp x4, #0
-; CHECK-GI-NEXT: sub x10, x6, #64
; CHECK-GI-NEXT: csel x0, x0, x9, eq
+; CHECK-GI-NEXT: lsr x9, x3, x13
; CHECK-GI-NEXT: cmp x4, #64
-; CHECK-GI-NEXT: lsr x9, x3, x10
; CHECK-GI-NEXT: csel x1, x12, xzr, lo
-; CHECK-GI-NEXT: orr x8, x11, x8
-; CHECK-GI-NEXT: cmp x6, #64
+; CHECK-GI-NEXT: orr x8, x10, x8
; CHECK-GI-NEXT: lsr x10, x3, x6
+; CHECK-GI-NEXT: cmp x6, #64
; CHECK-GI-NEXT: csel x8, x8, x9, lo
; CHECK-GI-NEXT: cmp x6, #0
; CHECK-GI-NEXT: csel x2, x2, x8, eq
diff --git a/llvm/test/CodeGen/AArch64/smul_fix_sat.ll b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
index 744d1be126ff1..711adaa0649f0 100644
--- a/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
+++ b/llvm/test/CodeGen/AArch64/smul_fix_sat.ll
@@ -6,13 +6,13 @@
define i32 @func(i32 %x, i32 %y) {
; CHECK-SD-LABEL: func:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: smull x9, w0, w1
-; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
-; CHECK-SD-NEXT: lsr x10, x9, #32
-; CHECK-SD-NEXT: extr w9, w10, w9, #2
-; CHECK-SD-NEXT: cmp w10, #1
-; CHECK-SD-NEXT: csel w8, w8, w9, gt
-; CHECK-SD-NEXT: cmn w10, #2
+; CHECK-SD-NEXT: smull x8, w0, w1
+; CHECK-SD-NEXT: mov w10, #2147483647 // =0x7fffffff
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: extr w8, w9, w8, #2
+; CHECK-SD-NEXT: cmp w9, #1
+; CHECK-SD-NEXT: csel w8, w10, w8, gt
+; CHECK-SD-NEXT: cmn w9, #2
; CHECK-SD-NEXT: mov w9, #-2147483648 // =0x80000000
; CHECK-SD-NEXT: csel w0, w9, w8, lt
; CHECK-SD-NEXT: ret
@@ -36,13 +36,13 @@ define i32 @func(i32 %x, i32 %y) {
define i64 @func2(i64 %x, i64 %y) {
; CHECK-SD-LABEL: func2:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mul x9, x0, x1
-; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-SD-NEXT: smulh x10, x0, x1
-; CHECK-SD-NEXT: extr x9, x10, x9, #2
-; CHECK-SD-NEXT: cmp x10, #1
-; CHECK-SD-NEXT: csel x8, x8, x9, gt
-; CHECK-SD-NEXT: cmn x10, #2
+; CHECK-SD-NEXT: mul x8, x0, x1
+; CHECK-SD-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: smulh x9, x0, x1
+; CHECK-SD-NEXT: extr x8, x9, x8, #2
+; CHECK-SD-NEXT: cmp x9, #1
+; CHECK-SD-NEXT: csel x8, x10, x8, gt
+; CHECK-SD-NEXT: cmn x9, #2
; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
; CHECK-SD-NEXT: csel x0, x9, x8, lt
; CHECK-SD-NEXT: ret
@@ -82,15 +82,15 @@ define i64 @func2(i64 %x, i64 %y) {
define i4 @func3(i4 %x, i4 %y) {
; CHECK-SD-LABEL: func3:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sbfx w9, w1, #0, #4
-; CHECK-SD-NEXT: lsl w10, w0, #28
-; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
-; CHECK-SD-NEXT: smull x9, w10, w9
-; CHECK-SD-NEXT: lsr x10, x9, #32
-; CHECK-SD-NEXT: extr w9, w10, w9, #2
-; CHECK-SD-NEXT: cmp w10, #1
-; CHECK-SD-NEXT: csel w8, w8, w9, gt
-; CHECK-SD-NEXT: cmn w10, #2
+; CHECK-SD-NEXT: sbfx w8, w1, #0, #4
+; CHECK-SD-NEXT: lsl w9, w0, #28
+; CHECK-SD-NEXT: mov w10, #2147483647 // =0x7fffffff
+; CHECK-SD-NEXT: smull x8, w9, w8
+; CHECK-SD-NEXT: lsr x9, x8, #32
+; CHECK-SD-NEXT: extr w8, w9, w8, #2
+; CHECK-SD-NEXT: cmp w9, #1
+; CHECK-SD-NEXT: csel w8, w10, w8, gt
+; CHECK-SD-NEXT: cmn w9, #2
; CHECK-SD-NEXT: mov w9, #-2147483648 // =0x80000000
; CHECK-SD-NEXT: csel w8, w9, w8, lt
; CHECK-SD-NEXT: asr w0, w8, #28
@@ -98,13 +98,13 @@ define i4 @func3(i4 %x, i4 %y) {
;
; CHECK-GI-LABEL: func3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
-; CHECK-GI-NEXT: sbfx w10, w1, #0, #4
-; CHECK-GI-NEXT: mov w8, #7 // =0x7
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: sbfx w9, w9, #2, #6
-; CHECK-GI-NEXT: cmp w9, #7
-; CHECK-GI-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
+; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: sbfx w8, w8, #2, #6
+; CHECK-GI-NEXT: cmp w8, #7
+; CHECK-GI-NEXT: csel w8, w8, w9, lt
; CHECK-GI-NEXT: mov w9, #-8 // =0xfffffff8
; CHECK-GI-NEXT: cmn w8, #8
; CHECK-GI-NEXT: csel w0, w8, w9, gt
@@ -201,13 +201,13 @@ define i4 @func6(i4 %x, i4 %y) {
;
; CHECK-GI-LABEL: func6:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sbfx w9, w0, #0, #4
-; CHECK-GI-NEXT: sbfx w10, w1, #0, #4
-; CHECK-GI-NEXT: mov w8, #7 // =0x7
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: sxtb w9, w9
-; CHECK-GI-NEXT: cmp w9, #7
-; CHECK-GI-NEXT: csel w8, w9, w8, lt
+; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
+; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: sxtb w8, w8
+; CHECK-GI-NEXT: cmp w8, #7
+; CHECK-GI-NEXT: csel w8, w8, w9, lt
; CHECK-GI-NEXT: mov w9, #-8 // =0xfffffff8
; CHECK-GI-NEXT: cmn w8, #8
; CHECK-GI-NEXT: csel w0, w8, w9, gt
@@ -221,15 +221,15 @@ define i64 @func7(i64 %x, i64 %y) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mul x9, x0, x1
; CHECK-SD-NEXT: mov w8, #2147483647 // =0x7fffffff
-; CHECK-SD-NEXT: mov x11, #-2147483648 // =0xffffffff80000000
+; CHECK-SD-NEXT: mov x11, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: smulh x10, x0, x1
; CHECK-SD-NEXT: extr x9, x10, x9, #32
; CHECK-SD-NEXT: cmp x10, x8
-; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-SD-NEXT: csel x8, x8, x9, gt
-; CHECK-SD-NEXT: cmp x10, x11
-; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: csel x0, x9, x8, lt
+; CHECK-SD-NEXT: csel x8, x11, x9, gt
+; CHECK-SD-NEXT: mov x9, #-2147483648 // =0xffffffff80000000
+; CHECK-SD-NEXT: mov x11, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: cmp x10, x9
+; CHECK-SD-NEXT: csel x0, x11, x8, lt
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: func7:
@@ -269,15 +269,15 @@ define i64 @func8(i64 %x, i64 %y) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mul x9, x0, x1
; CHECK-SD-NEXT: mov x8, #4611686018427387903 // =0x3fffffffffffffff
-; CHECK-SD-NEXT: mov x11, #-4611686018427387904 // =0xc000000000000000
+; CHECK-SD-NEXT: mov x11, #9223372036854775807 // =0x7fffffffffffffff
; CHECK-SD-NEXT: smulh x10, x0, x1
; CHECK-SD-NEXT: extr x9, x10, x9, #63
; CHECK-SD-NEXT: cmp x10, x8
-; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-SD-NEXT: csel x8, x8, x9, gt
-; CHECK-SD-NEXT: cmp x10, x11
-; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: csel x0, x9, x8, lt
+; CHECK-SD-NEXT: csel x8, x11, x9, gt
+; CHECK-SD-NEXT: mov x9, #-4611686018427387904 // =0xc000000000000000
+; CHECK-SD-NEXT: mov x11, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: cmp x10, x9
+; CHECK-SD-NEXT: csel x0, x11, x8, lt
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: func8:
@@ -536,28 +536,28 @@ define <8 x i32> @vec_v8i32(<8 x i32> %x, <8 x i32> %y) {
define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) {
; CHECK-SD-LABEL: vec_v2i64:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: mov x9, v1.d[1]
-; CHECK-SD-NEXT: mov x10, v0.d[1]
-; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
-; CHECK-SD-NEXT: fmov x12, d0
-; CHECK-SD-NEXT: mul x11, x10, x9
-; CHECK-SD-NEXT: smulh x9, x10, x9
-; CHECK-SD-NEXT: fmov x10, d1
-; CHECK-SD-NEXT: mul x13, x12, x10
-; CHECK-SD-NEXT: smulh x10, x12, x10
-; CHECK-SD-NEXT: extr x11, x9, x11, #15
+; CHECK-SD-NEXT: mov x8, v1.d[1]
+; CHECK-SD-NEXT: mov x9, v0.d[1]
+; CHECK-SD-NEXT: fmov x11, d0
+; CHECK-SD-NEXT: mul x10, x9, x8
+; CHECK-SD-NEXT: smulh x8, x9, x8
+; CHECK-SD-NEXT: fmov x9, d1
+; CHECK-SD-NEXT: mul x12, x11, x9
+; CHECK-SD-NEXT: smulh x9, x11, x9
+; CHECK-SD-NEXT: extr x10, x8, x10, #15
+; CHECK-SD-NEXT: mov x11, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: cmp x8, #4, lsl #12 // =16384
+; CHECK-SD-NEXT: csel x10, x11, x10, ge
+; CHECK-SD-NEXT: cmn x8, #4, lsl #12 // =16384
+; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-SD-NEXT: csel x10, x8, x10, lt
+; CHECK-SD-NEXT: extr x12, x9, x12, #15
; CHECK-SD-NEXT: cmp x9, #4, lsl #12 // =16384
-; CHECK-SD-NEXT: csel x11, x8, x11, ge
+; CHECK-SD-NEXT: csel x11, x11, x12, ge
; CHECK-SD-NEXT: cmn x9, #4, lsl #12 // =16384
-; CHECK-SD-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: csel x11, x9, x11, lt
-; CHECK-SD-NEXT: extr x12, x10, x13, #15
-; CHECK-SD-NEXT: cmp x10, #4, lsl #12 // =16384
-; CHECK-SD-NEXT: csel x8, x8, x12, ge
-; CHECK-SD-NEXT: cmn x10, #4, lsl #12 // =16384
-; CHECK-SD-NEXT: csel x8, x9, x8, lt
+; CHECK-SD-NEXT: csel x8, x8, x11, lt
; CHECK-SD-NEXT: fmov d0, x8
-; CHECK-SD-NEXT: mov v0.d[1], x11
+; CHECK-SD-NEXT: mov v0.d[1], x10
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: vec_v2i64:
@@ -628,48 +628,48 @@ define <4 x i64> @vec_v4i64(<4 x i64> %x, <4 x i64> %y) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov x8, v2.d[1]
; CHECK-SD-NEXT: mov x9, v0.d[1]
-; CHECK-SD-NEXT: mov w16, #2147483647 // =0x7fffffff
-; CHECK-SD-NEXT: fmov x10, d2
-; CHECK-SD-NEXT: fmov x11, d0
-; CHECK-SD-NEXT: mov x18, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: mov w17, #2147483647 // =0x7fffffff
; CHECK-SD-NEXT: mov x14, v3.d[1]
; CHECK-SD-NEXT: mov x15, v1.d[1]
+; CHECK-SD-NEXT: mov x18, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-SD-NEXT: fmov x10, d2
+; CHECK-SD-NEXT: fmov x11, d0
+; CHECK-SD-NEXT: mov x0, #-9223372036854775808 // =0x8000000000000000
; CHECK-SD-NEXT: mul x13, x9, x8
; CHECK-SD-NEXT: smulh x8, x9, x8
; CHECK-SD-NEXT: mul x12, x11, x10
; CHECK-SD-NEXT: smulh x9, x11, x10
; CHECK-SD-NEXT: extr x13, x8, x13, #32
-; CHECK-SD-NEXT: cmp x8, x16
+; CHECK-SD-NEXT: cmp x8, x17
; CHECK-SD-NEXT: mul x10, x15, x14
; CHECK-SD-NEXT: csel x13, x18, x13, gt
; CHECK-SD-NEXT: smulh x11, x15, x14
; CHECK-SD-NEXT: fmov x14, d3
; CHECK-SD-NEXT: fmov x15, d1
; CHECK-SD-NEXT: extr x12, x9, x12, #32
-; CHECK-SD-NEXT: mul x17, x15, x14
+; CHECK-SD-NEXT: mul x16, x15, x14
; CHECK-SD-NEXT: smulh x14, x15, x14
; CHECK-SD-NEXT: mov x15, #-2147483648 // =0xffffffff80000000
+; CHECK-SD-NEXT: extr x10, x11, x10, #32
; CHECK-SD-NEXT: cmp x8, x15
-; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
-; CHECK-SD-NEXT: csel x13, x8, x13, lt
-; CHECK-SD-NEXT: cmp x9, x16
+; CHECK-SD-NEXT: csel x8, x0, x13, lt
+; CHECK-SD-NEXT: cmp x9, x17
; CHECK-SD-NEXT: csel x12, x18, x12, gt
; CHECK-SD-NEXT: cmp x9, x15
-; CHECK-SD-NEXT: extr x9, x11, x10, #32
-; CHECK-SD-NEXT: csel x10, x8, x12, lt
-; CHECK-SD-NEXT: cmp x11, x16
-; CHECK-SD-NEXT: csel x9, x18, x9, gt
+; CHECK-SD-NEXT: csel x9, x0, x12, lt
+; CHECK-SD-NEXT: cmp x11, x17
+; CHECK-SD-NEXT: csel x10, x18, x10, gt
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: extr x12, x14, x16, #32
; CHECK-SD-NEXT: cmp x11, x15
-; CHECK-SD-NEXT: extr x11, x14, x17, #32
-; CHECK-SD-NEXT: csel x9, x8, x9, lt
-; CHECK-SD-NEXT: cmp x14, x16
-; CHECK-SD-NEXT: fmov d0, x10
-; CHECK-SD-NEXT: csel x11, x18, x11, gt
+; CHECK-SD-NEXT: csel x10, x0, x10, lt
+; CHECK-SD-NEXT: cmp x14, x17
+; CHECK-SD-NEXT: csel x11, x18, x12, gt
; CHECK-SD-NEXT: cmp x14, x15
-; CHECK-SD-NEXT: csel x8, x8, x11, lt
-; CHECK-SD-NEXT: fmov d1, x8
-; CHECK-SD-NEXT: mov v0.d[1], x13
-; CHECK-SD-NEXT: mov v1.d[1], x9
+; CHECK-SD-NEXT: mov v0.d[1], x8
+; CHECK-SD-NEXT: csel x11, x0, x11, lt
+; CHECK-SD-NEXT: fmov d1, x11
+; CHECK-SD-NEXT: mov v1.d[1], x10
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: vec_v4i64:
diff --git a/llvm/test/CodeGen/AArch64/split-vector-insert.ll b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
index 109059e76bbc6..3848a72d3cfeb 100644
--- a/llvm/test/CodeGen/AArch64/split-vector-insert.ll
+++ b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
@@ -17,30 +17,30 @@ define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %
; CHECK-LEGALIZATION-NEXT: .cfi_offset w29, -16
; CHECK-LEGALIZATION-NEXT: addvl sp, sp, #-3
; CHECK-LEGALIZATION-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-LEGALIZATION-NEXT: cntd x8
; CHECK-LEGALIZATION-NEXT: ptrue p0.d, vl2
+; CHECK-LEGALIZATION-NEXT: cntd x8
; CHECK-LEGALIZATION-NEXT: mov w9, #2 // =0x2
; CHECK-LEGALIZATION-NEXT: sub x8, x8, #2
; CHECK-LEGALIZATION-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-LEGALIZATION-NEXT: mov x10, sp
-; CHECK-LEGALIZATION-NEXT: cmp x8, #2
; CHECK-LEGALIZATION-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-LEGALIZATION-NEXT: cmp x8, #2
; CHECK-LEGALIZATION-NEXT: csel x9, x8, x9, lo
-; CHECK-LEGALIZATION-NEXT: cmp x8, #4
; CHECK-LEGALIZATION-NEXT: lsl x9, x9, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp]
; CHECK-LEGALIZATION-NEXT: str q2, [x10, x9]
; CHECK-LEGALIZATION-NEXT: mov w9, #4 // =0x4
-; CHECK-LEGALIZATION-NEXT: addvl x10, sp, #1
-; CHECK-LEGALIZATION-NEXT: ldr z0, [sp]
+; CHECK-LEGALIZATION-NEXT: cmp x8, #4
; CHECK-LEGALIZATION-NEXT: csel x9, x8, x9, lo
-; CHECK-LEGALIZATION-NEXT: cmp x8, #6
+; CHECK-LEGALIZATION-NEXT: ldr z0, [sp]
+; CHECK-LEGALIZATION-NEXT: addvl x10, sp, #1
; CHECK-LEGALIZATION-NEXT: lsl x9, x9, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp, #1, mul vl]
; CHECK-LEGALIZATION-NEXT: str q3, [x10, x9]
; CHECK-LEGALIZATION-NEXT: mov w9, #6 // =0x6
-; CHECK-LEGALIZATION-NEXT: ldr z0, [sp, #1, mul vl]
+; CHECK-LEGALIZATION-NEXT: cmp x8, #6
; CHECK-LEGALIZATION-NEXT: csel x8, x8, x9, lo
+; CHECK-LEGALIZATION-NEXT: ldr z0, [sp, #1, mul vl]
; CHECK-LEGALIZATION-NEXT: addvl x9, sp, #2
; CHECK-LEGALIZATION-NEXT: lsl x8, x8, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp, #2, mul vl]
@@ -60,30 +60,30 @@ define <vscale x 2 x i64> @test_nxv2i64_v8i64(<vscale x 2 x i64> %a, <8 x i64> %
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: cntd x8
; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 // =0x2
; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov x10, sp
-; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: csel x9, x8, x9, lo
-; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: str q2, [x10, x9]
; CHECK-NEXT: mov w9, #4 // =0x4
-; CHECK-NEXT: addvl x10, sp, #1
-; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: csel x9, x8, x9, lo
-; CHECK-NEXT: cmp x8, #6
+; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: str z0, [sp, #1, mul vl]
; CHECK-NEXT: str q3, [x10, x9]
; CHECK-NEXT: mov w9, #6 // =0x6
-; CHECK-NEXT: ldr z0, [sp, #1, mul vl]
+; CHECK-NEXT: cmp x8, #6
; CHECK-NEXT: csel x8, x8, x9, lo
+; CHECK-NEXT: ldr z0, [sp, #1, mul vl]
; CHECK-NEXT: addvl x9, sp, #2
; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: str z0, [sp, #2, mul vl]
@@ -112,30 +112,30 @@ define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x
; CHECK-LEGALIZATION-NEXT: .cfi_offset w29, -16
; CHECK-LEGALIZATION-NEXT: addvl sp, sp, #-3
; CHECK-LEGALIZATION-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-LEGALIZATION-NEXT: cntd x8
; CHECK-LEGALIZATION-NEXT: ptrue p0.d, vl2
+; CHECK-LEGALIZATION-NEXT: cntd x8
; CHECK-LEGALIZATION-NEXT: mov w9, #2 // =0x2
; CHECK-LEGALIZATION-NEXT: sub x8, x8, #2
; CHECK-LEGALIZATION-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-LEGALIZATION-NEXT: mov x10, sp
-; CHECK-LEGALIZATION-NEXT: cmp x8, #2
; CHECK-LEGALIZATION-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-LEGALIZATION-NEXT: cmp x8, #2
; CHECK-LEGALIZATION-NEXT: csel x9, x8, x9, lo
-; CHECK-LEGALIZATION-NEXT: cmp x8, #4
; CHECK-LEGALIZATION-NEXT: lsl x9, x9, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp]
; CHECK-LEGALIZATION-NEXT: str q2, [x10, x9]
; CHECK-LEGALIZATION-NEXT: mov w9, #4 // =0x4
-; CHECK-LEGALIZATION-NEXT: addvl x10, sp, #1
-; CHECK-LEGALIZATION-NEXT: ldr z0, [sp]
+; CHECK-LEGALIZATION-NEXT: cmp x8, #4
; CHECK-LEGALIZATION-NEXT: csel x9, x8, x9, lo
-; CHECK-LEGALIZATION-NEXT: cmp x8, #6
+; CHECK-LEGALIZATION-NEXT: ldr z0, [sp]
+; CHECK-LEGALIZATION-NEXT: addvl x10, sp, #1
; CHECK-LEGALIZATION-NEXT: lsl x9, x9, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp, #1, mul vl]
; CHECK-LEGALIZATION-NEXT: str q3, [x10, x9]
; CHECK-LEGALIZATION-NEXT: mov w9, #6 // =0x6
-; CHECK-LEGALIZATION-NEXT: ldr z0, [sp, #1, mul vl]
+; CHECK-LEGALIZATION-NEXT: cmp x8, #6
; CHECK-LEGALIZATION-NEXT: csel x8, x8, x9, lo
+; CHECK-LEGALIZATION-NEXT: ldr z0, [sp, #1, mul vl]
; CHECK-LEGALIZATION-NEXT: addvl x9, sp, #2
; CHECK-LEGALIZATION-NEXT: lsl x8, x8, #3
; CHECK-LEGALIZATION-NEXT: str z0, [sp, #2, mul vl]
@@ -155,30 +155,30 @@ define <vscale x 2 x double> @test_nxv2f64_v8f64(<vscale x 2 x double> %a, <8 x
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT: cntd x8
; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: cntd x8
; CHECK-NEXT: mov w9, #2 // =0x2
; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: mov x10, sp
-; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: cmp x8, #2
; CHECK-NEXT: csel x9, x8, x9, lo
-; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: str q2, [x10, x9]
; CHECK-NEXT: mov w9, #4 // =0x4
-; CHECK-NEXT: addvl x10, sp, #1
-; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: cmp x8, #4
; CHECK-NEXT: csel x9, x8, x9, lo
-; CHECK-NEXT: cmp x8, #6
+; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: addvl x10, sp, #1
; CHECK-NEXT: lsl x9, x9, #3
; CHECK-NEXT: str z0, [sp, #1, mul vl]
; CHECK-NEXT: str q3, [x10, x9]
; CHECK-NEXT: mov w9, #6 // =0x6
-; CHECK-NEXT: ldr z0, [sp, #1, mul vl]
+; CHECK-NEXT: cmp x8, #6
; CHECK-NEXT: csel x8, x8, x9, lo
+; CHECK-NEXT: ldr z0, [sp, #1, mul vl]
; CHECK-NEXT: addvl x9, sp, #2
; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: str z0, [sp, #2, mul vl]
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll b/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
index 8a41482b01652..f57e04178f0c2 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
@@ -5,12 +5,12 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
; CHECK-LABEL: test_minsize:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #5 // =0x5
-; CHECK-NEXT: mov w9, #42 // =0x2a
+; CHECK-NEXT: mov w9, #-10 // =0xfffffff6
+; CHECK-NEXT: mov w10, #42 // =0x2a
; CHECK-NEXT: sdiv w8, w0, w8
; CHECK-NEXT: add w8, w8, w8, lsl #2
; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
-; CHECK-NEXT: csel w0, w9, w8, eq
+; CHECK-NEXT: csel w0, w10, w9, eq
; CHECK-NEXT: ret
%rem = srem i32 %X, 5
%cmp = icmp eq i32 %rem, 0
@@ -23,14 +23,14 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone {
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429 // =0xcccd
; CHECK-NEXT: mov w9, #39321 // =0x9999
+; CHECK-NEXT: mov w10, #-10 // =0xfffffff6
; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: movk w9, #6553, lsl #16
+; CHECK-NEXT: mov w11, #42 // =0x2a
; CHECK-NEXT: madd w8, w0, w8, w9
; CHECK-NEXT: mov w9, #858993459 // =0x33333333
; CHECK-NEXT: cmp w8, w9
-; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
-; CHECK-NEXT: mov w9, #42 // =0x2a
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: csel w0, w11, w10, lo
; CHECK-NEXT: ret
%rem = srem i32 %X, 5
%cmp = icmp eq i32 %rem, 0
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat.ll b/llvm/test/CodeGen/AArch64/ssub_sat.ll
index 4740803fc7622..8f0ac6c655353 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat.ll
@@ -63,11 +63,11 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sxth w8, w0
; CHECK-GI-NEXT: sub w8, w8, w1, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
@@ -76,11 +76,11 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: func8:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: sxtb w9, w0
-; CHECK-SD-NEXT: mov w8, #127 // =0x7f
-; CHECK-SD-NEXT: sub w9, w9, w1, sxtb
-; CHECK-SD-NEXT: cmp w9, #127
-; CHECK-SD-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-NEXT: sxtb w8, w0
+; CHECK-SD-NEXT: mov w9, #127 // =0x7f
+; CHECK-SD-NEXT: sub w8, w8, w1, sxtb
+; CHECK-SD-NEXT: cmp w8, #127
+; CHECK-SD-NEXT: csel w8, w8, w9, lt
; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80
; CHECK-SD-NEXT: cmn w8, #128
; CHECK-SD-NEXT: csel w0, w8, w9, gt
@@ -90,11 +90,11 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: sxtb w8, w0
; CHECK-GI-NEXT: sub w8, w8, w1, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
@@ -103,12 +103,12 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-SD-LABEL: func3:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: lsl w9, w1, #28
-; CHECK-SD-NEXT: sbfx w10, w0, #0, #4
-; CHECK-SD-NEXT: mov w8, #7 // =0x7
-; CHECK-SD-NEXT: sub w9, w10, w9, asr #28
-; CHECK-SD-NEXT: cmp w9, #7
-; CHECK-SD-NEXT: csel w8, w9, w8, lt
+; CHECK-SD-NEXT: lsl w8, w1, #28
+; CHECK-SD-NEXT: sbfx w9, w0, #0, #4
+; CHECK-SD-NEXT: sub w8, w9, w8, asr #28
+; CHECK-SD-NEXT: mov w9, #7 // =0x7
+; CHECK-SD-NEXT: cmp w8, #7
+; CHECK-SD-NEXT: csel w8, w8, w9, lt
; CHECK-SD-NEXT: mov w9, #-8 // =0xfffffff8
; CHECK-SD-NEXT: cmn w8, #8
; CHECK-SD-NEXT: csel w0, w8, w9, gt
@@ -121,8 +121,8 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
; CHECK-GI-NEXT: sub w8, w8, w9
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
+; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll b/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
index f08629c15f26c..32f2b22842e12 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
@@ -75,11 +75,11 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxth w9, w0
; CHECK-GI-NEXT: sub w8, w9, w8, sxth
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i16 %y, %z
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
@@ -105,11 +105,11 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: sxtb w9, w0
; CHECK-GI-NEXT: sub w8, w9, w8, sxtb
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i8 %y, %z
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
@@ -139,8 +139,8 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-GI-NEXT: sub w8, w9, w8
; CHECK-GI-NEXT: sbfx w9, w8, #0, #4
; CHECK-GI-NEXT: asr w10, w9, #3
-; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: add w10, w10, #8
+; CHECK-GI-NEXT: cmp w8, w9
; CHECK-GI-NEXT: csel w0, w10, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i4 %y, %z
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index f4359edcc1bbd..fc62160ce4d27 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -280,11 +280,11 @@ define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: ldrsb w8, [x0]
; CHECK-GI-NEXT: ldrsb w9, [x1]
; CHECK-GI-NEXT: sub w8, w8, w9
-; CHECK-GI-NEXT: sxtb w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #7, #1
-; CHECK-GI-NEXT: sub w10, w10, #128
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w8, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #7, #1
+; CHECK-GI-NEXT: sxtb w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #128
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w8, w9, w8, ne
; CHECK-GI-NEXT: strb w8, [x2]
; CHECK-GI-NEXT: ret
%x = load <1 x i8>, ptr %px
@@ -308,11 +308,11 @@ define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-GI-NEXT: ldrsh w8, [x0]
; CHECK-GI-NEXT: ldrsh w9, [x1]
; CHECK-GI-NEXT: sub w8, w8, w9
-; CHECK-GI-NEXT: sxth w9, w8
-; CHECK-GI-NEXT: sbfx w10, w8, #15, #1
-; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w8, w10, w8, ne
+; CHECK-GI-NEXT: sbfx w9, w8, #15, #1
+; CHECK-GI-NEXT: sxth w10, w8
+; CHECK-GI-NEXT: sub w9, w9, #8, lsl #12 // =32768
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w8, w9, w8, ne
; CHECK-GI-NEXT: strh w8, [x2]
; CHECK-GI-NEXT: ret
%x = load <1 x i16>, ptr %px
diff --git a/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll b/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
index 3473b063e35ee..e71fa92e806f3 100644
--- a/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
@@ -102,11 +102,11 @@ define <2 x i64> @extract_v2i64_nxv8i64_8(<vscale x 8 x i64> %arg) {
; CHECK-NEXT: sub x8, x8, #2
; CHECK-NEXT: str z2, [sp, #2, mul vl]
; CHECK-NEXT: cmp x8, #8
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x8, x9, lo
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
+; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: lsl x8, x8, #3
; CHECK-NEXT: ldr q0, [x9, x8]
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-insert-element.ll b/llvm/test/CodeGen/AArch64/sve-insert-element.ll
index 29da2a7db8dc4..77a45e240ce25 100644
--- a/llvm/test/CodeGen/AArch64/sve-insert-element.ll
+++ b/llvm/test/CodeGen/AArch64/sve-insert-element.ll
@@ -633,8 +633,8 @@ define <vscale x 32 x i1> @test_predicate_insert_32xi1(<vscale x 32 x i1> %val,
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 16 + 16 * VG
-; CHECK-NEXT: rdvl x8, #2
; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
+; CHECK-NEXT: rdvl x8, #2
; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: mov w9, w1
diff --git a/llvm/test/CodeGen/AArch64/sve-mask-partition.ll b/llvm/test/CodeGen/AArch64/sve-mask-partition.ll
index 98855998c9cb3..b91c61c25e45a 100644
--- a/llvm/test/CodeGen/AArch64/sve-mask-partition.ll
+++ b/llvm/test/CodeGen/AArch64/sve-mask-partition.ll
@@ -226,10 +226,10 @@ define <vscale x 32 x i1> @mask_exclude_active_nxv32(<vscale x 32 x i1> %mask.in
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: rdvl x8, #1
; CHECK-NEXT: mov x9, x8
-; CHECK-NEXT: brkb p0.b, p2/z, p0.b
; CHECK-NEXT: brkb p1.b, p2/z, p1.b
-; CHECK-NEXT: cntp x10, p0, p0.b
+; CHECK-NEXT: brkb p0.b, p2/z, p0.b
; CHECK-NEXT: incp x9, p1.b
+; CHECK-NEXT: cntp x10, p0, p0.b
; CHECK-NEXT: cmp x10, x8
; CHECK-NEXT: csel x9, x10, x9, ne
; CHECK-NEXT: whilelo p0.b, xzr, x9
@@ -244,15 +244,15 @@ define <32 x i1> @mask_exclude_active_v32(<32 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w9, [sp, #64]
-; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ldr w10, [sp, #72]
+; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: mov w11, #16 // =0x10
; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: ldr w9, [sp, #80]
; CHECK-NEXT: mov v0.b[1], w1
; CHECK-NEXT: mov v1.b[1], w10
-; CHECK-NEXT: ldr w10, [sp, #128]
+; CHECK-NEXT: ldr w10, [sp]
; CHECK-NEXT: mov v0.b[2], w2
; CHECK-NEXT: mov v1.b[2], w9
; CHECK-NEXT: ldr w9, [sp, #88]
@@ -270,48 +270,48 @@ define <32 x i1> @mask_exclude_active_v32(<32 x i1> %mask.in) {
; CHECK-NEXT: ldr w9, [sp, #120]
; CHECK-NEXT: mov v0.b[7], w7
; CHECK-NEXT: mov v1.b[7], w9
-; CHECK-NEXT: ldr w9, [sp]
-; CHECK-NEXT: mov v0.b[8], w9
-; CHECK-NEXT: ldr w9, [sp, #8]
-; CHECK-NEXT: mov v1.b[8], w10
-; CHECK-NEXT: ldr w10, [sp, #136]
-; CHECK-NEXT: mov v0.b[9], w9
-; CHECK-NEXT: ldr w9, [sp, #16]
-; CHECK-NEXT: mov v1.b[9], w10
-; CHECK-NEXT: ldr w10, [sp, #144]
-; CHECK-NEXT: mov v0.b[10], w9
-; CHECK-NEXT: ldr w9, [sp, #24]
-; CHECK-NEXT: mov v1.b[10], w10
-; CHECK-NEXT: ldr w10, [sp, #152]
-; CHECK-NEXT: mov v0.b[11], w9
-; CHECK-NEXT: ldr w9, [sp, #32]
-; CHECK-NEXT: mov v1.b[11], w10
-; CHECK-NEXT: ldr w10, [sp, #160]
-; CHECK-NEXT: mov v0.b[12], w9
-; CHECK-NEXT: ldr w9, [sp, #40]
-; CHECK-NEXT: mov v1.b[12], w10
-; CHECK-NEXT: ldr w10, [sp, #168]
-; CHECK-NEXT: mov v0.b[13], w9
-; CHECK-NEXT: ldr w9, [sp, #48]
-; CHECK-NEXT: mov v1.b[13], w10
-; CHECK-NEXT: ldr w10, [sp, #176]
-; CHECK-NEXT: mov v0.b[14], w9
-; CHECK-NEXT: ldr w9, [sp, #56]
-; CHECK-NEXT: mov v1.b[14], w10
-; CHECK-NEXT: ldr w10, [sp, #184]
-; CHECK-NEXT: mov v0.b[15], w9
-; CHECK-NEXT: mov v1.b[15], w10
+; CHECK-NEXT: ldr w9, [sp, #128]
+; CHECK-NEXT: mov v0.b[8], w10
+; CHECK-NEXT: ldr w10, [sp, #8]
+; CHECK-NEXT: mov v1.b[8], w9
+; CHECK-NEXT: ldr w9, [sp, #136]
+; CHECK-NEXT: mov v0.b[9], w10
+; CHECK-NEXT: ldr w10, [sp, #16]
+; CHECK-NEXT: mov v1.b[9], w9
+; CHECK-NEXT: ldr w9, [sp, #144]
+; CHECK-NEXT: mov v0.b[10], w10
+; CHECK-NEXT: ldr w10, [sp, #24]
+; CHECK-NEXT: mov v1.b[10], w9
+; CHECK-NEXT: ldr w9, [sp, #152]
+; CHECK-NEXT: mov v0.b[11], w10
+; CHECK-NEXT: ldr w10, [sp, #32]
+; CHECK-NEXT: mov v1.b[11], w9
+; CHECK-NEXT: ldr w9, [sp, #160]
+; CHECK-NEXT: mov v0.b[12], w10
+; CHECK-NEXT: ldr w10, [sp, #40]
+; CHECK-NEXT: mov v1.b[12], w9
+; CHECK-NEXT: ldr w9, [sp, #168]
+; CHECK-NEXT: mov v0.b[13], w10
+; CHECK-NEXT: ldr w10, [sp, #48]
+; CHECK-NEXT: mov v1.b[13], w9
+; CHECK-NEXT: ldr w9, [sp, #176]
+; CHECK-NEXT: mov v0.b[14], w10
+; CHECK-NEXT: ldr w10, [sp, #56]
+; CHECK-NEXT: mov v1.b[14], w9
+; CHECK-NEXT: ldr w9, [sp, #184]
+; CHECK-NEXT: mov v0.b[15], w10
+; CHECK-NEXT: mov v1.b[15], w9
; CHECK-NEXT: shl v0.16b, v0.16b, #7
; CHECK-NEXT: shl v1.16b, v1.16b, #7
-; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0
-; CHECK-NEXT: cmpne p2.b, p0/z, z1.b, #0
-; CHECK-NEXT: brkb p1.b, p0/z, p1.b
+; CHECK-NEXT: cmpne p2.b, p0/z, z0.b, #0
+; CHECK-NEXT: cmpne p1.b, p0/z, z1.b, #0
; CHECK-NEXT: brkb p2.b, p0/z, p2.b
-; CHECK-NEXT: cntp x9, p1, p1.b
+; CHECK-NEXT: brkb p1.b, p0/z, p1.b
; CHECK-NEXT: cntp x10, p2, p2.b
-; CHECK-NEXT: cmp x9, #16
-; CHECK-NEXT: add x10, x10, #16
-; CHECK-NEXT: csel x9, x9, x10, ne
+; CHECK-NEXT: cntp x9, p1, p1.b
+; CHECK-NEXT: add x9, x9, #16
+; CHECK-NEXT: cmp x10, #16
+; CHECK-NEXT: csel x9, x10, x9, ne
; CHECK-NEXT: whilelo p0.b, x11, x9
; CHECK-NEXT: whilelo p1.b, xzr, x9
; CHECK-NEXT: adrp x9, .LCPI17_0
diff --git a/llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll b/llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
index 0bc8cb8bc5003..2a959798c4d16 100644
--- a/llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
@@ -96,10 +96,10 @@ define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) {
; CHECK-NEXT: str z3, [sp, #3, mul vl]
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: str z2, [sp, #2, mul vl]
-; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: str z1, [sp, #1, mul vl]
-; CHECK-NEXT: str z0, [sp]
+; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: csel x8, x9, x8, lo
+; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr x0, [x9, x8, lsl #3]
; CHECK-NEXT: addvl sp, sp, #4
@@ -165,10 +165,10 @@ define i32 @split_extract_16i32(<vscale x 16 x i32> %a) {
; CHECK-NEXT: movk w9, #1, lsl #16
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: str z2, [sp, #2, mul vl]
-; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: str z1, [sp, #1, mul vl]
-; CHECK-NEXT: str z0, [sp]
+; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: csel x8, x8, x9, lo
+; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ldr w0, [x9, x8, lsl #2]
; CHECK-NEXT: addvl sp, sp, #4
diff --git a/llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll b/llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
index 6116473d9588e..170edfdcf7f87 100644
--- a/llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
@@ -77,8 +77,8 @@ define <vscale x 8 x i64> @split_insert_8i64_idx(<vscale x 8 x i64> %a, i64 %elt
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: str z2, [sp, #2, mul vl]
; CHECK-NEXT: cmp x1, x8
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x1, x8, lo
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: str x0, [x9, x8, lsl #3]
; CHECK-NEXT: ldr z0, [sp]
@@ -138,9 +138,9 @@ define <vscale x 32 x i16> @split_insert_32i16(<vscale x 32 x i16> %a, i16 %elt)
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: str z2, [sp, #2, mul vl]
; CHECK-NEXT: cmp x8, #128
-; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: str z1, [sp, #1, mul vl]
; CHECK-NEXT: str z0, [sp]
; CHECK-NEXT: strh w0, [x9, x8, lsl #1]
; CHECK-NEXT: ldr z0, [sp]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
index 682dc0927d810..43c7ded2aba2f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
@@ -430,23 +430,23 @@ define i8 @smaxv_v8i8(<8 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrsb w8, [sp, #9]
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #11]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #13]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #13]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, gt
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -470,49 +470,49 @@ define i8 @smaxv_v16i8(<16 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrsb w8, [sp, #1]
; NONEON-NOSVE-NEXT: ldrsb w9, [sp]
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #2]
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #3]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #4]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #5]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #6]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #5]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #9]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #11]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #11]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, gt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, gt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %a)
@@ -540,87 +540,87 @@ define i8 @smaxv_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: ldrsb w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #18]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #18]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #2]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #19]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #21]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #5]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #22]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #22]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #23]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #25]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #26]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #26]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #27]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #29]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #30]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #30]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #14]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #31]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
@@ -651,13 +651,13 @@ define i16 @smaxv_v4i16(<4 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrsh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, gt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, gt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %a)
@@ -679,23 +679,23 @@ define i16 @smaxv_v8i16(<8 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrsh w8, [sp, #2]
; NONEON-NOSVE-NEXT: ldrsh w9, [sp]
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #4]
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #10]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, gt
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, gt
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -725,39 +725,39 @@ define i16 @smaxv_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: ldrsh w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, gt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #22]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #26]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #30]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, gt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
@@ -807,13 +807,13 @@ define i32 @smaxv_v4i32(<4 x i32> %a) {
; NONEON-NOSVE-NEXT: str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldp w9, w8, [sp]
+; NONEON-NOSVE-NEXT: ldp w10, w11, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
-; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, gt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, gt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, gt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a)
@@ -841,8 +841,8 @@ define i32 @smaxv_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: csel w8, w8, w9, gt
; NONEON-NOSVE-NEXT: cmp w11, w10
; NONEON-NOSVE-NEXT: csel w9, w11, w10, gt
-; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: ldp w11, w12, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, gt
; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
@@ -931,23 +931,23 @@ define i8 @sminv_v8i8(<8 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrsb w8, [sp, #9]
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #11]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #13]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #13]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, lt
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -971,49 +971,49 @@ define i8 @sminv_v16i8(<16 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrsb w8, [sp, #1]
; NONEON-NOSVE-NEXT: ldrsb w9, [sp]
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #2]
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #3]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #4]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #5]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #6]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #5]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #9]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #11]
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #11]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %a)
@@ -1041,87 +1041,87 @@ define i8 @sminv_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: ldrsb w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #18]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #18]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #2]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #19]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #21]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #5]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #22]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #22]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #23]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #25]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #26]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #26]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #27]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #29]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsb w9, [sp, #30]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #30]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #14]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsb w10, [sp, #31]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
@@ -1152,13 +1152,13 @@ define i16 @sminv_v4i16(<4 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrsh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %a)
@@ -1180,23 +1180,23 @@ define i16 @sminv_v8i16(<8 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrsh w8, [sp, #2]
; NONEON-NOSVE-NEXT: ldrsh w9, [sp]
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #4]
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #10]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
+; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lt
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, lt
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -1226,39 +1226,39 @@ define i16 @sminv_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: ldrsh w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, lt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #22]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #26]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
+; NONEON-NOSVE-NEXT: ldrsh w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
; NONEON-NOSVE-NEXT: ldrsh w10, [sp, #30]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lt
; NONEON-NOSVE-NEXT: ldrsh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
@@ -1308,13 +1308,13 @@ define i32 @sminv_v4i32(<4 x i32> %a) {
; NONEON-NOSVE-NEXT: str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldp w9, w8, [sp]
+; NONEON-NOSVE-NEXT: ldp w10, w11, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
-; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lt
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lt
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lt
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a)
@@ -1342,8 +1342,8 @@ define i32 @sminv_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lt
; NONEON-NOSVE-NEXT: cmp w11, w10
; NONEON-NOSVE-NEXT: csel w9, w11, w10, lt
-; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: ldp w11, w12, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lt
; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
@@ -1432,23 +1432,23 @@ define i8 @umaxv_v8i8(<8 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #9]
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #11]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #13]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #13]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, hi
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -1472,49 +1472,49 @@ define i8 @umaxv_v16i8(<16 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #1]
; NONEON-NOSVE-NEXT: ldrb w9, [sp]
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #2]
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #3]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #4]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #5]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #6]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #5]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #9]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #11]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #11]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, hi
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, hi
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a)
@@ -1542,87 +1542,87 @@ define i8 @umaxv_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: ldrb w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #18]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #18]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #2]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #19]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #21]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #5]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #22]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #22]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #23]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #25]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #26]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #26]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #27]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #29]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #30]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #30]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #14]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #31]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
@@ -1653,13 +1653,13 @@ define i16 @umaxv_v4i16(<4 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldrh w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, hi
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, hi
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a)
@@ -1681,23 +1681,23 @@ define i16 @umaxv_v8i16(<8 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #2]
; NONEON-NOSVE-NEXT: ldrh w9, [sp]
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #4]
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrh w10, [sp, #10]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: ldrh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, hi
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, hi
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -1727,39 +1727,39 @@ define i16 @umaxv_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: ldrh w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, hi
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #22]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #26]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #30]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, hi
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
@@ -1809,13 +1809,13 @@ define i32 @umaxv_v4i32(<4 x i32> %a) {
; NONEON-NOSVE-NEXT: str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldp w9, w8, [sp]
+; NONEON-NOSVE-NEXT: ldp w10, w11, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
-; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, hi
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, hi
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, hi
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a)
@@ -1843,8 +1843,8 @@ define i32 @umaxv_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: cmp w11, w10
; NONEON-NOSVE-NEXT: csel w9, w11, w10, hi
-; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: ldp w11, w12, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
@@ -1933,23 +1933,23 @@ define i8 @uminv_v8i8(<8 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #9]
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #11]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #13]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #13]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, lo
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -1973,49 +1973,49 @@ define i8 @uminv_v16i8(<16 x i8> %a) {
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #1]
; NONEON-NOSVE-NEXT: ldrb w9, [sp]
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #2]
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #3]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #4]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #5]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #6]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #5]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #9]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #11]
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrb w10, [sp, #11]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #14]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrb w9, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lo
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lo
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %a)
@@ -2043,87 +2043,87 @@ define i8 @uminv_v32i8(ptr %a) {
; NONEON-NOSVE-NEXT: ldrb w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #18]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #18]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #2]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #19]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #3]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #21]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #5]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #22]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #22]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #23]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #7]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #25]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #9]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #26]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #26]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #10]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #27]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #11]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #29]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #13]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrb w9, [sp, #30]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrb w10, [sp, #30]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #14]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrb w10, [sp, #31]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrb w11, [sp, #15]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
@@ -2154,13 +2154,13 @@ define i16 @uminv_v4i16(<4 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldrh w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lo
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lo
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %a)
@@ -2182,23 +2182,23 @@ define i16 @uminv_v8i16(<8 x i16> %a) {
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #2]
; NONEON-NOSVE-NEXT: ldrh w9, [sp]
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #4]
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #6]
-; NONEON-NOSVE-NEXT: cmp w8, w10
-; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #10]
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #12]
+; NONEON-NOSVE-NEXT: ldrh w10, [sp, #10]
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #12]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: ldrh w9, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w8, w8, w11, lo
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w0, w8, w9, lo
; NONEON-NOSVE-NEXT: add sp, sp, #16
@@ -2228,39 +2228,39 @@ define i16 @uminv_v16i16(ptr %a) {
; NONEON-NOSVE-NEXT: ldrh w11, [sp]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #20]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #4]
-; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w10, w8
+; NONEON-NOSVE-NEXT: csel w8, w10, w8, lo
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #22]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #24]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #8]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #26]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #10]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #28]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w10, w11, w10, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
-; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
+; NONEON-NOSVE-NEXT: cmp w8, w10
+; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #30]
+; NONEON-NOSVE-NEXT: cmp w11, w9
+; NONEON-NOSVE-NEXT: csel w9, w11, w9, lo
; NONEON-NOSVE-NEXT: ldrh w11, [sp, #14]
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
@@ -2310,13 +2310,13 @@ define i32 @uminv_v4i32(<4 x i32> %a) {
; NONEON-NOSVE-NEXT: str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldp w9, w8, [sp]
+; NONEON-NOSVE-NEXT: ldp w10, w11, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
-; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #8]
; NONEON-NOSVE-NEXT: cmp w8, w10
; NONEON-NOSVE-NEXT: csel w8, w8, w10, lo
-; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: csel w0, w8, w9, lo
+; NONEON-NOSVE-NEXT: cmp w8, w11
+; NONEON-NOSVE-NEXT: csel w0, w8, w11, lo
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a)
@@ -2344,8 +2344,8 @@ define i32 @uminv_v8i32(ptr %a) {
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: cmp w11, w10
; NONEON-NOSVE-NEXT: csel w9, w11, w10, lo
-; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: ldp w11, w12, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
; NONEON-NOSVE-NEXT: ldp w10, w9, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w11, w10
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
index 9f4737a5d3408..6261c22e295cd 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
@@ -318,148 +318,148 @@ define void @select_v32i8(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: ldrb w12, [sp, #35]
; NONEON-NOSVE-NEXT: ldrb w13, [sp, #19]
; NONEON-NOSVE-NEXT: cmp w9, w8
-; NONEON-NOSVE-NEXT: ldrb w14, [sp, #36]
-; NONEON-NOSVE-NEXT: ldrb w16, [sp, #20]
; NONEON-NOSVE-NEXT: csel w8, w9, w8, eq
+; NONEON-NOSVE-NEXT: ldrb w14, [sp, #20]
; NONEON-NOSVE-NEXT: cmp w11, w10
-; NONEON-NOSVE-NEXT: ldrb w18, [sp, #37]
; NONEON-NOSVE-NEXT: csel w9, w11, w10, eq
-; NONEON-NOSVE-NEXT: cmp w13, w12
-; NONEON-NOSVE-NEXT: ldrb w1, [sp, #21]
+; NONEON-NOSVE-NEXT: ldrb w11, [sp, #36]
; NONEON-NOSVE-NEXT: str w8, [sp, #12] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrb w16, [sp, #37]
+; NONEON-NOSVE-NEXT: ldrb w18, [sp, #21]
+; NONEON-NOSVE-NEXT: cmp w13, w12
; NONEON-NOSVE-NEXT: csel w8, w13, w12, eq
-; NONEON-NOSVE-NEXT: cmp w16, w14
-; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #4] // 8-byte Folded Spill
-; NONEON-NOSVE-NEXT: csel w8, w16, w14, eq
-; NONEON-NOSVE-NEXT: cmp w1, w18
; NONEON-NOSVE-NEXT: ldrb w13, [sp, #38]
+; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #4] // 8-byte Folded Spill
+; NONEON-NOSVE-NEXT: cmp w14, w11
+; NONEON-NOSVE-NEXT: csel w8, w14, w11, eq
; NONEON-NOSVE-NEXT: ldrb w14, [sp, #22]
-; NONEON-NOSVE-NEXT: csel w12, w1, w18, eq
+; NONEON-NOSVE-NEXT: cmp w18, w16
+; NONEON-NOSVE-NEXT: csel w12, w18, w16, eq
; NONEON-NOSVE-NEXT: ldrb w16, [sp, #39]
; NONEON-NOSVE-NEXT: ldrb w18, [sp, #23]
; NONEON-NOSVE-NEXT: ldrb w1, [sp, #40]
; NONEON-NOSVE-NEXT: cmp w14, w13
-; NONEON-NOSVE-NEXT: ldrb w2, [sp, #24]
-; NONEON-NOSVE-NEXT: ldrb w4, [sp, #25]
; NONEON-NOSVE-NEXT: csel w13, w14, w13, eq
+; NONEON-NOSVE-NEXT: ldrb w2, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w18, w16
-; NONEON-NOSVE-NEXT: ldrb w6, [sp, #27]
; NONEON-NOSVE-NEXT: csel w14, w18, w16, eq
; NONEON-NOSVE-NEXT: ldrb w18, [sp, #41]
+; NONEON-NOSVE-NEXT: ldrb w4, [sp, #25]
; NONEON-NOSVE-NEXT: cmp w2, w1
; NONEON-NOSVE-NEXT: csel w16, w2, w1, eq
; NONEON-NOSVE-NEXT: ldrb w1, [sp, #42]
; NONEON-NOSVE-NEXT: ldrb w2, [sp, #26]
+; NONEON-NOSVE-NEXT: ldrb w6, [sp, #27]
; NONEON-NOSVE-NEXT: cmp w4, w18
-; NONEON-NOSVE-NEXT: ldrb w28, [sp, #44]
-; NONEON-NOSVE-NEXT: ldrb w29, [sp, #28]
; NONEON-NOSVE-NEXT: csel w18, w4, w18, eq
; NONEON-NOSVE-NEXT: ldrb w4, [sp, #43]
; NONEON-NOSVE-NEXT: cmp w2, w1
-; NONEON-NOSVE-NEXT: str w8, [sp] // 4-byte Spill
; NONEON-NOSVE-NEXT: csel w1, w2, w1, eq
-; NONEON-NOSVE-NEXT: ldrb w30, [sp, #45]
-; NONEON-NOSVE-NEXT: cmp w6, w4
+; NONEON-NOSVE-NEXT: ldrb w29, [sp, #44]
+; NONEON-NOSVE-NEXT: ldrb w30, [sp, #28]
+; NONEON-NOSVE-NEXT: str w8, [sp] // 4-byte Spill
+; NONEON-NOSVE-NEXT: ldrb w28, [sp, #45]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #29]
-; NONEON-NOSVE-NEXT: ldrb w7, [sp, #46]
+; NONEON-NOSVE-NEXT: cmp w6, w4
; NONEON-NOSVE-NEXT: csel w2, w6, w4, eq
+; NONEON-NOSVE-NEXT: ldrb w7, [sp, #46]
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #30]
-; NONEON-NOSVE-NEXT: cmp w29, w28
+; NONEON-NOSVE-NEXT: cmp w30, w29
+; NONEON-NOSVE-NEXT: csel w4, w30, w29, eq
; NONEON-NOSVE-NEXT: stp q2, q3, [sp, #48]
; NONEON-NOSVE-NEXT: ldrb w20, [sp, #47]
-; NONEON-NOSVE-NEXT: csel w4, w29, w28, eq
-; NONEON-NOSVE-NEXT: ldrb w28, [sp, #31]
-; NONEON-NOSVE-NEXT: cmp w8, w30
+; NONEON-NOSVE-NEXT: ldrb w29, [sp, #31]
+; NONEON-NOSVE-NEXT: cmp w8, w28
+; NONEON-NOSVE-NEXT: csel w6, w8, w28, eq
; NONEON-NOSVE-NEXT: ldrb w22, [sp, #64]
-; NONEON-NOSVE-NEXT: csel w6, w8, w30, eq
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #48]
; NONEON-NOSVE-NEXT: cmp w9, w7
-; NONEON-NOSVE-NEXT: ldrb w27, [sp, #65]
; NONEON-NOSVE-NEXT: csel w7, w9, w7, eq
+; NONEON-NOSVE-NEXT: ldrb w27, [sp, #65]
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #49]
-; NONEON-NOSVE-NEXT: cmp w28, w20
+; NONEON-NOSVE-NEXT: cmp w29, w20
+; NONEON-NOSVE-NEXT: csel w20, w29, w20, eq
; NONEON-NOSVE-NEXT: ldrb w26, [sp, #66]
-; NONEON-NOSVE-NEXT: ldrb w25, [sp, #67]
-; NONEON-NOSVE-NEXT: csel w20, w28, w20, eq
; NONEON-NOSVE-NEXT: ldrb w28, [sp, #50]
; NONEON-NOSVE-NEXT: cmp w8, w22
; NONEON-NOSVE-NEXT: csel w22, w8, w22, eq
+; NONEON-NOSVE-NEXT: ldrb w25, [sp, #67]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #51]
; NONEON-NOSVE-NEXT: cmp w9, w27
-; NONEON-NOSVE-NEXT: ldrb w24, [sp, #68]
; NONEON-NOSVE-NEXT: csel w11, w9, w27, eq
+; NONEON-NOSVE-NEXT: ldrb w24, [sp, #68]
; NONEON-NOSVE-NEXT: ldrb w27, [sp, #52]
; NONEON-NOSVE-NEXT: cmp w28, w26
-; NONEON-NOSVE-NEXT: ldrb w23, [sp, #69]
-; NONEON-NOSVE-NEXT: ldrb w21, [sp, #70]
; NONEON-NOSVE-NEXT: csel w26, w28, w26, eq
+; NONEON-NOSVE-NEXT: ldrb w23, [sp, #69]
; NONEON-NOSVE-NEXT: ldrb w28, [sp, #53]
; NONEON-NOSVE-NEXT: cmp w8, w25
; NONEON-NOSVE-NEXT: csel w10, w8, w25, eq
+; NONEON-NOSVE-NEXT: ldrb w21, [sp, #70]
; NONEON-NOSVE-NEXT: ldrb w25, [sp, #54]
; NONEON-NOSVE-NEXT: cmp w27, w24
-; NONEON-NOSVE-NEXT: ldrb w19, [sp, #71]
; NONEON-NOSVE-NEXT: csel w24, w27, w24, eq
+; NONEON-NOSVE-NEXT: ldrb w19, [sp, #71]
; NONEON-NOSVE-NEXT: ldrb w27, [sp, #55]
; NONEON-NOSVE-NEXT: cmp w28, w23
-; NONEON-NOSVE-NEXT: ldrb w5, [sp, #72]
-; NONEON-NOSVE-NEXT: ldrb w3, [sp, #73]
; NONEON-NOSVE-NEXT: csel w23, w28, w23, eq
+; NONEON-NOSVE-NEXT: ldrb w5, [sp, #72]
; NONEON-NOSVE-NEXT: ldrb w28, [sp, #56]
; NONEON-NOSVE-NEXT: cmp w25, w21
; NONEON-NOSVE-NEXT: csel w21, w25, w21, eq
+; NONEON-NOSVE-NEXT: ldrb w3, [sp, #73]
; NONEON-NOSVE-NEXT: ldrb w25, [sp, #57]
; NONEON-NOSVE-NEXT: cmp w27, w19
-; NONEON-NOSVE-NEXT: ldrb w17, [sp, #74]
; NONEON-NOSVE-NEXT: csel w19, w27, w19, eq
+; NONEON-NOSVE-NEXT: ldrb w17, [sp, #74]
; NONEON-NOSVE-NEXT: ldrb w27, [sp, #58]
; NONEON-NOSVE-NEXT: cmp w28, w5
-; NONEON-NOSVE-NEXT: ldrb w15, [sp, #75]
-; NONEON-NOSVE-NEXT: ldrb w29, [sp, #61]
; NONEON-NOSVE-NEXT: csel w5, w28, w5, eq
-; NONEON-NOSVE-NEXT: cmp w25, w3
+; NONEON-NOSVE-NEXT: ldrb w15, [sp, #75]
; NONEON-NOSVE-NEXT: ldrb w28, [sp, #59]
+; NONEON-NOSVE-NEXT: cmp w25, w3
; NONEON-NOSVE-NEXT: csel w3, w25, w3, eq
-; NONEON-NOSVE-NEXT: cmp w27, w17
; NONEON-NOSVE-NEXT: ldrb w25, [sp, #76]
+; NONEON-NOSVE-NEXT: cmp w27, w17
; NONEON-NOSVE-NEXT: csel w17, w27, w17, eq
-; NONEON-NOSVE-NEXT: ldrb w27, [sp, #60]
+; NONEON-NOSVE-NEXT: ldrb w29, [sp, #60]
; NONEON-NOSVE-NEXT: cmp w28, w15
; NONEON-NOSVE-NEXT: csel w15, w28, w15, eq
-; NONEON-NOSVE-NEXT: ldrb w28, [sp, #77]
+; NONEON-NOSVE-NEXT: ldrb w27, [sp, #77]
+; NONEON-NOSVE-NEXT: ldrb w28, [sp, #61]
; NONEON-NOSVE-NEXT: ldrb w30, [sp, #62]
-; NONEON-NOSVE-NEXT: cmp w27, w25
+; NONEON-NOSVE-NEXT: cmp w29, w25
+; NONEON-NOSVE-NEXT: csel w25, w29, w25, eq
+; NONEON-NOSVE-NEXT: ldrb w29, [sp, #78]
+; NONEON-NOSVE-NEXT: cmp w28, w27
+; NONEON-NOSVE-NEXT: csel w27, w28, w27, eq
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #79]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #63]
-; NONEON-NOSVE-NEXT: csel w25, w27, w25, eq
-; NONEON-NOSVE-NEXT: ldrb w27, [sp, #78]
-; NONEON-NOSVE-NEXT: cmp w29, w28
-; NONEON-NOSVE-NEXT: csel w28, w29, w28, eq
+; NONEON-NOSVE-NEXT: cmp w30, w29
+; NONEON-NOSVE-NEXT: csel w28, w30, w29, eq
; NONEON-NOSVE-NEXT: strb w10, [sp, #99]
; NONEON-NOSVE-NEXT: ldrb w29, [sp, #16]
-; NONEON-NOSVE-NEXT: cmp w30, w27
-; NONEON-NOSVE-NEXT: strb w28, [sp, #109]
-; NONEON-NOSVE-NEXT: csel w27, w30, w27, eq
; NONEON-NOSVE-NEXT: cmp w8, w9
-; NONEON-NOSVE-NEXT: strb w25, [sp, #108]
; NONEON-NOSVE-NEXT: csel w8, w8, w9, eq
; NONEON-NOSVE-NEXT: ldrb w9, [sp, #32]
-; NONEON-NOSVE-NEXT: strb w27, [sp, #110]
; NONEON-NOSVE-NEXT: strb w8, [sp, #111]
-; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #128] // 16-byte Folded Reload
; NONEON-NOSVE-NEXT: ldp w10, w8, [sp] // 8-byte Folded Reload
; NONEON-NOSVE-NEXT: cmp w29, w9
-; NONEON-NOSVE-NEXT: strb w15, [sp, #107]
-; NONEON-NOSVE-NEXT: strb w17, [sp, #106]
+; NONEON-NOSVE-NEXT: strb w28, [sp, #110]
+; NONEON-NOSVE-NEXT: strb w27, [sp, #109]
+; NONEON-NOSVE-NEXT: ldp x28, x27, [sp, #128] // 16-byte Folded Reload
; NONEON-NOSVE-NEXT: strb w10, [sp, #84]
; NONEON-NOSVE-NEXT: strb w8, [sp, #83]
; NONEON-NOSVE-NEXT: ldp w10, w8, [sp, #8] // 8-byte Folded Reload
-; NONEON-NOSVE-NEXT: strb w3, [sp, #105]
-; NONEON-NOSVE-NEXT: strb w5, [sp, #104]
+; NONEON-NOSVE-NEXT: strb w25, [sp, #108]
+; NONEON-NOSVE-NEXT: strb w15, [sp, #107]
; NONEON-NOSVE-NEXT: strb w8, [sp, #81]
; NONEON-NOSVE-NEXT: csel w8, w29, w9, eq
-; NONEON-NOSVE-NEXT: strb w19, [sp, #103]
+; NONEON-NOSVE-NEXT: strb w17, [sp, #106]
; NONEON-NOSVE-NEXT: ldp x29, x30, [sp, #112] // 16-byte Folded Reload
+; NONEON-NOSVE-NEXT: strb w3, [sp, #105]
+; NONEON-NOSVE-NEXT: strb w5, [sp, #104]
+; NONEON-NOSVE-NEXT: strb w19, [sp, #103]
; NONEON-NOSVE-NEXT: strb w21, [sp, #102]
; NONEON-NOSVE-NEXT: strb w23, [sp, #101]
; NONEON-NOSVE-NEXT: strb w24, [sp, #100]
@@ -511,19 +511,19 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) {
; NONEON-NOSVE-NEXT: sub sp, sp, #32
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
; NONEON-NOSVE-NEXT: stp d1, d2, [sp, #8]
-; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #16]
+; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #16]
; NONEON-NOSVE-NEXT: str d0, [sp]
; NONEON-NOSVE-NEXT: ldr w10, [sp, #12]
; NONEON-NOSVE-NEXT: ldr w11, [sp, #4]
-; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
; NONEON-NOSVE-NEXT: sbfx w9, w9, #0, #1
-; NONEON-NOSVE-NEXT: cmp w8, #0
-; NONEON-NOSVE-NEXT: csel w8, w11, w10, ne
-; NONEON-NOSVE-NEXT: ldr w10, [sp]
+; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
; NONEON-NOSVE-NEXT: cmp w9, #0
-; NONEON-NOSVE-NEXT: str w8, [sp, #28]
-; NONEON-NOSVE-NEXT: ldr w8, [sp, #8]
-; NONEON-NOSVE-NEXT: csel w8, w10, w8, ne
+; NONEON-NOSVE-NEXT: csel w9, w11, w10, ne
+; NONEON-NOSVE-NEXT: ldr w10, [sp]
+; NONEON-NOSVE-NEXT: str w9, [sp, #28]
+; NONEON-NOSVE-NEXT: ldr w9, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, #0
+; NONEON-NOSVE-NEXT: csel w8, w10, w9, ne
; NONEON-NOSVE-NEXT: str w8, [sp, #24]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
; NONEON-NOSVE-NEXT: add sp, sp, #32
@@ -691,77 +691,77 @@ define void @select_v16i16(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: ldrh w14, [sp, #22]
; NONEON-NOSVE-NEXT: ldrh w15, [sp, #6]
; NONEON-NOSVE-NEXT: cmp w9, w8
+; NONEON-NOSVE-NEXT: csel w8, w9, w8, eq
; NONEON-NOSVE-NEXT: ldrh w16, [sp, #24]
; NONEON-NOSVE-NEXT: ldrh w17, [sp, #8]
-; NONEON-NOSVE-NEXT: csel w8, w9, w8, eq
; NONEON-NOSVE-NEXT: cmp w13, w12
-; NONEON-NOSVE-NEXT: ldrh w1, [sp, #12]
; NONEON-NOSVE-NEXT: csel w9, w13, w12, eq
; NONEON-NOSVE-NEXT: cmp w15, w14
+; NONEON-NOSVE-NEXT: csel w14, w15, w14, eq
; NONEON-NOSVE-NEXT: ldrh w12, [sp, #26]
; NONEON-NOSVE-NEXT: ldrh w13, [sp, #10]
-; NONEON-NOSVE-NEXT: csel w14, w15, w14, eq
; NONEON-NOSVE-NEXT: cmp w17, w16
-; NONEON-NOSVE-NEXT: csel w16, w17, w16, eq
-; NONEON-NOSVE-NEXT: ldrh w17, [sp, #28]
+; NONEON-NOSVE-NEXT: csel w15, w17, w16, eq
+; NONEON-NOSVE-NEXT: ldrh w18, [sp, #28]
+; NONEON-NOSVE-NEXT: ldrh w1, [sp, #12]
; NONEON-NOSVE-NEXT: stp q2, q3, [sp, #32]
; NONEON-NOSVE-NEXT: cmp w13, w12
+; NONEON-NOSVE-NEXT: csel w12, w13, w12, eq
; NONEON-NOSVE-NEXT: ldrh w3, [sp, #30]
; NONEON-NOSVE-NEXT: ldrh w4, [sp, #14]
-; NONEON-NOSVE-NEXT: csel w12, w13, w12, eq
-; NONEON-NOSVE-NEXT: cmp w1, w17
-; NONEON-NOSVE-NEXT: ldrh w5, [sp, #32]
-; NONEON-NOSVE-NEXT: csel w17, w1, w17, eq
+; NONEON-NOSVE-NEXT: cmp w1, w18
+; NONEON-NOSVE-NEXT: csel w18, w1, w18, eq
; NONEON-NOSVE-NEXT: ldrh w1, [sp, #48]
-; NONEON-NOSVE-NEXT: cmp w4, w3
+; NONEON-NOSVE-NEXT: ldrh w5, [sp, #32]
; NONEON-NOSVE-NEXT: ldrh w6, [sp, #50]
; NONEON-NOSVE-NEXT: ldrh w7, [sp, #34]
-; NONEON-NOSVE-NEXT: ldrh w2, [sp, #52]
+; NONEON-NOSVE-NEXT: cmp w4, w3
; NONEON-NOSVE-NEXT: csel w3, w4, w3, eq
+; NONEON-NOSVE-NEXT: ldrh w2, [sp, #52]
; NONEON-NOSVE-NEXT: ldrh w4, [sp, #36]
; NONEON-NOSVE-NEXT: cmp w5, w1
-; NONEON-NOSVE-NEXT: ldrh w13, [sp, #54]
; NONEON-NOSVE-NEXT: csel w1, w5, w1, eq
+; NONEON-NOSVE-NEXT: ldrh w13, [sp, #54]
; NONEON-NOSVE-NEXT: ldrh w5, [sp, #38]
; NONEON-NOSVE-NEXT: cmp w7, w6
-; NONEON-NOSVE-NEXT: ldrh w18, [sp, #56]
-; NONEON-NOSVE-NEXT: ldrh w15, [sp, #58]
; NONEON-NOSVE-NEXT: csel w6, w7, w6, eq
+; NONEON-NOSVE-NEXT: ldrh w17, [sp, #56]
; NONEON-NOSVE-NEXT: ldrh w7, [sp, #40]
; NONEON-NOSVE-NEXT: cmp w4, w2
; NONEON-NOSVE-NEXT: csel w2, w4, w2, eq
+; NONEON-NOSVE-NEXT: ldrh w16, [sp, #58]
; NONEON-NOSVE-NEXT: ldrh w4, [sp, #42]
; NONEON-NOSVE-NEXT: cmp w5, w13
-; NONEON-NOSVE-NEXT: ldrh w11, [sp, #60]
; NONEON-NOSVE-NEXT: csel w13, w5, w13, eq
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #60]
; NONEON-NOSVE-NEXT: ldrh w5, [sp, #44]
-; NONEON-NOSVE-NEXT: cmp w7, w18
+; NONEON-NOSVE-NEXT: cmp w7, w17
+; NONEON-NOSVE-NEXT: csel w17, w7, w17, eq
; NONEON-NOSVE-NEXT: ldrh w10, [sp, #62]
-; NONEON-NOSVE-NEXT: strh w8, [sp, #66]
-; NONEON-NOSVE-NEXT: csel w18, w7, w18, eq
-; NONEON-NOSVE-NEXT: cmp w4, w15
; NONEON-NOSVE-NEXT: ldrh w7, [sp, #46]
-; NONEON-NOSVE-NEXT: csel w15, w4, w15, eq
+; NONEON-NOSVE-NEXT: cmp w4, w16
+; NONEON-NOSVE-NEXT: csel w16, w4, w16, eq
; NONEON-NOSVE-NEXT: cmp w5, w11
-; NONEON-NOSVE-NEXT: ldrh w4, [sp, #16]
; NONEON-NOSVE-NEXT: csel w11, w5, w11, eq
+; NONEON-NOSVE-NEXT: ldrh w4, [sp, #16]
; NONEON-NOSVE-NEXT: ldrh w5, [sp]
; NONEON-NOSVE-NEXT: cmp w7, w10
; NONEON-NOSVE-NEXT: csel w10, w7, w10, eq
-; NONEON-NOSVE-NEXT: strh w11, [sp, #92]
+; NONEON-NOSVE-NEXT: strh w8, [sp, #66]
; NONEON-NOSVE-NEXT: cmp w5, w4
-; NONEON-NOSVE-NEXT: strh w10, [sp, #94]
; NONEON-NOSVE-NEXT: csel w8, w5, w4, eq
-; NONEON-NOSVE-NEXT: strh w15, [sp, #90]
-; NONEON-NOSVE-NEXT: strh w18, [sp, #88]
+; NONEON-NOSVE-NEXT: strh w10, [sp, #94]
+; NONEON-NOSVE-NEXT: strh w11, [sp, #92]
+; NONEON-NOSVE-NEXT: strh w16, [sp, #90]
+; NONEON-NOSVE-NEXT: strh w17, [sp, #88]
; NONEON-NOSVE-NEXT: strh w13, [sp, #86]
; NONEON-NOSVE-NEXT: strh w2, [sp, #84]
; NONEON-NOSVE-NEXT: strh w6, [sp, #82]
; NONEON-NOSVE-NEXT: strh w1, [sp, #80]
; NONEON-NOSVE-NEXT: strh w3, [sp, #78]
-; NONEON-NOSVE-NEXT: strh w17, [sp, #76]
+; NONEON-NOSVE-NEXT: strh w18, [sp, #76]
; NONEON-NOSVE-NEXT: strh w12, [sp, #74]
-; NONEON-NOSVE-NEXT: strh w16, [sp, #72]
+; NONEON-NOSVE-NEXT: strh w15, [sp, #72]
; NONEON-NOSVE-NEXT: strh w14, [sp, #70]
; NONEON-NOSVE-NEXT: strh w9, [sp, #68]
; NONEON-NOSVE-NEXT: strh w8, [sp, #64]
@@ -793,19 +793,19 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) {
; NONEON-NOSVE-NEXT: sub sp, sp, #32
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
; NONEON-NOSVE-NEXT: stp d1, d2, [sp, #8]
-; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #16]
+; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #16]
; NONEON-NOSVE-NEXT: str d0, [sp]
; NONEON-NOSVE-NEXT: ldr w10, [sp, #12]
; NONEON-NOSVE-NEXT: ldr w11, [sp, #4]
-; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
; NONEON-NOSVE-NEXT: sbfx w9, w9, #0, #1
-; NONEON-NOSVE-NEXT: cmp w8, #0
-; NONEON-NOSVE-NEXT: csel w8, w11, w10, ne
-; NONEON-NOSVE-NEXT: ldr w10, [sp]
+; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
; NONEON-NOSVE-NEXT: cmp w9, #0
-; NONEON-NOSVE-NEXT: str w8, [sp, #28]
-; NONEON-NOSVE-NEXT: ldr w8, [sp, #8]
-; NONEON-NOSVE-NEXT: csel w8, w10, w8, ne
+; NONEON-NOSVE-NEXT: csel w9, w11, w10, ne
+; NONEON-NOSVE-NEXT: ldr w10, [sp]
+; NONEON-NOSVE-NEXT: str w9, [sp, #28]
+; NONEON-NOSVE-NEXT: ldr w9, [sp, #8]
+; NONEON-NOSVE-NEXT: cmp w8, #0
+; NONEON-NOSVE-NEXT: csel w8, w10, w9, ne
; NONEON-NOSVE-NEXT: str w8, [sp, #24]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
; NONEON-NOSVE-NEXT: add sp, sp, #32
@@ -831,33 +831,33 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) {
; NONEON-NOSVE-NEXT: sub sp, sp, #64
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
; NONEON-NOSVE-NEXT: str d2, [sp, #40]
-; NONEON-NOSVE-NEXT: ldrh w9, [sp, #46]
+; NONEON-NOSVE-NEXT: ldrh w11, [sp, #46]
; NONEON-NOSVE-NEXT: stp q0, q1, [sp]
-; NONEON-NOSVE-NEXT: ldrh w11, [sp, #44]
+; NONEON-NOSVE-NEXT: ldrh w10, [sp, #44]
; NONEON-NOSVE-NEXT: ldr w12, [sp, #28]
; NONEON-NOSVE-NEXT: ldr w13, [sp, #12]
-; NONEON-NOSVE-NEXT: ldrh w10, [sp, #42]
-; NONEON-NOSVE-NEXT: sbfx w9, w9, #0, #1
+; NONEON-NOSVE-NEXT: ldrh w9, [sp, #42]
; NONEON-NOSVE-NEXT: sbfx w11, w11, #0, #1
-; NONEON-NOSVE-NEXT: ldrh w8, [sp, #40]
; NONEON-NOSVE-NEXT: sbfx w10, w10, #0, #1
-; NONEON-NOSVE-NEXT: cmp w9, #0
-; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
-; NONEON-NOSVE-NEXT: csel w9, w13, w12, ne
-; NONEON-NOSVE-NEXT: ldr w12, [sp, #8]
+; NONEON-NOSVE-NEXT: ldrh w8, [sp, #40]
+; NONEON-NOSVE-NEXT: sbfx w9, w9, #0, #1
; NONEON-NOSVE-NEXT: cmp w11, #0
-; NONEON-NOSVE-NEXT: str w9, [sp, #60]
-; NONEON-NOSVE-NEXT: ldr w9, [sp, #24]
-; NONEON-NOSVE-NEXT: ldr w11, [sp, #4]
-; NONEON-NOSVE-NEXT: csel w9, w12, w9, ne
+; NONEON-NOSVE-NEXT: csel w11, w13, w12, ne
+; NONEON-NOSVE-NEXT: ldr w12, [sp, #8]
+; NONEON-NOSVE-NEXT: str w11, [sp, #60]
+; NONEON-NOSVE-NEXT: ldr w11, [sp, #24]
; NONEON-NOSVE-NEXT: cmp w10, #0
+; NONEON-NOSVE-NEXT: sbfx w8, w8, #0, #1
+; NONEON-NOSVE-NEXT: csel w10, w12, w11, ne
+; NONEON-NOSVE-NEXT: ldr w11, [sp, #4]
+; NONEON-NOSVE-NEXT: str w10, [sp, #56]
+; NONEON-NOSVE-NEXT: ldr w10, [sp, #20]
+; NONEON-NOSVE-NEXT: cmp w9, #0
+; NONEON-NOSVE-NEXT: csel w9, w11, w10, ne
; NONEON-NOSVE-NEXT: ldr w10, [sp]
-; NONEON-NOSVE-NEXT: str w9, [sp, #56]
-; NONEON-NOSVE-NEXT: ldr w9, [sp, #20]
-; NONEON-NOSVE-NEXT: csel w9, w11, w9, ne
-; NONEON-NOSVE-NEXT: cmp w8, #0
; NONEON-NOSVE-NEXT: str w9, [sp, #52]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #16]
+; NONEON-NOSVE-NEXT: cmp w8, #0
; NONEON-NOSVE-NEXT: csel w8, w10, w9, ne
; NONEON-NOSVE-NEXT: str w8, [sp, #48]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
@@ -886,36 +886,37 @@ define void @select_v8i32(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-96]!
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
-; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #16]
-; NONEON-NOSVE-NEXT: ldp w10, w13, [sp, #4]
-; NONEON-NOSVE-NEXT: ldp w12, w11, [sp, #24]
+; NONEON-NOSVE-NEXT: ldp w8, w11, [sp, #20]
+; NONEON-NOSVE-NEXT: ldp w9, w12, [sp, #4]
; NONEON-NOSVE-NEXT: stp q2, q3, [sp, #32]
-; NONEON-NOSVE-NEXT: ldr w14, [sp, #12]
-; NONEON-NOSVE-NEXT: cmp w10, w9
-; NONEON-NOSVE-NEXT: csel w9, w10, w9, eq
-; NONEON-NOSVE-NEXT: cmp w13, w12
-; NONEON-NOSVE-NEXT: ldp w10, w16, [sp, #48]
-; NONEON-NOSVE-NEXT: csel w12, w13, w12, eq
-; NONEON-NOSVE-NEXT: cmp w14, w11
-; NONEON-NOSVE-NEXT: ldp w15, w13, [sp, #32]
-; NONEON-NOSVE-NEXT: csel w11, w14, w11, eq
-; NONEON-NOSVE-NEXT: ldp w17, w14, [sp, #56]
-; NONEON-NOSVE-NEXT: ldp w18, w1, [sp, #40]
-; NONEON-NOSVE-NEXT: cmp w15, w10
-; NONEON-NOSVE-NEXT: stp w12, w11, [sp, #72]
-; NONEON-NOSVE-NEXT: csel w10, w15, w10, eq
-; NONEON-NOSVE-NEXT: cmp w13, w16
-; NONEON-NOSVE-NEXT: ldr w15, [sp]
-; NONEON-NOSVE-NEXT: csel w13, w13, w16, eq
-; NONEON-NOSVE-NEXT: cmp w18, w17
-; NONEON-NOSVE-NEXT: csel w16, w18, w17, eq
-; NONEON-NOSVE-NEXT: cmp w1, w14
-; NONEON-NOSVE-NEXT: stp w10, w13, [sp, #80]
-; NONEON-NOSVE-NEXT: csel w10, w1, w14, eq
-; NONEON-NOSVE-NEXT: cmp w15, w8
-; NONEON-NOSVE-NEXT: csel w8, w15, w8, eq
-; NONEON-NOSVE-NEXT: stp w16, w10, [sp, #88]
-; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
+; NONEON-NOSVE-NEXT: ldr w13, [sp, #12]
+; NONEON-NOSVE-NEXT: ldp w15, w14, [sp, #48]
+; NONEON-NOSVE-NEXT: cmp w9, w8
+; NONEON-NOSVE-NEXT: csel w8, w9, w8, eq
+; NONEON-NOSVE-NEXT: ldr w18, [sp, #44]
+; NONEON-NOSVE-NEXT: cmp w12, w11
+; NONEON-NOSVE-NEXT: csel w9, w12, w11, eq
+; NONEON-NOSVE-NEXT: ldp w10, w12, [sp, #28]
+; NONEON-NOSVE-NEXT: ldp w17, w16, [sp, #56]
+; NONEON-NOSVE-NEXT: cmp w13, w10
+; NONEON-NOSVE-NEXT: csel w10, w13, w10, eq
+; NONEON-NOSVE-NEXT: ldp w11, w13, [sp, #36]
+; NONEON-NOSVE-NEXT: cmp w12, w15
+; NONEON-NOSVE-NEXT: csel w12, w12, w15, eq
+; NONEON-NOSVE-NEXT: ldr w15, [sp, #16]
+; NONEON-NOSVE-NEXT: stp w9, w10, [sp, #72]
+; NONEON-NOSVE-NEXT: cmp w11, w14
+; NONEON-NOSVE-NEXT: csel w11, w11, w14, eq
+; NONEON-NOSVE-NEXT: cmp w13, w17
+; NONEON-NOSVE-NEXT: csel w13, w13, w17, eq
+; NONEON-NOSVE-NEXT: stp w12, w11, [sp, #80]
+; NONEON-NOSVE-NEXT: cmp w18, w16
+; NONEON-NOSVE-NEXT: csel w14, w18, w16, eq
+; NONEON-NOSVE-NEXT: ldr w16, [sp]
+; NONEON-NOSVE-NEXT: stp w13, w14, [sp, #88]
+; NONEON-NOSVE-NEXT: cmp w16, w15
+; NONEON-NOSVE-NEXT: csel w9, w16, w15, eq
+; NONEON-NOSVE-NEXT: stp w9, w8, [sp, #64]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #64]
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #96
@@ -970,19 +971,19 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) {
; NONEON-NOSVE-NEXT: sub sp, sp, #64
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
; NONEON-NOSVE-NEXT: str d2, [sp, #40]
-; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #40]
+; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #40]
; NONEON-NOSVE-NEXT: stp q0, q1, [sp]
; NONEON-NOSVE-NEXT: ldr x10, [sp, #24]
; NONEON-NOSVE-NEXT: ldr x11, [sp, #8]
-; NONEON-NOSVE-NEXT: sbfx x8, x8, #0, #1
; NONEON-NOSVE-NEXT: sbfx x9, x9, #0, #1
-; NONEON-NOSVE-NEXT: cmp x8, #0
-; NONEON-NOSVE-NEXT: csel x8, x11, x10, ne
-; NONEON-NOSVE-NEXT: ldr x10, [sp]
+; NONEON-NOSVE-NEXT: sbfx x8, x8, #0, #1
; NONEON-NOSVE-NEXT: cmp x9, #0
-; NONEON-NOSVE-NEXT: str x8, [sp, #56]
-; NONEON-NOSVE-NEXT: ldr x8, [sp, #16]
-; NONEON-NOSVE-NEXT: csel x8, x10, x8, ne
+; NONEON-NOSVE-NEXT: csel x9, x11, x10, ne
+; NONEON-NOSVE-NEXT: ldr x10, [sp]
+; NONEON-NOSVE-NEXT: str x9, [sp, #56]
+; NONEON-NOSVE-NEXT: ldr x9, [sp, #16]
+; NONEON-NOSVE-NEXT: cmp x8, #0
+; NONEON-NOSVE-NEXT: csel x8, x10, x9, ne
; NONEON-NOSVE-NEXT: str x8, [sp, #48]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
; NONEON-NOSVE-NEXT: add sp, sp, #64
@@ -1019,13 +1020,13 @@ define void @select_v4i64(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: csel x8, x9, x8, eq
; NONEON-NOSVE-NEXT: cmp x10, x11
; NONEON-NOSVE-NEXT: csel x9, x10, x11, eq
-; NONEON-NOSVE-NEXT: ldr x10, [sp, #16]
-; NONEON-NOSVE-NEXT: ldr x11, [sp]
+; NONEON-NOSVE-NEXT: ldr x11, [sp, #16]
; NONEON-NOSVE-NEXT: cmp x13, x12
-; NONEON-NOSVE-NEXT: csel x12, x13, x12, eq
-; NONEON-NOSVE-NEXT: cmp x11, x10
-; NONEON-NOSVE-NEXT: stp x9, x12, [sp, #80]
-; NONEON-NOSVE-NEXT: csel x9, x11, x10, eq
+; NONEON-NOSVE-NEXT: csel x10, x13, x12, eq
+; NONEON-NOSVE-NEXT: ldr x12, [sp]
+; NONEON-NOSVE-NEXT: stp x9, x10, [sp, #80]
+; NONEON-NOSVE-NEXT: cmp x12, x11
+; NONEON-NOSVE-NEXT: csel x9, x12, x11, eq
; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #64]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #64]
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
index 593ec1113cc19..af88cc0d85eb1 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-gather-scatter.ll
@@ -51,12 +51,12 @@ define <2 x i64> @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
-; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2
+; NONEON-NOSVE-NEXT: mov w10, #2 // =0x2
; NONEON-NOSVE-NEXT: str q0, [sp, #112]
-; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #112]
+; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #112]
+; NONEON-NOSVE-NEXT: cmp x8, #0
+; NONEON-NOSVE-NEXT: csel x8, x10, xzr, eq
; NONEON-NOSVE-NEXT: cmp x9, #0
-; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq
-; NONEON-NOSVE-NEXT: cmp x10, #0
; NONEON-NOSVE-NEXT: csetm x9, eq
; NONEON-NOSVE-NEXT: sub w8, w8, w9
; NONEON-NOSVE-NEXT: strb w8, [sp, #140]
@@ -133,14 +133,14 @@ define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #96
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
-; NONEON-NOSVE-NEXT: ldr q1, [x0]
-; NONEON-NOSVE-NEXT: ldr q0, [x1]
-; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2
-; NONEON-NOSVE-NEXT: str q1, [sp, #64]
-; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #64]
+; NONEON-NOSVE-NEXT: ldr q0, [x0]
+; NONEON-NOSVE-NEXT: ldr q1, [x1]
+; NONEON-NOSVE-NEXT: mov w10, #2 // =0x2
+; NONEON-NOSVE-NEXT: str q0, [sp, #64]
+; NONEON-NOSVE-NEXT: ldp x9, x8, [sp, #64]
+; NONEON-NOSVE-NEXT: cmp x8, #0
+; NONEON-NOSVE-NEXT: csel x8, x10, xzr, eq
; NONEON-NOSVE-NEXT: cmp x9, #0
-; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq
-; NONEON-NOSVE-NEXT: cmp x10, #0
; NONEON-NOSVE-NEXT: csetm x9, eq
; NONEON-NOSVE-NEXT: sub w8, w8, w9
; NONEON-NOSVE-NEXT: strb w8, [sp, #92]
@@ -152,13 +152,13 @@ define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {
; NONEON-NOSVE-NEXT: add sp, sp, #96
; NONEON-NOSVE-NEXT: ret
; NONEON-NOSVE-NEXT: .LBB1_3: // %cond.store
-; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #32]
+; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #32]
; NONEON-NOSVE-NEXT: ldr x9, [sp, #32]
; NONEON-NOSVE-NEXT: ldr x10, [sp, #48]
; NONEON-NOSVE-NEXT: str x9, [x10]
; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB1_2
; NONEON-NOSVE-NEXT: .LBB1_4: // %cond.store1
-; NONEON-NOSVE-NEXT: stp q1, q0, [sp]
+; NONEON-NOSVE-NEXT: stp q0, q1, [sp]
; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr x9, [sp, #24]
; NONEON-NOSVE-NEXT: str x8, [x9]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
index fc7ffc447a9d0..dab0774df481e 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
@@ -277,8 +277,8 @@ define i1 @ptest_or_v16i1(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, hi
; NONEON-NOSVE-NEXT: and w9, w13, #0xff
-; NONEON-NOSVE-NEXT: and w10, w10, #0xff
; NONEON-NOSVE-NEXT: and w8, w8, #0xff
+; NONEON-NOSVE-NEXT: and w10, w10, #0xff
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, hi
; NONEON-NOSVE-NEXT: and w9, w16, #0xff
@@ -486,8 +486,8 @@ define i1 @ptest_and_v16i1(ptr %a, ptr %b) {
; NONEON-NOSVE-NEXT: cmp w9, w8
; NONEON-NOSVE-NEXT: csel w8, w9, w8, lo
; NONEON-NOSVE-NEXT: and w9, w13, #0xff
-; NONEON-NOSVE-NEXT: and w10, w10, #0xff
; NONEON-NOSVE-NEXT: and w8, w8, #0xff
+; NONEON-NOSVE-NEXT: and w10, w10, #0xff
; NONEON-NOSVE-NEXT: cmp w8, w9
; NONEON-NOSVE-NEXT: csel w8, w8, w9, lo
; NONEON-NOSVE-NEXT: and w9, w16, #0xff
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-compress.ll b/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
index dd3269963595f..3eef803a50d1b 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-compress.ll
@@ -190,9 +190,9 @@ define <vscale x 8 x i32> @test_compress_large(<vscale x 8 x i32> %vec, <vscale
; CHECK-SVE-NEXT: compact z1.s, p0, z1.s
; CHECK-SVE-NEXT: ptrue p0.s
; CHECK-SVE-NEXT: cmp x9, x8
-; CHECK-SVE-NEXT: str z0, [sp]
; CHECK-SVE-NEXT: csel x8, x9, x8, lo
; CHECK-SVE-NEXT: mov x9, sp
+; CHECK-SVE-NEXT: str z0, [sp]
; CHECK-SVE-NEXT: st1w { z1.s }, p0, [x9, x8, lsl #2]
; CHECK-SVE-NEXT: ldr z0, [sp]
; CHECK-SVE-NEXT: ldr z1, [sp, #1, mul vl]
@@ -218,9 +218,9 @@ define <vscale x 8 x i32> @test_compress_large(<vscale x 8 x i32> %vec, <vscale
; CHECK-SME2p2-NEXT: compact z1.s, p0, z1.s
; CHECK-SME2p2-NEXT: ptrue p0.s
; CHECK-SME2p2-NEXT: cmp x9, x8
-; CHECK-SME2p2-NEXT: str z0, [sp]
; CHECK-SME2p2-NEXT: csel x8, x9, x8, lo
; CHECK-SME2p2-NEXT: mov x9, sp
+; CHECK-SME2p2-NEXT: str z0, [sp]
; CHECK-SME2p2-NEXT: st1w { z1.s }, p0, [x9, x8, lsl #2]
; CHECK-SME2p2-NEXT: ld1w { z0.s, z1.s }, pn8/z, [sp]
; CHECK-SME2p2-NEXT: addvl sp, sp, #2
diff --git a/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll b/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
index 2451ea478ed71..777093bb9b0e1 100644
--- a/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
+++ b/llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
@@ -6,11 +6,11 @@ define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: add w9, w1, w0
; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: mov w10, #2 // =0x2
; CHECK-NEXT: orr w9, w9, #0x1
; CHECK-NEXT: and w9, w9, #0xffff
; CHECK-NEXT: cmp w9, #1024
-; CHECK-NEXT: mov w9, #2 // =0x2
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%add = add i16 %b, %a
%or = or i16 %add, 1
@@ -24,11 +24,11 @@ define zeroext i16 @overflow_sub(i16 zeroext %a, i16 zeroext %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: mov w10, #2 // =0x2
; CHECK-NEXT: orr w9, w9, #0x1
; CHECK-NEXT: and w9, w9, #0xffff
; CHECK-NEXT: cmp w9, #1024
-; CHECK-NEXT: mov w9, #2 // =0x2
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%add = sub i16 %a, %b
%or = or i16 %add, 1
@@ -42,11 +42,11 @@ define zeroext i16 @overflow_mul(i16 zeroext %a, i16 zeroext %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: mul w9, w1, w0
; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: mov w10, #2 // =0x2
; CHECK-NEXT: orr w9, w9, #0x1
; CHECK-NEXT: and w9, w9, #0xffff
; CHECK-NEXT: cmp w9, #1024
-; CHECK-NEXT: mov w9, #2 // =0x2
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%add = mul i16 %b, %a
%or = or i16 %add, 1
@@ -60,11 +60,11 @@ define zeroext i16 @overflow_shl(i16 zeroext %a, i16 zeroext %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: lsl w9, w0, w1
; CHECK-NEXT: mov w8, #5 // =0x5
+; CHECK-NEXT: mov w10, #2 // =0x2
; CHECK-NEXT: orr w9, w9, #0x1
; CHECK-NEXT: and w9, w9, #0xffff
; CHECK-NEXT: cmp w9, #1024
-; CHECK-NEXT: mov w9, #2 // =0x2
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%add = shl i16 %a, %b
%or = or i16 %add, 1
@@ -77,10 +77,10 @@ define i32 @overflow_add_no_consts(i8 zeroext %a, i8 zeroext %b, i8 zeroext %lim
; CHECK-LABEL: overflow_add_no_consts:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w1, w0
-; CHECK-NEXT: mov w9, #8 // =0x8
+; CHECK-NEXT: mov w9, #16 // =0x10
+; CHECK-NEXT: mov w10, #8 // =0x8
; CHECK-NEXT: cmp w2, w8, uxtb
-; CHECK-NEXT: mov w8, #16 // =0x10
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: csel w0, w10, w9, lo
; CHECK-NEXT: ret
%add = add i8 %b, %a
%cmp = icmp ugt i8 %add, %limit
@@ -93,10 +93,10 @@ define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: add w9, w1, w0
; CHECK-NEXT: mov w8, #16 // =0x10
+; CHECK-NEXT: mov w10, #8 // =0x8
; CHECK-NEXT: and w9, w9, #0xff
; CHECK-NEXT: cmp w9, #128
-; CHECK-NEXT: mov w9, #8 // =0x8
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%add = add i8 %b, %a
%cmp = icmp ugt i8 %add, -128
@@ -122,8 +122,8 @@ define i32 @unsafe_add_underflow(i8 zeroext %a) {
; CHECK-LABEL: unsafe_add_underflow:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16 // =0x10
-; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: mov w9, #8 // =0x8
+; CHECK-NEXT: cmp w0, #1
; CHECK-NEXT: csel w0, w9, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i8 %a, 1
@@ -135,8 +135,8 @@ define i32 @safe_add_underflow(i8 zeroext %a) {
; CHECK-LABEL: safe_add_underflow:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16 // =0x10
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w9, #8 // =0x8
+; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w0, w9, w8, eq
; CHECK-NEXT: ret
%cmp = icmp eq i8 %a, 0
@@ -147,11 +147,11 @@ define i32 @safe_add_underflow(i8 zeroext %a) {
define i32 @safe_add_underflow_neg(i8 zeroext %a) {
; CHECK-LABEL: safe_add_underflow_neg:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub w9, w0, #2
; CHECK-NEXT: mov w8, #16 // =0x10
+; CHECK-NEXT: sub w9, w0, #2
+; CHECK-NEXT: mov w10, #8 // =0x8
; CHECK-NEXT: cmp w9, #251
-; CHECK-NEXT: mov w9, #8 // =0x8
-; CHECK-NEXT: csel w0, w9, w8, lo
+; CHECK-NEXT: csel w0, w10, w8, lo
; CHECK-NEXT: ret
%add = add i8 %a, -2
%cmp = icmp ult i8 %add, -5
@@ -193,8 +193,8 @@ define i32 @safe_sub_underflow(i8 zeroext %a) {
; CHECK-LABEL: safe_sub_underflow:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #8 // =0x8
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w9, #16 // =0x10
+; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: csel w0, w9, w8, eq
; CHECK-NEXT: ret
%cmp.not = icmp eq i8 %a, 0
@@ -205,11 +205,11 @@ define i32 @safe_sub_underflow(i8 zeroext %a) {
define i32 @safe_sub_underflow_neg(i8 zeroext %a) {
; CHECK-LABEL: safe_sub_underflow_neg:
; CHECK: // %bb.0:
-; CHECK-NEXT: sub w9, w0, #4
; CHECK-NEXT: mov w8, #16 // =0x10
+; CHECK-NEXT: sub w9, w0, #4
+; CHECK-NEXT: mov w10, #8 // =0x8
; CHECK-NEXT: cmp w9, #250
-; CHECK-NEXT: mov w9, #8 // =0x8
-; CHECK-NEXT: csel w0, w9, w8, hi
+; CHECK-NEXT: csel w0, w10, w8, hi
; CHECK-NEXT: ret
%sub = add i8 %a, -4
%cmp = icmp ugt i8 %sub, -6
@@ -283,10 +283,10 @@ define i8 @convert_add_order(i8 zeroext %arg) {
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: sub w10, w9, #40
; CHECK-NEXT: cmp w10, #20
+; CHECK-NEXT: mov w10, #255 // =0xff
; CHECK-NEXT: cinc w8, w8, hs
; CHECK-NEXT: cmp w9, #50
-; CHECK-NEXT: mov w9, #255 // =0xff
-; CHECK-NEXT: csel w8, w8, w9, lo
+; CHECK-NEXT: csel w8, w8, w10, lo
; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret
%shl = or i8 %arg, 1
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat.ll b/llvm/test/CodeGen/AArch64/uadd_sat.ll
index 7a7906622fb9c..c2d77b34f0068 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat.ll
@@ -62,11 +62,11 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
define i8 @func8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: func8:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and w9, w0, #0xff
-; CHECK-SD-NEXT: mov w8, #255 // =0xff
-; CHECK-SD-NEXT: add w9, w9, w1, uxtb
-; CHECK-SD-NEXT: cmp w9, #255
-; CHECK-SD-NEXT: csel w0, w9, w8, lo
+; CHECK-SD-NEXT: and w8, w0, #0xff
+; CHECK-SD-NEXT: mov w9, #255 // =0xff
+; CHECK-SD-NEXT: add w8, w8, w1, uxtb
+; CHECK-SD-NEXT: cmp w8, #255
+; CHECK-SD-NEXT: csel w0, w8, w9, lo
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: func8:
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll b/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
index 5c81e3f20277a..8cf39ed701ebf 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
@@ -112,12 +112,12 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mul w8, w1, w2
; CHECK-GI-NEXT: and w9, w0, #0xf
-; CHECK-GI-NEXT: mov w10, #15 // =0xf
; CHECK-GI-NEXT: and w8, w8, #0xf
; CHECK-GI-NEXT: add w8, w9, w8
-; CHECK-GI-NEXT: and w9, w8, #0xf
-; CHECK-GI-NEXT: cmp w8, w9
-; CHECK-GI-NEXT: csel w0, w10, w8, ne
+; CHECK-GI-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NEXT: and w10, w8, #0xf
+; CHECK-GI-NEXT: cmp w8, w10
+; CHECK-GI-NEXT: csel w0, w9, w8, ne
; CHECK-GI-NEXT: ret
%a = mul i4 %y, %z
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
diff --git a/llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll b/llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll
index d5f516fb3aa27..2b45897c667a8 100644
--- a/llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll
+++ b/llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll
@@ -35,8 +35,8 @@ define i64 @underflow_compare_fold_i64_multi_use(i64 %a, i64 %b, ptr addrspace(1
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, x1
; CHECK-NEXT: cmp x8, x0
-; CHECK-NEXT: str x8, [x2]
; CHECK-NEXT: csel x0, x8, x0, lo
+; CHECK-NEXT: str x8, [x2]
; CHECK-NEXT: ret
%sub = sub i64 %a, %b
store i64 %sub, ptr addrspace(1) %ptr
@@ -76,8 +76,8 @@ define i32 @underflow_compare_fold_i32_multi_use(i32 %a, i32 %b, ptr addrspace(1
; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w0, w1
; CHECK-NEXT: cmp w8, w0
-; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: csel w0, w8, w0, lo
+; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%sub = sub i32 %a, %b
store i32 %sub, ptr addrspace(1) %ptr
diff --git a/llvm/test/CodeGen/AArch64/umul_fix_sat.ll b/llvm/test/CodeGen/AArch64/umul_fix_sat.ll
index f7ffb9ec61abf..8bf1238b0e62c 100644
--- a/llvm/test/CodeGen/AArch64/umul_fix_sat.ll
+++ b/llvm/test/CodeGen/AArch64/umul_fix_sat.ll
@@ -68,13 +68,13 @@ define i4 @func3(i4 %x, i4 %y) {
;
; CHECK-GI-LABEL: func3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w9, w0, #0xf
-; CHECK-GI-NEXT: and w10, w1, #0xf
-; CHECK-GI-NEXT: mov w8, #15 // =0xf
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: lsr w9, w9, #2
-; CHECK-GI-NEXT: cmp w9, #15
-; CHECK-GI-NEXT: csel w0, w9, w8, lo
+; CHECK-GI-NEXT: and w8, w0, #0xf
+; CHECK-GI-NEXT: and w9, w1, #0xf
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NEXT: lsr w8, w8, #2
+; CHECK-GI-NEXT: cmp w8, #15
+; CHECK-GI-NEXT: csel w0, w8, w9, lo
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 2)
ret i4 %tmp
@@ -138,12 +138,12 @@ define i4 @func6(i4 %x, i4 %y) {
;
; CHECK-GI-LABEL: func6:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: and w9, w0, #0xf
-; CHECK-GI-NEXT: and w10, w1, #0xf
-; CHECK-GI-NEXT: mov w8, #15 // =0xf
-; CHECK-GI-NEXT: mul w9, w9, w10
-; CHECK-GI-NEXT: cmp w9, #15
-; CHECK-GI-NEXT: csel w0, w9, w8, lo
+; CHECK-GI-NEXT: and w8, w0, #0xf
+; CHECK-GI-NEXT: and w9, w1, #0xf
+; CHECK-GI-NEXT: mul w8, w8, w9
+; CHECK-GI-NEXT: mov w9, #15 // =0xf
+; CHECK-GI-NEXT: cmp w8, #15
+; CHECK-GI-NEXT: csel w0, w8, w9, lo
; CHECK-GI-NEXT: ret
%tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 0)
ret i4 %tmp
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
index bb5aa1fd0684d..24342e3604b02 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
@@ -5,12 +5,12 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
; CHECK-LABEL: test_minsize:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #5 // =0x5
-; CHECK-NEXT: mov w9, #42 // =0x2a
+; CHECK-NEXT: mov w9, #-10 // =0xfffffff6
+; CHECK-NEXT: mov w10, #42 // =0x2a
; CHECK-NEXT: udiv w8, w0, w8
; CHECK-NEXT: add w8, w8, w8, lsl #2
; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
-; CHECK-NEXT: csel w0, w9, w8, eq
+; CHECK-NEXT: csel w0, w10, w9, eq
; CHECK-NEXT: ret
%rem = urem i32 %X, 5
%cmp = icmp eq i32 %rem, 0
@@ -23,12 +23,12 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone {
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429 // =0xcccd
; CHECK-NEXT: mov w9, #858993459 // =0x33333333
+; CHECK-NEXT: mov w10, #-10 // =0xfffffff6
; CHECK-NEXT: movk w8, #52428, lsl #16
+; CHECK-NEXT: mov w11, #42 // =0x2a
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: cmp w8, w9
-; CHECK-NEXT: mov w8, #-10 // =0xfffffff6
-; CHECK-NEXT: mov w9, #42 // =0x2a
-; CHECK-NEXT: csel w0, w9, w8, ls
+; CHECK-NEXT: csel w0, w11, w10, ls
; CHECK-NEXT: ret
%rem = urem i32 %X, 5
%cmp = icmp eq i32 %rem, 0
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
index c6617dbd20c2e..5e10029bc8485 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
@@ -158,29 +158,29 @@ define i8 @test_v9i8(<9 x i8> %a) nounwind {
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
; CHECK-GI-NEXT: umov w10, v0.b[2]
-; CHECK-GI-NEXT: fmov w11, s1
-; CHECK-GI-NEXT: cmp w8, w11, uxtb
; CHECK-GI-NEXT: umov w11, v0.b[3]
+; CHECK-GI-NEXT: umov w13, v0.b[4]
+; CHECK-GI-NEXT: fmov w12, s1
+; CHECK-GI-NEXT: cmp w8, w12, uxtb
; CHECK-GI-NEXT: csel w8, w8, w9, hi
-; CHECK-GI-NEXT: umov w9, v0.b[4]
+; CHECK-GI-NEXT: umov w9, v0.b[5]
; CHECK-GI-NEXT: cmp w10, w8, uxtb
; CHECK-GI-NEXT: csel w8, w8, w10, lo
-; CHECK-GI-NEXT: umov w10, v0.b[5]
+; CHECK-GI-NEXT: umov w10, v0.b[6]
; CHECK-GI-NEXT: cmp w11, w8, uxtb
; CHECK-GI-NEXT: csel w8, w8, w11, lo
-; CHECK-GI-NEXT: umov w11, v0.b[6]
+; CHECK-GI-NEXT: umov w11, v0.b[7]
+; CHECK-GI-NEXT: cmp w13, w8, uxtb
+; CHECK-GI-NEXT: csel w8, w8, w13, lo
+; CHECK-GI-NEXT: umov w12, v0.b[8]
; CHECK-GI-NEXT: cmp w9, w8, uxtb
; CHECK-GI-NEXT: csel w8, w8, w9, lo
-; CHECK-GI-NEXT: umov w9, v0.b[7]
; CHECK-GI-NEXT: cmp w10, w8, uxtb
; CHECK-GI-NEXT: csel w8, w8, w10, lo
-; CHECK-GI-NEXT: umov w10, v0.b[8]
; CHECK-GI-NEXT: cmp w11, w8, uxtb
; CHECK-GI-NEXT: csel w8, w8, w11, lo
-; CHECK-GI-NEXT: cmp w9, w8, uxtb
-; CHECK-GI-NEXT: csel w8, w8, w9, lo
-; CHECK-GI-NEXT: cmp w10, w8, uxtb
-; CHECK-GI-NEXT: csel w0, w8, w10, lo
+; CHECK-GI-NEXT: cmp w12, w8, uxtb
+; CHECK-GI-NEXT: csel w0, w8, w12, lo
; CHECK-GI-NEXT: ret
%b = call i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)
ret i8 %b
@@ -216,11 +216,11 @@ define i1 @test_v4i1(<4 x i1> %a) nounwind {
; CHECK-GI-NEXT: umov w11, v0.h[3]
; CHECK-GI-NEXT: and w12, w8, #0x1
; CHECK-GI-NEXT: and w13, w9, #0x1
+; CHECK-GI-NEXT: and w14, w10, #0x1
+; CHECK-GI-NEXT: and w15, w11, #0x1
; CHECK-GI-NEXT: cmp w12, w13
-; CHECK-GI-NEXT: and w12, w10, #0x1
-; CHECK-GI-NEXT: and w13, w11, #0x1
; CHECK-GI-NEXT: csel w8, w8, w9, hi
-; CHECK-GI-NEXT: cmp w12, w13
+; CHECK-GI-NEXT: cmp w14, w15
; CHECK-GI-NEXT: csel w9, w10, w11, hi
; CHECK-GI-NEXT: and w10, w8, #0x1
; CHECK-GI-NEXT: and w11, w9, #0x1
diff --git a/llvm/test/CodeGen/AArch64/vector-compress.ll b/llvm/test/CodeGen/AArch64/vector-compress.ll
index 55c343164a1b8..8c5fb73e2b894 100644
--- a/llvm/test/CodeGen/AArch64/vector-compress.ll
+++ b/llvm/test/CodeGen/AArch64/vector-compress.ll
@@ -35,45 +35,46 @@ define <4 x i32> @test_compress_v4i32(<4 x i32> %vec, <4 x i1> %mask) {
define <4 x i32> @test_compress_v4i32_with_passthru(<4 x i32> %vec, <4 x i1> %mask, <4 x i32> %passthru) {
; CHECK-LABEL: test_compress_v4i32_with_passthru:
; CHECK: ; %bb.0:
-; CHECK-NEXT: str q2, [sp, #-16]!
+; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: movi.4s v3, #1
+; CHECK-NEXT: mov x11, sp
; CHECK-NEXT: mov x12, sp
; CHECK-NEXT: mov x10, sp
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: mov x14, sp
-; CHECK-NEXT: mov w15, #3 ; =0x3
+; CHECK-NEXT: str q2, [sp]
+; CHECK-NEXT: mov x13, sp
; CHECK-NEXT: shl.4s v1, v1, #31
; CHECK-NEXT: cmlt.4s v1, v1, #0
; CHECK-NEXT: and.16b v3, v1, v3
; CHECK-NEXT: mov.s w8, v1[1]
-; CHECK-NEXT: fmov w16, s1
-; CHECK-NEXT: mov.s w11, v1[2]
-; CHECK-NEXT: mov.s w13, v1[3]
-; CHECK-NEXT: addv.4s s2, v3
-; CHECK-NEXT: bfi x12, x16, #2, #1
-; CHECK-NEXT: and x16, x16, #0x1
+; CHECK-NEXT: mov.s w14, v1[2]
+; CHECK-NEXT: mov.s w15, v1[3]
+; CHECK-NEXT: addv.4s s3, v3
; CHECK-NEXT: and x8, x8, #0x1
-; CHECK-NEXT: add x8, x16, x8
-; CHECK-NEXT: and x11, x11, #0x1
-; CHECK-NEXT: and x13, x13, #0x1
-; CHECK-NEXT: fmov w16, s2
-; CHECK-NEXT: add x11, x8, x11
-; CHECK-NEXT: orr x8, x9, x8, lsl #2
-; CHECK-NEXT: add x13, x11, x13
-; CHECK-NEXT: bfi x14, x11, #2, #2
-; CHECK-NEXT: cmp x13, #3
-; CHECK-NEXT: bfi x10, x16, #2, #2
-; CHECK-NEXT: mov.s w16, v0[3]
-; CHECK-NEXT: csel x11, x13, x15, lo
-; CHECK-NEXT: ldr w10, [x10]
+; CHECK-NEXT: and x14, x14, #0x1
+; CHECK-NEXT: and x15, x15, #0x1
+; CHECK-NEXT: fmov w9, s3
+; CHECK-NEXT: bfi x11, x9, #2, #2
+; CHECK-NEXT: fmov w9, s1
+; CHECK-NEXT: ldr w11, [x11]
; CHECK-NEXT: str s0, [sp]
+; CHECK-NEXT: bfi x12, x9, #2, #1
+; CHECK-NEXT: and x9, x9, #0x1
+; CHECK-NEXT: add x8, x9, x8
+; CHECK-NEXT: mov.s w9, v0[3]
+; CHECK-NEXT: add x14, x8, x14
; CHECK-NEXT: st1.s { v0 }[1], [x12]
+; CHECK-NEXT: mov w12, #3 ; =0x3
+; CHECK-NEXT: orr x8, x10, x8, lsl #2
+; CHECK-NEXT: add x15, x14, x15
+; CHECK-NEXT: bfi x13, x14, #2, #2
+; CHECK-NEXT: cmp x15, #3
+; CHECK-NEXT: csel x12, x15, x12, lo
; CHECK-NEXT: st1.s { v0 }[2], [x8]
-; CHECK-NEXT: orr x8, x9, x11, lsl #2
-; CHECK-NEXT: csel w9, w16, w10, hi
-; CHECK-NEXT: st1.s { v0 }[3], [x14]
+; CHECK-NEXT: orr x8, x10, x12, lsl #2
+; CHECK-NEXT: csel w9, w9, w11, hi
+; CHECK-NEXT: st1.s { v0 }[3], [x13]
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ldr q0, [sp], #16
; CHECK-NEXT: ret
@@ -477,45 +478,45 @@ define <4 x i32> @test_compress_knownbits_zext_v4i16_4i32(<4 x i16> %vec, <4 x i
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: movi.4s v3, #1
-; CHECK-NEXT: mov x14, sp
+; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: movi.4s v4, #3
+; CHECK-NEXT: mov x11, sp
; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: mov x13, sp
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov x12, sp
-; CHECK-NEXT: mov x15, sp
; CHECK-NEXT: shl.4s v1, v1, #31
; CHECK-NEXT: and.16b v2, v2, v4
; CHECK-NEXT: cmlt.4s v1, v1, #0
; CHECK-NEXT: str q2, [sp]
; CHECK-NEXT: and.16b v3, v1, v3
-; CHECK-NEXT: mov.s w8, v1[1]
-; CHECK-NEXT: mov.s w9, v1[2]
-; CHECK-NEXT: mov.s w10, v1[3]
-; CHECK-NEXT: fmov w11, s1
-; CHECK-NEXT: addv.4s s1, v3
-; CHECK-NEXT: and x16, x11, #0x1
-; CHECK-NEXT: and x8, x8, #0x1
-; CHECK-NEXT: bfi x14, x11, #2, #1
-; CHECK-NEXT: add x8, x16, x8
+; CHECK-NEXT: mov.s w9, v1[1]
+; CHECK-NEXT: mov.s w13, v1[2]
+; CHECK-NEXT: mov.s w15, v1[3]
+; CHECK-NEXT: addv.4s s3, v3
; CHECK-NEXT: and x9, x9, #0x1
-; CHECK-NEXT: and x10, x10, #0x1
-; CHECK-NEXT: fmov w11, s1
-; CHECK-NEXT: add x9, x8, x9
-; CHECK-NEXT: mov w16, #3 ; =0x3
-; CHECK-NEXT: add x10, x9, x10
-; CHECK-NEXT: orr x8, x12, x8, lsl #2
-; CHECK-NEXT: bfi x15, x9, #2, #2
-; CHECK-NEXT: cmp x10, #3
-; CHECK-NEXT: bfi x13, x11, #2, #2
-; CHECK-NEXT: mov.s w11, v0[3]
-; CHECK-NEXT: csel x9, x10, x16, lo
-; CHECK-NEXT: ldr w13, [x13]
+; CHECK-NEXT: and x13, x13, #0x1
+; CHECK-NEXT: and x15, x15, #0x1
+; CHECK-NEXT: fmov w14, s3
+; CHECK-NEXT: bfi x10, x14, #2, #2
+; CHECK-NEXT: fmov w14, s1
+; CHECK-NEXT: ldr w10, [x10]
; CHECK-NEXT: str s0, [sp]
-; CHECK-NEXT: st1.s { v0 }[1], [x14]
-; CHECK-NEXT: st1.s { v0 }[2], [x8]
-; CHECK-NEXT: orr x8, x12, x9, lsl #2
-; CHECK-NEXT: csel w9, w11, w13, hi
-; CHECK-NEXT: st1.s { v0 }[3], [x15]
+; CHECK-NEXT: bfi x11, x14, #2, #1
+; CHECK-NEXT: and x14, x14, #0x1
+; CHECK-NEXT: add x9, x14, x9
+; CHECK-NEXT: mov.s w14, v0[3]
+; CHECK-NEXT: add x13, x9, x13
+; CHECK-NEXT: st1.s { v0 }[1], [x11]
+; CHECK-NEXT: mov w11, #3 ; =0x3
+; CHECK-NEXT: add x15, x13, x15
+; CHECK-NEXT: orr x9, x8, x9, lsl #2
+; CHECK-NEXT: bfi x12, x13, #2, #2
+; CHECK-NEXT: cmp x15, #3
+; CHECK-NEXT: csel x11, x15, x11, lo
+; CHECK-NEXT: orr x8, x8, x11, lsl #2
+; CHECK-NEXT: st1.s { v0 }[2], [x9]
+; CHECK-NEXT: csel w9, w14, w10, hi
+; CHECK-NEXT: st1.s { v0 }[3], [x12]
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ldr q0, [sp], #16
; CHECK-NEXT: ret
@@ -533,45 +534,45 @@ define <4 x i32> @test_compress_numsignbits_sext_v4i16_4i32(<4 x i16> %vec, <4 x
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: movi.4s v3, #1
-; CHECK-NEXT: mov x14, sp
+; CHECK-NEXT: mov x10, sp
; CHECK-NEXT: movi.4s v4, #3
+; CHECK-NEXT: mov x11, sp
; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: mov x13, sp
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: mov x12, sp
-; CHECK-NEXT: mov x15, sp
; CHECK-NEXT: shl.4s v1, v1, #31
; CHECK-NEXT: and.16b v2, v2, v4
; CHECK-NEXT: cmlt.4s v1, v1, #0
; CHECK-NEXT: str q2, [sp]
; CHECK-NEXT: and.16b v3, v1, v3
-; CHECK-NEXT: mov.s w8, v1[1]
-; CHECK-NEXT: mov.s w9, v1[2]
-; CHECK-NEXT: mov.s w10, v1[3]
-; CHECK-NEXT: fmov w11, s1
-; CHECK-NEXT: addv.4s s1, v3
-; CHECK-NEXT: and x16, x11, #0x1
-; CHECK-NEXT: and x8, x8, #0x1
-; CHECK-NEXT: bfi x14, x11, #2, #1
-; CHECK-NEXT: add x8, x16, x8
+; CHECK-NEXT: mov.s w9, v1[1]
+; CHECK-NEXT: mov.s w13, v1[2]
+; CHECK-NEXT: mov.s w15, v1[3]
+; CHECK-NEXT: addv.4s s3, v3
; CHECK-NEXT: and x9, x9, #0x1
-; CHECK-NEXT: and x10, x10, #0x1
-; CHECK-NEXT: fmov w11, s1
-; CHECK-NEXT: add x9, x8, x9
-; CHECK-NEXT: mov w16, #3 ; =0x3
-; CHECK-NEXT: add x10, x9, x10
-; CHECK-NEXT: orr x8, x12, x8, lsl #2
-; CHECK-NEXT: bfi x15, x9, #2, #2
-; CHECK-NEXT: cmp x10, #3
-; CHECK-NEXT: bfi x13, x11, #2, #2
-; CHECK-NEXT: mov.s w11, v0[3]
-; CHECK-NEXT: csel x9, x10, x16, lo
-; CHECK-NEXT: ldr w13, [x13]
+; CHECK-NEXT: and x13, x13, #0x1
+; CHECK-NEXT: and x15, x15, #0x1
+; CHECK-NEXT: fmov w14, s3
+; CHECK-NEXT: bfi x10, x14, #2, #2
+; CHECK-NEXT: fmov w14, s1
+; CHECK-NEXT: ldr w10, [x10]
; CHECK-NEXT: str s0, [sp]
-; CHECK-NEXT: st1.s { v0 }[1], [x14]
-; CHECK-NEXT: st1.s { v0 }[2], [x8]
-; CHECK-NEXT: orr x8, x12, x9, lsl #2
-; CHECK-NEXT: csel w9, w11, w13, hi
-; CHECK-NEXT: st1.s { v0 }[3], [x15]
+; CHECK-NEXT: bfi x11, x14, #2, #1
+; CHECK-NEXT: and x14, x14, #0x1
+; CHECK-NEXT: add x9, x14, x9
+; CHECK-NEXT: mov.s w14, v0[3]
+; CHECK-NEXT: add x13, x9, x13
+; CHECK-NEXT: st1.s { v0 }[1], [x11]
+; CHECK-NEXT: mov w11, #3 ; =0x3
+; CHECK-NEXT: add x15, x13, x15
+; CHECK-NEXT: orr x9, x8, x9, lsl #2
+; CHECK-NEXT: bfi x12, x13, #2, #2
+; CHECK-NEXT: cmp x15, #3
+; CHECK-NEXT: csel x11, x15, x11, lo
+; CHECK-NEXT: orr x8, x8, x11, lsl #2
+; CHECK-NEXT: st1.s { v0 }[2], [x9]
+; CHECK-NEXT: csel w9, w14, w10, hi
+; CHECK-NEXT: st1.s { v0 }[3], [x12]
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ldr q0, [sp], #16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll b/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
index 2c7fd22622853..06e849e3f2e75 100644
--- a/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
@@ -570,8 +570,8 @@ define i8 @extract_last_active_split(<vscale x 32 x i8> %data, <vscale x 32 x i1
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: csel x8, x8, x9, lo
; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: ldrb w8, [x9, x8]
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: csel w0, w8, w0, ne
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/vselect-masked-shift.ll b/llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
index 2d5db9ad8b2f1..6969c41b6dd75 100644
--- a/llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-masked-shift.ll
@@ -175,12 +175,12 @@ define <1 x i128> @neg_masked_shl_v1i128(<1 x i128> %x, <1 x i128> %amt) {
; CHECK-NEXT: lsr x9, x0, #1
; CHECK-NEXT: lsl x11, x1, x2
; CHECK-NEXT: eor x10, x8, #0x3f
-; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: lsr x9, x9, x10
; CHECK-NEXT: lsl x10, x0, x2
; CHECK-NEXT: orr x9, x11, x9
-; CHECK-NEXT: csel x0, x10, xzr, lo
+; CHECK-NEXT: cmp x8, #128
; CHECK-NEXT: csel x1, x9, xzr, lo
+; CHECK-NEXT: csel x0, x10, xzr, lo
; CHECK-NEXT: ret
entry:
%m = and <1 x i128> %amt, splat (i128 63)
>From 2d9bb3ebc81ceae2c2340f476c4acf845a2fc2c3 Mon Sep 17 00:00:00 2001
From: Shanzhi Chen <chenshanzhi at huawei.com>
Date: Thu, 10 Sep 2026 11:47:45 +0800
Subject: [PATCH 3/3] Update tests
---
llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
index c838c08cd5e51..456118b37b215 100644
--- a/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
@@ -924,11 +924,11 @@ define i80 @fct20(i128 %a, i128 %b) {
; LLC-NEXT: mov w11, #26220 // =0x666c
; LLC-NEXT: movk x12, #11077, lsl #32
; LLC-NEXT: and x11, x8, x11
-; LLC-NEXT: cmp x10, #0
; LLC-NEXT: movk x12, #45, lsl #48
-; LLC-NEXT: csel x1, x11, x8, eq
; LLC-NEXT: and x12, x9, x12
+; LLC-NEXT: cmp x10, #0
; LLC-NEXT: csel x0, x12, x9, eq
+; LLC-NEXT: csel x1, x11, x8, eq
; LLC-NEXT: ret
; OPT-LABEL: @fct20(
; OPT-NEXT: entry:
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