[llvm] [AArch64] Enable CMP+CSEL fusion under Generic (PR #222280)
Shanzhi Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 02:36:24 PDT 2026
https://github.com/chenshanzhi created https://github.com/llvm/llvm-project/pull/222280
FeatureFuseCmpCSel is enabled under Generic, as many modern cores support this fusion and it has minimal performance impact on cores that do not support it.
>From 56a837cf883f1b7becee3561afe480df8ca50eed Mon Sep 17 00:00:00 2001
From: Shanzhi Chen <chenshanzhi at huawei.com>
Date: Wed, 9 Sep 2026 16:56:58 +0800
Subject: [PATCH] [AArch64] Enable CMP+CSEL fusion under Generic
FeatureFuseCmpCSel is enabled under Generic, as many modern cores
support this fusion and it has minimal performance impact on cores that
do not support it.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index f996522ba4d09..5eae632c3b03b 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1287,10 +1287,13 @@ def ProcessorFeatures {
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations. We use a fixed load latency of 4 as the a510 scheduling model
// has a latency of 2 for most loads which is disproportionately low for many
-// cpus.
+// cpus. FeatureFuseCmpCSel is enabled under Generic, as many modern cores
+// support this fusion and it has minimal performance impact on cores that do
+// not support it.
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
[FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
- FeatureEnableSelectOptimize, FeatureFixedLoadLatency4]>;
+ FeatureEnableSelectOptimize, FeatureFixedLoadLatency4,
+ FeatureFuseCmpCSel]>;
def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
[TuneA35]>;
def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
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