[llvm] [AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16 (PR #221960)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 04:29:02 PDT 2026
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/221960
>From 4418362e9226a50f9a3f2f1b03b36e44a0d29654 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 8 Sep 2026 18:47:43 +0800
Subject: [PATCH] [AMDGPU] Select trunc(srl x, 16) as hi16 subregister on
true16
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 6 +
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 12337 ++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 1397 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll | 34 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 2939 ++--
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 930 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 343 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll | 119 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 5486 ++++---
.../CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll | 1536 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 1680 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 840 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll | 1824 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 1968 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 2112 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 2256 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 2400 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 780 +-
.../atomic_optimizations_global_pointer.ll | 77 +-
.../AMDGPU/atomicrmw-bf16-gfx11plus.ll | 2 +-
llvm/test/CodeGen/AMDGPU/bf16-math.ll | 2 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 8978 +++++------
.../CodeGen/AMDGPU/bitcast_vector_bigint.ll | 5 -
llvm/test/CodeGen/AMDGPU/bitreverse.ll | 5 +-
.../buffer-fat-pointer-atomicrmw-fadd.ll | 132 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 90 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 90 +-
.../build-vector-packed-partial-undef.ll | 55 +-
.../CodeGen/AMDGPU/build_vector.gfx11plus.ll | 4 +-
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 14 +-
.../CodeGen/AMDGPU/combine_andor_with_cmps.ll | 32 +-
.../AMDGPU/combine_andor_with_cmps_nnan.ll | 32 +-
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 23 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 48 +-
.../AMDGPU/divergence-driven-buildvector.ll | 11 +-
.../CodeGen/AMDGPU/extract-hi16-true16.ll | 234 +
.../CodeGen/AMDGPU/extract-subvector-16bit.ll | 154 +-
.../CodeGen/AMDGPU/extract_vector_elt-f16.ll | 66 +-
llvm/test/CodeGen/AMDGPU/fabs.bf16.ll | 54 +-
llvm/test/CodeGen/AMDGPU/fabs.f16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 534 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 151 +-
llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fdiv.f16.ll | 10 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fadd.ll | 219 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 283 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 283 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fsub.ll | 283 +-
llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll | 36 +-
.../float-to-arbitrary-fp-fp8-f16-hw.ll | 216 +-
.../AMDGPU/float-to-arbitrary-fp-fp8-hw.ll | 50 +-
.../AMDGPU/float-to-arbitrary-fp-widen.ll | 2957 ++--
llvm/test/CodeGen/AMDGPU/fma.f16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll | 116 +-
llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll | 75 +-
llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll | 21 +-
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll | 116 +-
llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll | 75 +-
.../CodeGen/AMDGPU/fneg-modifier-casting.ll | 58 +-
.../AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll | 52 +-
llvm/test/CodeGen/AMDGPU/fpow.ll | 60 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 522 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 474 +-
llvm/test/CodeGen/AMDGPU/fract-match.ll | 285 +-
.../CodeGen/AMDGPU/frexp-inf-nan-combine.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fshr.ll | 126 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 252 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 280 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 280 +-
.../CodeGen/AMDGPU/global-atomicrmw-fsub.ll | 280 +-
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll | 67 +-
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll | 664 +-
llvm/test/CodeGen/AMDGPU/idot4s.ll | 60 +-
llvm/test/CodeGen/AMDGPU/idot4u.ll | 79 +-
.../AMDGPU/insert_vector_elt.v2bf16.ll | 140 +-
.../CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 191 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll | 51 +-
.../AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 228 +-
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll | 138 +-
llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll | 216 +-
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 44 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll | 28 +-
.../CodeGen/AMDGPU/llvm.is.fpclass.f16.ll | 25 +-
llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll | 39 +-
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 131 +-
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 131 +-
llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 46 +-
llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll | 264 +-
llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll | 264 +-
llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll | 332 +-
.../test/CodeGen/AMDGPU/load-atomic-global.ll | 808 +-
llvm/test/CodeGen/AMDGPU/load-atomic-local.ll | 796 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 60 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 108 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 108 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 108 +-
llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll | 24 +-
llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll | 11 +-
llvm/test/CodeGen/AMDGPU/mad-mix.ll | 24 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 5597 ++++---
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 5597 ++++---
llvm/test/CodeGen/AMDGPU/repeated-divisor.ll | 16 +-
llvm/test/CodeGen/AMDGPU/roundeven.ll | 14 +-
.../AMDGPU/scalar_to_vector.gfx11plus.ll | 4 +-
llvm/test/CodeGen/AMDGPU/scmp.ll | 16 +-
.../AMDGPU/select-fabs-fneg-extract.v2f16.ll | 438 +-
.../AMDGPU/select-flags-to-fmin-fmax.ll | 366 +-
llvm/test/CodeGen/AMDGPU/select.f16.ll | 280 +-
.../AMDGPU/sext-in-reg-vector-shuffle.ll | 24 +-
llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll | 21 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 21 +-
llvm/test/CodeGen/AMDGPU/strict_fpext.ll | 40 +-
llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll | 57 +-
llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll | 36 +-
llvm/test/CodeGen/AMDGPU/ucmp.ll | 16 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll | 44 +-
.../test/CodeGen/AMDGPU/vector-reduce-fadd.ll | 140 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmax.ll | 150 +-
.../CodeGen/AMDGPU/vector-reduce-fmaximum.ll | 219 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmin.ll | 150 +-
.../CodeGen/AMDGPU/vector-reduce-fminimum.ll | 219 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmul.ll | 140 +-
llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll | 10 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 42 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 42 +-
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 42 +-
.../test/CodeGen/AMDGPU/vector-reduce-umin.ll | 42 +-
.../test/CodeGen/AMDGPU/vector_rebroadcast.ll | 89 +-
.../CodeGen/AMDGPU/vector_shuffle.packed.ll | 269 +-
133 files changed, 30017 insertions(+), 46592 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index af08bf0861215a..193871bde2cb16 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3554,6 +3554,12 @@ def : GCNPat <
(EXTRACT_SUBREG $a, sub0)
>;
+let True16Predicate = UseRealTrue16Insts in
+def : GCNPat <
+ (i16 (DivergentUnaryFrag<trunc> (i32 (srl_oneuse VGPR_32:$src, (i32 16))))),
+ (EXTRACT_SUBREG VGPR_32:$src, hi16)
+>;
+
def : GCNPat <
(v2i32 (UniformUnaryFrag<trunc> v2i64:$a)),
(v2i32 (REG_SEQUENCE SReg_64,
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 7be6ad4575d694..aaa177348b323a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -7037,145 +7037,73 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32i32_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -7184,103 +7112,71 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
@@ -7336,188 +7232,188 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v74, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v72, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v61, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v43, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v56, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v46, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v39, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v182, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v180, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v52, v177, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v64, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v54, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v164, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v162, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v146, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v144, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v133, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v128, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v118, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v115, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v102, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v100, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v97, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v84, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v82, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v71, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -7525,28 +7421,6 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32i32_to_v128i8:
@@ -25128,569 +25002,631 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v32
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v63, v31 :: v_dual_mov_b32 v62, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v61, v29 :: v_dual_mov_b32 v60, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v59, v27 :: v_dual_mov_b32 v58, v26
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, v25 :: v_dual_mov_b32 v56, v24
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, v23 :: v_dual_mov_b32 v54, v22
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v21 :: v_dual_mov_b32 v52, v20
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, v19 :: v_dual_mov_b32 v50, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, v17 :: v_dual_mov_b32 v48, v16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v38, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v39, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v37 :: v_dual_and_b32 v35, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v33, v38 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v37 :: v_dual_and_b32 v36, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v34, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v0.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v63, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_lshlrev_b32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v34, v37 :: v_dual_and_b32 v37, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v32.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v33.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v19, v33, v35 :: v_dual_and_b32 v34, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v36, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v58, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v57, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v34, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v34, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v56, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v0, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v1, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB18_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v40 :: v_dual_mov_b32 v9, v41
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v42 :: v_dual_mov_b32 v11, v43
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v44 :: v_dual_mov_b32 v13, v45
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v46 :: v_dual_mov_b32 v15, v47
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v56 :: v_dual_mov_b32 v25, v57
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v58 :: v_dual_mov_b32 v27, v59
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v60 :: v_dual_mov_b32 v29, v61
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v62 :: v_dual_mov_b32 v31, v63
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:68
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -42142,145 +42078,73 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32f32_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -42289,103 +42153,71 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB36_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB36_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB36_4
@@ -42424,188 +42256,188 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB36_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v74, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v72, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v61, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v43, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v56, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v46, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v39, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v182, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v180, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v52, v177, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v64, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v54, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v164, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v162, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v146, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v144, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v133, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v128, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v118, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v115, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v102, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v100, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v97, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v84, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v82, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v71, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -42613,28 +42445,6 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32f32_to_v128i8:
@@ -61336,569 +61146,631 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v32f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v32
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v63, v31 :: v_dual_mov_b32 v62, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v61, v29 :: v_dual_mov_b32 v60, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v59, v27 :: v_dual_mov_b32 v58, v26
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, v25 :: v_dual_mov_b32 v56, v24
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, v23 :: v_dual_mov_b32 v54, v22
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v21 :: v_dual_mov_b32 v52, v20
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, v19 :: v_dual_mov_b32 v50, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, v17 :: v_dual_mov_b32 v48, v16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v38, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v39, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v37 :: v_dual_and_b32 v35, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v33, v38 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v37 :: v_dual_and_b32 v36, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v34, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v0.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v63, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_lshlrev_b32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v34, v37 :: v_dual_and_b32 v37, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v32.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v33.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v19, v33, v35 :: v_dual_and_b32 v34, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v36, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v58, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v57, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v34, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v34, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v56, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v0, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v1, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB42_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v40 :: v_dual_mov_b32 v9, v41
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v42 :: v_dual_mov_b32 v11, v43
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v44 :: v_dual_mov_b32 v13, v45
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v46 :: v_dual_mov_b32 v15, v47
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v56 :: v_dual_mov_b32 v25, v57
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v58 :: v_dual_mov_b32 v27, v59
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v60 :: v_dual_mov_b32 v29, v61
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v62 :: v_dual_mov_b32 v31, v63
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:68
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -76979,145 +76851,73 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16i64_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -77126,103 +76926,71 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB56_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_4
@@ -77286,188 +77054,188 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB56_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v74, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v72, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v61, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v43, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v56, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v46, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v39, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v182, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v180, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v52, v177, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v64, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v54, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v164, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v162, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v146, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v144, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v133, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v128, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v118, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v115, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v102, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v100, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v97, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v84, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v82, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v71, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -77475,28 +77243,6 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16i64_to_v128i8:
@@ -95134,569 +94880,631 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v32
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v63, v31 :: v_dual_mov_b32 v62, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v61, v29 :: v_dual_mov_b32 v60, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v59, v27 :: v_dual_mov_b32 v58, v26
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, v25 :: v_dual_mov_b32 v56, v24
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, v23 :: v_dual_mov_b32 v54, v22
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v21 :: v_dual_mov_b32 v52, v20
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, v19 :: v_dual_mov_b32 v50, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, v17 :: v_dual_mov_b32 v48, v16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v38, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB62_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v39, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v37 :: v_dual_and_b32 v35, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v33, v38 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v37 :: v_dual_and_b32 v36, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v34, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v0.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v63, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_lshlrev_b32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v34, v37 :: v_dual_and_b32 v37, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v32.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v33.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v19, v33, v35 :: v_dual_and_b32 v34, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v36, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v58, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v57, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v34, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v34, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: .LBB62_2: ; %end
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v56, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v0, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v1, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB62_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v40 :: v_dual_mov_b32 v9, v41
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v42 :: v_dual_mov_b32 v11, v43
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v44 :: v_dual_mov_b32 v13, v45
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v46 :: v_dual_mov_b32 v15, v47
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v56 :: v_dual_mov_b32 v25, v57
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v58 :: v_dual_mov_b32 v27, v59
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v60 :: v_dual_mov_b32 v29, v61
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v62 :: v_dual_mov_b32 v31, v63
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:68
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -109104,145 +108912,73 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16f64_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -109251,103 +108987,71 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB72_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB72_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB72_4
@@ -109386,188 +109090,188 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB72_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v74, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v72, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v61, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v59, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v43, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v67, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v65, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v56, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v46, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v65, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v39, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v66, v66, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v54, v64, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v64, v65, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v66, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v55, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v54, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v182, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v53, v180, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v52, v177, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v64, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v53, v54, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v53, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v54, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v164, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v162, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v146, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v144, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v133, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v131, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v128, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v118, v117, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v115, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v114, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v113, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v102, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v100, v99, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v97, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v84, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v82, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v71, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v69, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -109575,28 +109279,6 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:88
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16f64_to_v128i8:
@@ -128246,569 +127928,631 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v16f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v32
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB78_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v63, v31 :: v_dual_mov_b32 v62, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v61, v29 :: v_dual_mov_b32 v60, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v59, v27 :: v_dual_mov_b32 v58, v26
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, v25 :: v_dual_mov_b32 v56, v24
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, v23 :: v_dual_mov_b32 v54, v22
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v21 :: v_dual_mov_b32 v52, v20
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, v19 :: v_dual_mov_b32 v50, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, v17 :: v_dual_mov_b32 v48, v16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v38, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB78_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB78_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v35, v38 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v47, v36, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v39, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v32.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v34 :: v_dual_cndmask_b32 v46, v35, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v45, v33, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v37 :: v_dual_and_b32 v35, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v33, v38 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v37 :: v_dual_and_b32 v36, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v34, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v32 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v43, v15, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v14, v32, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v41, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v39, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_and_b32 v6, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v37, v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v8 :: v_dual_and_b32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v35, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v6 :: v_dual_and_b32 v2, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v1.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v0.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v63, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v62, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v62.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v61, v3, v7 :: v_dual_lshlrev_b32 v4, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v61.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v60, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_lshlrev_b32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_lshlrev_b32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v34, v37 :: v_dual_and_b32 v37, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v32.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v33.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v32, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v19, v33, v35 :: v_dual_and_b32 v34, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v36, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_f32 v34, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v59, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v59.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v60.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v25
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v58, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v58.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v57, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v34, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v34, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: .LBB78_2: ; %end
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v56, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v56.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v0.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v2.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v1.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v0, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v6, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v6 :: v_dual_cndmask_b32 v51, v0, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v5, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_add_f32 v1, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v0.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v1, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB78_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v40 :: v_dual_mov_b32 v9, v41
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v42 :: v_dual_mov_b32 v11, v43
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v44 :: v_dual_mov_b32 v13, v45
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v46 :: v_dual_mov_b32 v15, v47
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v56 :: v_dual_mov_b32 v25, v57
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v58 :: v_dual_mov_b32 v27, v59
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v60 :: v_dual_mov_b32 v29, v61
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v62 :: v_dual_mov_b32 v31, v63
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:68
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -155084,1008 +154828,1120 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:96
+; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:248
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:244
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:240
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:236
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:232
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:228
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:224
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:220
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:216
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:212
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:208
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:204
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:200
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:196
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:192
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:188
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:184
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:180
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:176
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:172
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:168
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:164
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:160
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:156
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:152
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:148
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:144
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:140
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:136
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:132
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:128
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:124
+; GFX11-TRUE16-NEXT: s_clause 0x1b ; 112-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:120
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:116
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:112
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:108
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:104
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:100
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:96
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:92
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:88
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:84
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:80
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:76
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:72
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:68
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:64
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:60
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:56
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:52
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:48
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:44
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:40
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:36
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:32
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:28
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
-; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v83, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_b32 v82, off, s32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr142_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr155_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr154_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr143_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v1
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v83
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v83
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v82
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[80:81], 24, v[82:83]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[29:30]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[27:28]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[113:114], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[129:130], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.h, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.h, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.h, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v88.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v139.h, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.h, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v109.h, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.h, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v153.h, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.h, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v141.h, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.h, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v155.h, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.h, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v154.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.h, v16.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.h, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.h, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v150.h, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.h, v20.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.h, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.h, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.h, v22.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.h, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.h, v23.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.h, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v24.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.h, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v25.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.h, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.h, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.h, v28.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v28.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v30.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v30.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v82.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v83.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83
; GFX11-TRUE16-NEXT: .LBB90_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v20
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v32 :: v_dual_add_f32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v31, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v38, v34, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v17, 16, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v37, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v70.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v38, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v37, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v39.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v34
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v119, v37, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v31, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v119.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v36, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v150, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v17, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v151, v17, v33 :: v_dual_and_b32 v18, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_cndmask_b32 v33, v20, v35
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v21, 0x40c00000, v21
; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v150.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v151.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v34
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 8, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v160, v19, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v17, v36, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v161, v17, v24, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v71.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v160.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v19, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v22, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v161.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v162, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v17, v24, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 8, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_and_b32 v37, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 24, v36
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v36
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v19, v24, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v37.l, v163.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v24, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 0x40c00000, v23 :: v_dual_add_f32 v26, 0x40c00000, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v164, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v49, v17, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v37
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v84.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v83.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v165, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_cndmask_b32 v48, v19, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v162.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v165.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v26, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v86.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v85.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v23
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v28, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_and_b32 v37, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v28, v33, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v87.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v96.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v25
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_and_b32 v37, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v34
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v51, v17, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[37:38]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v38
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_cndmask_b32 v50, v19, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v30, v33, v38 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_add_f32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v97.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v30
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v83
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v50.l, v167.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v176, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v83
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v53, v17, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_and_b32 v37, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v32, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v82
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v177, v17, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v82
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_cndmask_b32 v52, v19, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v164.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v177.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v17, v24, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v100.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v98.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v99.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 8, v29
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 8, v27
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v2, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v49
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v102.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v54.l, v179.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v20, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v180, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v17, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v48
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v181, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v2, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v166.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v64.l, v181.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v182, v2, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v67, v1, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[102:103], 24, v[50:51]
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v176.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v51
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v183, v1, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v2, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v66.l, v183.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v53
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v53
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v51
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v2, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v112.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v103.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v101.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 8, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v1, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v50
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v31
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v1, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v57, v3, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v35, v36 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v71, v1, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v57.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[84:85], 24, v[52:53]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v1, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v73, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v73.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v88, v1, v4 :: v_dual_lshlrev_b32 v1, 16, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v113.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v99, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v88.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v178.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[70:71]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v98, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[80:81], 24, v[54:55]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[31:32]
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v107, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v34
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v115.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v114.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 24, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v10, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v116.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v118.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v35, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v34, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v117.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v37, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v38, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v34, v36 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.h, v128.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v11.h, v130.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v33
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v119.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v14.h, v129.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 24, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 24, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v37, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v33
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v38, v37, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v13.h, v131.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v34, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v33, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v16.h, v132.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v15.h, v133.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v107.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v109, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v180.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v109.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[98:99]
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v117, v2, v3 :: v_dual_add_f32 v2, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v182.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v139, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v135, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v141, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v141.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v134, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v16
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v40.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v44.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v153, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v153.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v154, v2, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v117.l, v139.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[68:69]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v155, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[134:135]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[66:67]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[117:118]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v149, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.l, v154.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[146:147], 24, v[64:65]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[113:114], 24, v[35:36]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[129:130], 24, v[33:34]
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v148, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.l, v155.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 24, v149
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v149
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v135
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v135
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[148:149]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v148
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v134
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v118
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v118
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v117
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v99
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v99
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v98
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 24, v71
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 8, v71
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 8, v70
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 24, v69
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v69
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v68
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 24, v67
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v67
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 8, v66
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v65
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v65
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v64
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v55
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v55
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v54
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v52
; GFX11-TRUE16-NEXT: .LBB90_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v112, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v102, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v114, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v103, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v116, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v113, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v117, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v115, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v50, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v167, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v119, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v118, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v130, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v51, v128, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v55, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v1.l, v181.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v64.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v3.l, v180.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v65.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v183.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v152, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v142, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v140, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v67.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v44.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v68.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v5, v138, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v66.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v182.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v124, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v123, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v125, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v40.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v69.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v71.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v9, v122, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v10, v120, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v73.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v70.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v57.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v98.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v8, v106, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v9, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v10, v105, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v11, v104, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v107.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v88.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v117.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v11, v93, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v12, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v91, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v99.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v13.l, v139.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v109.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v118.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v89, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v78, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v51, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v131, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v129, v145, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v133, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v135, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v132, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v77, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v80, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v10, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v5.l, v153.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v6.l, v134.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v7.l, v141.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v8.l, v135.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v9.l, v155.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v10.l, v148.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v11.l, v154.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.l, v149.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v119.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v31.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v76, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v74, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v59, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v41, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v143, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v16, 16, v15
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v76, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v70, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v74, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v82, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v71, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v84, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v81, v58, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v39.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v12.l, v151.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v14.l, v150.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v34.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v16.l, v161.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v35.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v18.l, v160.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v137, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v136, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v127, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v126, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v121, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v111, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v110, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v108, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v86, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v83, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v96, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v85, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v98, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v15.l, v163.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v37.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v17.l, v162.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v38.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v19.l, v165.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v48.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v21.l, v164.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v49.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v23.l, v167.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v50.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v95, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v94, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v92, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v90, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v79, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v77, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v75, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v102, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v87, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v20.l, v166.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v51.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v100, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v164, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v97, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v101, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v99, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v22.l, v177.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v52.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v24.l, v176.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v53.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v26.l, v179.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v54.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.l, v178.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v55.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v63, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v58, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v45, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v42, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
@@ -156098,29 +155954,68 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:96
+; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:136
+; GFX11-TRUE16-NEXT: s_clause 0x1b ; 112-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:248
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -180174,149 +180069,73 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64f16_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:96
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:92
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -180325,339 +180144,307 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v17
; GFX11-TRUE16-NEXT: .LBB94_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v17
; GFX11-TRUE16-NEXT: .LBB94_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v45, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v179, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v176, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v161, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v135, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v132, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v35, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v1.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v65, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v51, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v55, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v65, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v50, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v117, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v113, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v99, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v51, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v65, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v51, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v55, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v51, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v86, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v84, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v81, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v71, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v77, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v76, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v74, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v63, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v61, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v58, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v56, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v42, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v181, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v167, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v150, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v145, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v130, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v128, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v51, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v114, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -180665,30 +180452,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:96
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v64f16_to_v128i8:
@@ -200987,149 +200750,73 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64i16_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:96
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:92
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -201138,339 +200825,307 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v17
; GFX11-TRUE16-NEXT: .LBB98_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[67:68], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[69:70], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[68:69], 24, v[17:18]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v17
; GFX11-TRUE16-NEXT: .LBB98_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v45, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v41, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v179, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v176, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v161, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v149, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v55, v135, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v64, v132, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v35, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v1.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v164, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v65, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v51, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v55, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v65, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v8.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v145, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v135, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v55, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v50, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v35, v117, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v39, v113, v103, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v50, v99, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v51, v97, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v9.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v65, v65, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v51, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v55, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v64, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v11.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v39, v39, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v65, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v52, v55, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v51, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v13, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v86, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v14, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v84, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v15, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v81, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v16, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v71, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v17, v77, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v76, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v18, v75, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v74, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v19, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v63, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v20, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v61, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v58, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v56, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v17, 16, v16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v19, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v23, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v42, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v181, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v25, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v167, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v26, v165, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v164, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v150, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v22, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v28, v147, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v145, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v24, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v29, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v130, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v30, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v128, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v39, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v15.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v51, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v52, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v12, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v13, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v14, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v15, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v16, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v17, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v150, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v19, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v20.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v11, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v21.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v22.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v23.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v20, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v21, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v22, v132, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v23, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v25.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v24, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v25, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v26, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v27, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v29.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v30.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v31, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v114, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v32, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v102, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v25, 16, v24
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v27, 16, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v28, v99, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v29, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v30, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v31, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v32, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v21, 16, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v24, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v27, 16, v29
; GFX11-TRUE16-NEXT: s_clause 0x5
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
@@ -201478,30 +201133,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112
-; GFX11-TRUE16-NEXT: s_clause 0x15 ; 88-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:96
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v64i16_to_v128i8:
@@ -209104,564 +208735,602 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v64f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:8
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v48, v16
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: scratch_load_b32 v16, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v62, v30 :: v_dual_mov_b32 v61, v29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v60, v28 :: v_dual_mov_b32 v59, v27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v58, v26 :: v_dual_mov_b32 v57, v25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v56, v24 :: v_dual_mov_b32 v55, v23
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, v22 :: v_dual_mov_b32 v53, v21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, v20 :: v_dual_mov_b32 v51, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, v18 :: v_dual_mov_b32 v49, v17
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v32
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB100_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v33, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v33
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v101, 0x400000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v32, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v47, v15 :: v_dual_mov_b32 v46, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, v13 :: v_dual_mov_b32 v44, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v43, v11 :: v_dual_mov_b32 v42, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, v9 :: v_dual_mov_b32 v40, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v38, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, v5 :: v_dual_mov_b32 v36, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, v3 :: v_dual_mov_b32 v34, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v48 :: v_dual_mov_b32 v17, v49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v50 :: v_dual_mov_b32 v19, v51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v52 :: v_dual_mov_b32 v21, v53
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v54 :: v_dual_mov_b32 v23, v55
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v56 :: v_dual_mov_b32 v25, v57
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v58 :: v_dual_mov_b32 v27, v59
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v60 :: v_dual_mov_b32 v29, v61
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v62 :: v_dual_mov_b32 v31, v63
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-TRUE16-NEXT: .LBB100_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB100_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v49
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v48
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v54
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v56
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v58
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v60
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v62
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v32
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v32, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v16, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v27, 16, v53
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v36, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v29, 16, v55
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v16, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v57
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v59
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v21, v22 :: v_dual_lshlrev_b32 v35, 16, v61
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v35, v36 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v35, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v35, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v38, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v36, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v38, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v51
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v63
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v23, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v39, v35, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v35
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v36, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v35, v38, v39 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v36, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v20 :: v_dual_lshlrev_b32 v25, 16, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v50
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v19, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v24, v26, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v37, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v39
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v37, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v38, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v52
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v48.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v24, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v49.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v24, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v25
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v48, v49, v37, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v37
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v38, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v21, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v37, v48, v49 :: v_dual_add_f32 v38, 0x40c00000, v38
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v38, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v26 :: v_dual_lshlrev_b32 v22, 16, v52
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v24, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v23, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v20, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v26, v21, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 0x40c00000, v23 :: v_dual_add_f32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v39, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v49
-; GFX11-TRUE16-NEXT: v_add3_u32 v48, v50, v38, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v39, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v37.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v48, v49, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v48, v50, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v53
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v51.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v20, v24 :: v_dual_add_f32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v25, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_add3_u32 v50, v51, v39, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v39
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v23, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v39, v50, v51 :: v_dual_add_f32 v48, 0x40c00000, v48
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v49, v49, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v48, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v21, v24, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_add_f32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v49, v50, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v49, 0x40c00000, v51
-; GFX11-TRUE16-NEXT: v_add3_u32 v50, v52, v48, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v48
-; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v49, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v39.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v50, v51, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v50, v52, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v25, v26, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 0x40c00000, v28 :: v_dual_lshlrev_b32 v24, 16, v54
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v26, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v25, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v55
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v26, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v50.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v22, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v28, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v53.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v27, v24, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v27, v28, v25, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v22, v26, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v29
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v52, v53, v49, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v50, v51, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v49, v52, v53 :: v_dual_add_f32 v50, 0x40c00000, v50
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v51, v51, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v50, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v23, v26, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v27 :: v_dual_add_f32 v26, 0x40c00000, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v49
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v51, v52, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v51, 0x40c00000, v53
-; GFX11-TRUE16-NEXT: v_add3_u32 v52, v54, v50, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v50
-; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v51, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v49.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v52, v53, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v52, v54, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v26
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v30 :: v_dual_lshlrev_b32 v26, 16, v56
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v24, v28, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v52.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v27, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v57
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v28
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v24, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v30, v25, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v27, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v55.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v25, v29, v26, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v24, v28, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v54, v55, v51, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v51
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v48.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v52, v53, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v27, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v51, v54, v55 :: v_dual_add_f32 v52, 0x40c00000, v52
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v53, v53, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v52, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v29, v30, v27, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v31
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v25, v28, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v29, 0x40c00000, v29 :: v_dual_add_f32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v53, v54, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v53, 0x40c00000, v55
-; GFX11-TRUE16-NEXT: v_add3_u32 v54, v64, v52, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v52
-; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v53, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v51.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v54, v55, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v54, v64, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v30, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v32 :: v_dual_lshlrev_b32 v28, 16, v58
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v54.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v29, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v59
+; GFX11-TRUE16-NEXT: v_add3_u32 v26, v26, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v30
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v27, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_f32 v29, 0x40c00000, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v26, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v26, v32, v27, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v65.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v27, v31, v28, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v26, v30, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v28
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v33
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v64, v65, v53, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v53
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v50.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v54, v55, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v29, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v64, v65 :: v_dual_add_f32 v54, 0x40c00000, v54
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v54, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v29
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v27, v30, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v31 :: v_dual_add_f32 v30, 0x40c00000, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v55, v64, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v55, 0x40c00000, v65
-; GFX11-TRUE16-NEXT: v_add3_u32 v64, v66, v54, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v54
-; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v55, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v52
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v53.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v64, v65, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v64, v66, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v30
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v29, 0x40c00000, v34 :: v_dual_lshlrev_b32 v30, 16, v60
+; GFX11-TRUE16-NEXT: v_add3_u32 v28, v28, v32, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v64.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v31, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v61
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v28, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v28, v34, v29, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v31, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v67.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v29, v33, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v28, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v30
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v66, v67, v55, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v55
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v54
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v64, v65, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v31, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v66, v67 :: v_dual_add_f32 v64, 0x40c00000, v64
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v64, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v31, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v35
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v29, v32, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v55
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v65, v66, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v65, 0x40c00000, v67
-; GFX11-TRUE16-NEXT: v_add3_u32 v66, v68, v64, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64
-; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v65, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v55.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v66, v67, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v66, v68, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v68, v69, v65, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v65
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v64
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v54.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v66, v67, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v52.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v34, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v36 :: v_dual_lshlrev_b32 v32, 16, v62
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v66.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v63
+; GFX11-TRUE16-NEXT: v_add3_u32 v30, v30, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v34
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v31, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_add_f32 v33, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v30, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v30, v36, v31, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v69.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v35, v32, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v36, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v30, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v37
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v33
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v65, v68, v69 :: v_dual_add_f32 v66, 0x40c00000, v66
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v66, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v65
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v67, v68, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v69
-; GFX11-TRUE16-NEXT: v_add3_u32 v68, v70, v66, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v66
-; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-TRUE16-NEXT: v_bfe_u32 v71, v67, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v65.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v68, v69, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v68, v70, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v36, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v31, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v38
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v0 :: v_dual_cndmask_b32 v31, v35, v37
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
+; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v38, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v68.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v37, v33, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v34, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v36, v38, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v37, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v38
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v33, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v37, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v71
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v37, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v36, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v34, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v70.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v71, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v71.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v38, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v70, v71, v67, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v67
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v66
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v68, v69, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v67, v70, v71 :: v_dual_add_f32 v68, 0x40c00000, v68
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v68, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v80
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v35, v38, v39 :: v_dual_and_b32 v38, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v36, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v67
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v69, v70, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v69, 0x40c00000, v71
-; GFX11-TRUE16-NEXT: v_add3_u32 v70, v80, v68, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v68
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v38 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v80, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
-; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v69, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v70, v71, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v70, v80, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v38, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v3.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v80, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v80, v81, v69, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v69
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v70, v71, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v71, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v69, v80, v81 :: v_dual_add_f32 v70, 0x40c00000, v70
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v71, v71, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v70, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v81, v38, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v38
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v82
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v37, v80, v81 :: v_dual_and_b32 v80, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v38, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v71, v80, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v71, 0x40c00000, v81
-; GFX11-TRUE16-NEXT: v_add3_u32 v80, v82, v70, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v70
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v39, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v82, v38, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v38
; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-TRUE16-NEXT: v_bfe_u32 v83, v71, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v68
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v80, v81, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v80, v82, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT: v_bfe_u32 v83, v80, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v5.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v39, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v82, v6, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v82, v83, v71, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v71
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v70
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v80, v81, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v82, v83, v80, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v80
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v39, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v71, v82, v83 :: v_dual_add_f32 v80, 0x40c00000, v80
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v84 :: v_dual_cndmask_b32 v39, v82, v83
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v81, v81, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v7
; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v80, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v71
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v81, v82, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v83
-; GFX11-TRUE16-NEXT: v_add3_u32 v82, v84, v80, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v81, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v81, v84, v80, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v80
; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v82, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
-; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v81, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v71.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v80, v82, v83, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v82, v84, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v7.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v82
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v81, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v85, v82, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v84, v85, v81, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v81
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v82, v83, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v83, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v81, v84, v85 :: v_dual_add_f32 v82, 0x40c00000, v82
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v83, v83, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v82, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v81
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v83, v84, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v83, 0x40c00000, v85
-; GFX11-TRUE16-NEXT: v_add3_u32 v84, v86, v82, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v82
-; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v2.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v9, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
-; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v83, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v81.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v84, v85, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v84, v86, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v85
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v83, v84, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v81, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.l, v8.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v82, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v81, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.l, v9.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v42, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v85, v82, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v86, v87, v83, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v83
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v82
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v80.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v84, v85, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v11, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v83, v86, v87 :: v_dual_add_f32 v84, 0x40c00000, v84
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v82
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v85, v85, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v84, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v85
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v43, v83, v84, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v81, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v13 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v83
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v85, v86, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v85, 0x40c00000, v87
-; GFX11-TRUE16-NEXT: v_add3_u32 v86, v96, v84, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v84
-; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
-; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v85, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v83.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v84, v86, v87, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v86, v96, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v42.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v4.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v81, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v82, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v43.l, v11.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v44, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v84, v12, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v96, v97, v85, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v97, 0x400000, v85
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v86, v87, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
-; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v13, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v86, 0x40c00000, v86 :: v_dual_cndmask_b32 v85, v96, v97
-; GFX11-TRUE16-NEXT: v_add3_u32 v87, v87, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v86, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v85
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v87, v96, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v96, v97, v86, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v97, 0x400000, v86
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v98
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v84
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v86, v96, v97, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v99, v87, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v85.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v86
-; GFX11-TRUE16-NEXT: v_add3_u32 v96, v96, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v85, v82, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v14
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v84.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v81, 0x40c00000, v85 :: v_dual_lshlrev_b32 v82, 16, v15
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v98, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v97, v98, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v98, v99, v87, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v99, 0x400000, v87
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v87, v98, v99, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v45, v83, v84, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v81, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v82, 0x40c00000, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v80, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v84, v81, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v82, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v97, v100, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v80, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v82
+; GFX11-TRUE16-NEXT: v_add3_u32 v84, v84, v82, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v80, v86, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.l, v13.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v87, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.l, v12.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v84, v96, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v6.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v83, v85, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v96, v101, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v86.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v87.l
-; GFX11-TRUE16-NEXT: .LBB100_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.l, v14.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v47, v80, v86, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v47.l, v82.h
+; GFX11-TRUE16-NEXT: .LBB100_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v40 :: v_dual_mov_b32 v9, v41
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v42 :: v_dual_mov_b32 v11, v43
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v44 :: v_dual_mov_b32 v13, v45
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v46 :: v_dual_mov_b32 v15, v47
+; GFX11-TRUE16-NEXT: s_clause 0xf ; 64-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:68
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -219757,589 +219426,497 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v17
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v52, 16, v24
; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v32
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v33, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v38, v33, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v32, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v16, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v34, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_lshlrev_b32 v82, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v30
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v48, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v39, v33, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v36, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v33
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v38, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v10
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v16, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v37, v39, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v36, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v33, v38, v48
; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v37
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v35, v36 :: v_dual_add_f32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v38, v34, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v17.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v16.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v35, v38, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v35, v37 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v38, v34, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34
+; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v36, 0x40c00000, v36
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v35, v38, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_add3_u32 v38, v39, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v35, v37, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v36, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v48
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v19, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v35, v38, v39 :: v_dual_lshlrev_b32 v38, 16, v21
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v36, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add3_u32 v37, v37, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v38, v36, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v37, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v36, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v36
+; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v20, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v38, v35, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v18.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v19.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v35.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v48, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v48
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v37
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v39, v48, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v38, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v32.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v20, 0x7fff
; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v36, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v37, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v38, v49, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v48, v49, v38, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v37, v39, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v50
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v36.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v37, v48, v49 :: v_dual_lshlrev_b32 v48, 16, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v38, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v37, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v38, v38, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v38, v49, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v23
; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v39, v50, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v51, 0x40c00000, v38
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 0x40c00000, v23 :: v_dual_add_f32 v48, 0x40c00000, v48
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v21.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v20.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v48, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v48, 0x40c00000, v48 :: v_dual_cndmask_b32 v21, v39, v49
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v50, v38, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v38
+; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v48, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v37.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v39, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v39, v50, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v48
-; GFX11-TRUE16-NEXT: v_add3_u32 v49, v49, v48, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v39, v39, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v39, v50, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v51, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v50, v51, v48, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v48
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v39, v49, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v23, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v49, v38, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v39
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v49, v50, v51, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v48, v48, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v52
+; GFX11-TRUE16-NEXT: v_add3_u32 v49, v49, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v39, v50, v51 :: v_dual_lshlrev_b32 v50, 16, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v23
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v48, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v51
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v48, v50, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v49, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v49, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v48
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v25
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_add3_u32 v49, v49, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v23.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v53, 0x40c00000, v48
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v50 :: v_dual_cndmask_b32 v23, v49, v51
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v49, v52, v48, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v48
+; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v50, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v52, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v52
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v49, v51, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v53, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v50, v50, v52, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v22.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v51, v51, v53, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v50, v48, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v50, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v49
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v39.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v49, v51, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v49, v52, v24, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT: v_add3_u32 v52, v53, v50, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v50
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v49, v51, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v50, 0x40c00000, v54
+; GFX11-TRUE16-NEXT: v_add3_u32 v51, v51, v25, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v49, v52, v53 :: v_dual_lshlrev_b32 v52, 16, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v25
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v50, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v50, v50, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v53
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v50, v52, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v51, v49, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v51, v26, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v27
; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_add3_u32 v51, v51, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v25.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v55, 0x40c00000, v50
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v38.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v51, v53, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v51, v54, v50, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v50
+; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v52, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v54, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v54
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v51, v53, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v55, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v52, v52, v54, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v24.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v53, v53, v55, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v52, v50, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v52, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v28
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v49.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v51, v53, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v51, v54, v26, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v26
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: v_add3_u32 v54, v55, v52, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v52
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v51, v53, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v27, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v52, 0x40c00000, v64
+; GFX11-TRUE16-NEXT: v_add3_u32 v53, v53, v27, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v51, v54, v55 :: v_dual_lshlrev_b32 v54, 16, v29
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v27
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v52, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_add3_u32 v52, v52, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v48.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v64, 0x40c00000, v51
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v55
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v52, v54, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v53, v51, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v27.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v65, 0x40c00000, v52
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v48.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v53, v55, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v53, v64, v52, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v52
+; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v54, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v64, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v64
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v53, v55, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v65, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v64, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v26.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v65, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v54, v52, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v54, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v54, v54, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v50.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v66, 0x40c00000, v53
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v53, 0x400000, v65
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v54, v64, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v65
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v55, v53, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v54
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v51.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v52, v53, v55, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v53, v64, v28, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT: v_add3_u32 v64, v65, v54, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v54
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v55, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v55, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v54, 0x40c00000, v66
+; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v29, 0x7fff
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v31
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v53, v64, v65 :: v_dual_lshlrev_b32 v64, 16, v31
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v54, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v55, v55, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v29.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v54
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v64, 0x40c00000, v64 :: v_dual_cndmask_b32 v29, v55, v65
+; GFX11-TRUE16-NEXT: v_add3_u32 v55, v66, v54, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v54
+; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v30, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v64, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v66, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v66
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v55, v65, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v67, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v64, v64, v66, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v28.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v67, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v64, v54, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v64, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v55
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v53.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v55, v65, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v55, v66, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: v_add3_u32 v66, v67, v64, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v55, v65, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v31, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v64, 0x40c00000, v68
+; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v31, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v55, v66, v67 :: v_dual_lshlrev_b32 v66, 16, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v31
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v64, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_add3_u32 v64, v64, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v52.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v55
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v67
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v64, v66, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v65, v55, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v64
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v31.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v69, 0x40c00000, v64
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v66, 0x40c00000, v66 :: v_dual_cndmask_b32 v31, v65, v67
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v65, v68, v64, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v64
+; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
+; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v66, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v68, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v68
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v65, v67, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v69, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v66, v66, v68, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v30.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v69, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v66, v64, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v66, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v65
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v55.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v64, v65, v67, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v65, v68, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v68, v69, v66, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v66
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v65, v67, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v65, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v70
+; GFX11-TRUE16-NEXT: v_add3_u32 v65, v65, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v68, v69, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v67, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v66, v66, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v54.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v70, 0x40c00000, v65
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v69
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v66, v68, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
-; GFX11-TRUE16-NEXT: v_bfe_u32 v68, v70, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v70
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v67, v65, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v66
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v68, v68, v70, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v68, 0x40c00000, v68
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v50.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v65, v69, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v65, v70, v67, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v67
+; GFX11-TRUE16-NEXT: v_bfe_u32 v70, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
+; GFX11-TRUE16-NEXT: v_bfe_u32 v71, v68, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v65.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v67, v70, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v65, v69, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v70, v71, v68, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v68
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v67, v69, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v68, v71, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v68, v68
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v69, 0x40c00000, v80
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v65.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v70, v71, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v69, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v69, v71 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v66, 0x40c00000, v66
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v66, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v66
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v66
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v66, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v67, v80, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v70, 0x40c00000, v70
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v52.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v67, v71, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v67, v80, v69, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v69
+; GFX11-TRUE16-NEXT: v_bfe_u32 v80, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v69
+; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v70, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v68.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v69, v80, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v67, v71, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v67, v80, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v69, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v80, v81, v70, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v70
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v69, v71, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v71, 0x40c00000, v82
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v67.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v80, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v71, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v5, v69, v81
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v67, v82, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v80, 0x40c00000, v80 :: v_dual_cndmask_b32 v5, v69, v81
+; GFX11-TRUE16-NEXT: v_add3_u32 v69, v82, v71, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v71
+; GFX11-TRUE16-NEXT: v_bfe_u32 v82, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v71, v71
+; GFX11-TRUE16-NEXT: v_bfe_u32 v83, v80, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v66.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v67, v82, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v68.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v69, v83, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v70.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v71, v82, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v69, v69, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v82, v83, v80, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v80
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v71, v81, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v71, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v80, v80
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v81, 0x40c00000, v84
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v69.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v71, v71, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v80, v82, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v81, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v69, v83, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v67, v84, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v71.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v82, 0x40c00000, v82 :: v_dual_cndmask_b32 v7, v71, v83
+; GFX11-TRUE16-NEXT: v_add3_u32 v71, v84, v81, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v84, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v81
+; GFX11-TRUE16-NEXT: v_bfe_u32 v85, v82, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v6, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v80.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v81, v84, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v71, v71, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v67, v67, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v67, v84, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v67, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v69, v85, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v84, v85, v82, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v82
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v83, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v81, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v82
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v83, 0x40c00000, v86
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v71.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v81, v81, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v84, v85, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v83, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v85, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v67, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v84, 0x40c00000, v84
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v81, v85, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v81, v86, v83, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v83
+; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v84, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v86, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v67, 0x40c00000, v67
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v81.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v67, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v67
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v67, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v82.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v86, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v81, v85, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v69, v86, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v67, v67
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v86, v86, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v87, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v86, v87, v84, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v84
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v83, v85, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v83, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v84
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v85, 0x40c00000, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v81.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v83, v83, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v84, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v85, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v96, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v86, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v97, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v83.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v86, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v86, 0x40c00000, v87
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v98, v86, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v87, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v64.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v83, v86, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v83, 0x40c00000, v87
+; GFX11-TRUE16-NEXT: v_add3_u32 v86, v96, v85, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v85
+; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v85
+; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v83, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v83
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v84.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v85, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v86, v96, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v98, v86, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v69, v97, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v86
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v12
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v13, v69 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v87
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v97, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v86, 0x40c00000, v86
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v99, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v101, 0x400000, v86
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v69, v87, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v97, v97, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v96, v97, v83, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v14
+; GFX11-TRUE16-NEXT: v_bfe_u32 v99, v13, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v87, v86, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
-; GFX11-TRUE16-NEXT: v_bfe_u32 v100, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v103, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v86, v87, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v83, v83
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v86, 0x40c00000, v97
+; GFX11-TRUE16-NEXT: v_add3_u32 v87, v99, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v87, v87, v86, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v100, v100, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v69, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v86, v87, v101, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v85.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v83, v96, v98, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v97, v86, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v66.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v87, v96, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v87, 0x40c00000, v98
+; GFX11-TRUE16-NEXT: v_add3_u32 v96, v97, v86, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v97, 0x400000, v86
+; GFX11-TRUE16-NEXT: v_bfe_u32 v98, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v86
+; GFX11-TRUE16-NEXT: v_bfe_u32 v99, v87, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v83.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v86, v96, v97, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v97, v98, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v98, v99, v87, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v99, 0x400000, v87
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v87, v87
+; GFX11-TRUE16-NEXT: v_bfe_u32 v96, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v101, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v87, v98, v99, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v96.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v69, v69, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v69, v102, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v96, v96, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v97, v100, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v86
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v100, v103, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v86.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v15.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v97, v99, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v98.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v85.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v86.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v96, v101, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v87.h
; GFX11-TRUE16-NEXT: .LBB104_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 17fa6366bbca10..9e2c1f062baec4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -2929,94 +2929,94 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v4i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v7, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11-TRUE16-NEXT: .LBB22_2: ; %end
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
+; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v4i32:
@@ -3797,65 +3797,58 @@ define <16 x i8> @bitcast_v4i32_to_v16i8(<4 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4i32_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB24_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4i32_to_v16i8:
@@ -7690,94 +7683,94 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v4f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v7, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v4f32:
@@ -8558,63 +8551,56 @@ define <16 x i8> @bitcast_v4f32_to_v16i8(<4 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4f32_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v16, 1.0, v16
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4f32_to_v16i8:
@@ -12044,94 +12030,94 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v2i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v7, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11-TRUE16-NEXT: .LBB66_2: ; %end
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
+; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v2i64:
@@ -12912,65 +12898,58 @@ define <16 x i8> @bitcast_v2i64_to_v16i8(<2 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2i64_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB68_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_co_u32 v11, vcc_lo, v11, 3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2i64_to_v16i8:
@@ -15957,94 +15936,94 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v2f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v13 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v7, v8 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v6, v7 :: v_dual_lshlrev_b32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v10 :: v_dual_add_f32 v4, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v3, v9 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11-TRUE16-NEXT: .LBB82_2: ; %end
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v2, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.h
+; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v2f64:
@@ -16823,62 +16802,55 @@ define <16 x i8> @bitcast_v2f64_to_v16i8(<2 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2f64_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB84_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2f64_to_v16i8:
@@ -19497,89 +19469,76 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v7, v8 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v12, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v12, v5, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, v8, v9 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v5, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v13 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v12, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v9, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v10.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -20421,65 +20380,58 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8i16_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB96_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8i16_to_v16i8:
@@ -22533,97 +22485,94 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v8f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v13, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v8, v9 :: v_dual_and_b32 v6, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v11, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
-; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v8, v12 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v10, v10, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v13, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v10.h
+; GFX11-TRUE16-NEXT: .LBB102_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v8f16:
@@ -23491,65 +23440,58 @@ define <16 x i8> @bitcast_v8f16_to_v16i8(<8 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8f16_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v16, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB104_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v17.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8f16_to_v16i8:
@@ -25352,134 +25294,139 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8bf16_to_v16i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v4
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[2:3]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v3.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: .LBB108_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v6 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v13, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v6.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v1, v1, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v4, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v11, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v3, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v0, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v11, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v14.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[16:17]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v10.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v7, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v3, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 8, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v21
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v21.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v22.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8bf16_to_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
index c7cd6ebeca16e0..ebc3b81e62385c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
@@ -716,20 +716,17 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB6_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB6_4
-; GFX11-TRUE16-NEXT: s_branch .LBB6_3
-; GFX11-TRUE16-NEXT: .LBB6_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB6_4
-; GFX11-TRUE16-NEXT: .LBB6_3: ; %cmp.true
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
@@ -739,10 +736,10 @@ define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: .LBB6_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_bf16_to_i16:
@@ -1237,20 +1234,17 @@ define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_4
-; GFX11-TRUE16-NEXT: s_branch .LBB10_3
-; GFX11-TRUE16-NEXT: .LBB10_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_4
-; GFX11-TRUE16-NEXT: .LBB10_3: ; %cmp.true
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
@@ -1260,10 +1254,10 @@ define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: .LBB10_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_bf16_to_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index b18d1409ad0942..452cb0f08ccd54 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -4031,162 +4031,159 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v8i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v10, v11, v13 :: v_dual_and_b32 v13, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v9, v14 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v9.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v9, v11 :: v_dual_and_b32 v10, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v10.l
-; GFX11-TRUE16-NEXT: .LBB22_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v8i32:
@@ -5551,110 +5548,96 @@ define <32 x i8> @bitcast_v8i32_to_v32i8(<8 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8i32_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB24_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v28
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 3, v33
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 3, v32
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v27
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v26
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8i32_to_v32i8:
@@ -11522,162 +11505,159 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v8f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v10, v11, v13 :: v_dual_and_b32 v13, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v9, v14 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v9.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v9, v11 :: v_dual_and_b32 v10, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v10.l
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v8f32:
@@ -13042,107 +13022,94 @@ define <32 x i8> @bitcast_v8f32_to_v32i8(<8 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v8f32_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v27, 1.0, v27
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 1.0, v28 :: v_dual_add_f32 v3, 1.0, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v19, 1.0, v19
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 1.0, v20 :: v_dual_add_f32 v11, 1.0, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v32, 1.0, v32
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v33, 1.0, v33 :: v_dual_add_f32 v10, 1.0, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v26, 1.0, v26
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v18, 1.0, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v8f32_to_v32i8:
@@ -18511,162 +18478,159 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v4i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v10, v11, v13 :: v_dual_and_b32 v13, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v9, v14 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v9.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v9, v11 :: v_dual_and_b32 v10, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v10.l
-; GFX11-TRUE16-NEXT: .LBB66_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v4i64:
@@ -20031,113 +19995,99 @@ define <32 x i8> @bitcast_v4i64_to_v32i8(<4 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4i64_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB68_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_co_u32 v11, vcc_lo, v11, 3
+; GFX11-TRUE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_co_u32 v19, vcc_lo, v19, 3
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v20, null, 0, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_co_u32 v27, vcc_lo, v27, 3
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_co_u32 v26, vcc_lo, v26, 3
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v27, null, 0, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_co_u32 v32, vcc_lo, v32, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v28, null, 0, v28, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, v3, 3
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v33, null, 0, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4i64_to_v32i8:
@@ -24938,162 +24888,159 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v4f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v3 :: v_dual_mov_b32 v10, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v14 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v15, v12, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v16, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v10, v11, v13 :: v_dual_and_b32 v13, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v11, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v6.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v9, v14 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v9.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v9, v11 :: v_dual_and_b32 v10, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v12, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_add_f32 v10, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v12, v6, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v13, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v8.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v10.l
-; GFX11-TRUE16-NEXT: .LBB82_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v12 :: v_dual_mov_b32 v5, v13
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v4f64:
@@ -26452,108 +26399,94 @@ define <32 x i8> @bitcast_v4f64_to_v32i8(<4 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4f64_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB84_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_f64 v[27:28], v[27:28], 1.0
-; GFX11-TRUE16-NEXT: v_add_f64 v[19:20], v[19:20], 1.0
-; GFX11-TRUE16-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
-; GFX11-TRUE16-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[32:33], v[32:33], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4f64_to_v32i8:
@@ -30954,151 +30887,139 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v8, 16, v0
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v9, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v9, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v11, v12 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v14, v17, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v14, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v14, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v11, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v1, v12, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v14, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v3, v15 :: v_dual_lshlrev_b32 v15, 16, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v18, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v12, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v14, v15 :: v_dual_lshlrev_b32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v19, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v16, v18 :: v_dual_lshlrev_b32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v17
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v14, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v15, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v12, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_add_f32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v17, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v12, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v11.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v16, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v16.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v15, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v18, v19, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v11.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v12, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v17, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v20, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v7.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v17, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v18.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v16, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -32563,110 +32484,96 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16i16_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB96_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v33, v33, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v32, v32, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16i16_to_v32i8:
@@ -36392,162 +36299,158 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v16f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v15, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v5 :: v_dual_mov_b32 v13, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v9, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_4
+; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB102_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v13 :: v_dual_mov_b32 v5, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v0, 0x7fff
+; GFX11-TRUE16-NEXT: .LBB102_4: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v0, v5, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v11, v12 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v14, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v12, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v12, v14, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v9, v7, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v15, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v15 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v14, v16, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v5, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v14, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v13, v16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v12 :: v_dual_lshlrev_b32 v6, 16, v13
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v17.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v10.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v4, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v12, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v12, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v13, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v5, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v15, v16, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v17, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v12, v14 :: v_dual_lshlrev_b32 v12, 16, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v6, v15 :: v_dual_and_b32 v16, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v18, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v6, v20, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v13.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v12.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v19, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v18, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v16, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v14.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v15.l
-; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v21, v16, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v15, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.h
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -38064,110 +37967,96 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16f16_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v1 :: v_dual_mov_b32 v10, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v8
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB104_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v33, 0x200, v33 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v32, 0x200, v32 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[18:19]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v10
; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v19.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v27.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v33.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16f16_to_v32i8:
@@ -41536,244 +41425,246 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v16bf16_to_v32i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v7 :: v_dual_mov_b32 v27, v6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v5 :: v_dual_mov_b32 v19, v4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v3 :: v_dual_mov_b32 v11, v2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[6:7]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[4:5]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 24, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[2:3]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.h, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.h, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v7.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
; GFX11-TRUE16-NEXT: .LBB108_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v0, v4, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v8, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v10 :: v_dual_add_f32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v10, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v17, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v11, v16, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v8, v10 :: v_dual_and_b32 v9, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v10.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v12, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v11.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v0, v3 :: v_dual_and_b32 v3, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v8, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v12.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[26:27]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v26
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v14.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v9, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v1, v2 :: v_dual_add_f32 v1, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v13, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v8.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v9 :: v_dual_add_f32 v1, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v14, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v9, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v10 :: v_dual_lshlrev_b32 v0, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v10.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v22.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v13 :: v_dual_lshlrev_b32 v8, 16, v28
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v14, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v1, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v20.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v13, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v16.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v6, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v7, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v16, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v30.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v26.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v35
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v35
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v51, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 24, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v50, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v24.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v51
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v51
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[50:51]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[34:35]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v50
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v27.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v16.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v34.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v20.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v35.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v24.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v50.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v28.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v51.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v16bf16_to_v32i8:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index c108fb664ca936..986ab931d19fe7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -3065,33 +3065,23 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -3105,29 +3095,19 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -3149,62 +3129,63 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -9886,33 +9867,23 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -9926,29 +9897,19 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -9963,65 +9924,66 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -16255,33 +16217,23 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -16295,29 +16247,19 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -16339,62 +16281,63 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -22629,33 +22572,23 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -22669,29 +22602,19 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB60_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -22713,62 +22636,63 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB60_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -31226,33 +31150,23 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -31266,29 +31180,19 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB74_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -31305,62 +31209,63 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB74_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -35106,33 +35011,23 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -35146,29 +35041,19 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB78_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -35193,62 +35078,63 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v1
; GFX11-TRUE16-NEXT: .LBB78_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v35, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v30, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v38, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v33, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v14, 16, v3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v28, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v25, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v2, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v3, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v15, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v20, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v18, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v14, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v30, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v15, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v13, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v13, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v16, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v14, 16, v6
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v14, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v8
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v10
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 38a3d781676eff..48259e19a00c08 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -1435,36 +1435,40 @@ define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: .LBB14_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_i32:
@@ -2169,30 +2173,28 @@ define <4 x i8> @bitcast_i32_to_v4i8(i32 %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_i32_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB20_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_branch .LBB20_3
-; GFX11-TRUE16-NEXT: .LBB20_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: .LBB20_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_i32_to_v4i8:
@@ -3902,36 +3904,40 @@ define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: .LBB34_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_f32:
@@ -4639,30 +4645,28 @@ define <4 x i8> @bitcast_f32_to_v4i8(float %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_f32_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_branch .LBB40_3
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: .LBB40_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_f32_to_v4i8:
@@ -5995,27 +5999,24 @@ define <2 x i16> @bitcast_v2bf16_to_v2i16(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6785,30 +6786,28 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2i16_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_branch .LBB56_3
-; GFX11-TRUE16-NEXT: .LBB56_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: .LBB56_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2i16_to_v4i8:
@@ -7759,36 +7758,40 @@ define <2 x half> @bitcast_v2bf16_to_v2f16(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB62_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: .LBB62_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: .LBB62_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2f16:
@@ -8567,30 +8570,28 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2f16_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_branch .LBB68_3
-; GFX11-TRUE16-NEXT: .LBB68_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: .LBB68_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2f16_to_v4i8:
@@ -9323,36 +9324,40 @@ define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v1i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB72_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB72_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: .LBB72_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: .LBB72_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v1i32:
@@ -9954,50 +9959,50 @@ define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB76_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB76_4
-; GFX11-TRUE16-NEXT: s_branch .LBB76_3
-; GFX11-TRUE16-NEXT: .LBB76_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB76_4
-; GFX11-TRUE16-NEXT: .LBB76_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v4
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: .LBB76_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v4i8:
@@ -10843,30 +10848,28 @@ define <4 x i8> @bitcast_v1i32_to_v4i8(<1 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v1i32_to_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB80_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_branch .LBB80_3
-; GFX11-TRUE16-NEXT: .LBB80_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: .LBB80_3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v1i32_to_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index ffff9da12fe9fe..4e307f1d8aca20 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -137,13 +137,18 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v3bf16_to_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -151,34 +156,32 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v3, v7 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fc0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB0_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x7fc0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX11-TRUE16-NEXT: .LBB0_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v3bf16_to_v3f16:
@@ -907,37 +910,35 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB4_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fc0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
; GFX11-TRUE16-NEXT: .LBB4_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1330,7 +1331,7 @@ define <3 x bfloat> @bitcast_v3i16_to_v3bf16(<3 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
-; GFX9-NEXT: v_pk_add_u16 v1, v1, 3
+; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -1345,7 +1346,7 @@ define <3 x bfloat> @bitcast_v3i16_to_v3bf16(<3 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-NEXT: v_pk_add_u16 v1, v1, 3
+; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1452,7 +1453,7 @@ define inreg <3 x bfloat> @bitcast_v3i16_to_v3bf16_scalar(<3 x i16> inreg %a, i3
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB7_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
-; GFX9-NEXT: v_pk_add_u16 v1, s17, 3
+; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB7_5:
@@ -1475,7 +1476,7 @@ define inreg <3 x bfloat> @bitcast_v3i16_to_v3bf16_scalar(<3 x i16> inreg %a, i3
; GFX11-NEXT: s_cmp_lg_u32 s2, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB7_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-NEXT: v_pk_add_u16 v1, s1, 3
+; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB7_4:
@@ -1789,7 +1790,7 @@ define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: ; %bb.1: ; %cmp.true
-; GFX9-NEXT: v_pk_add_u16 v1, v1, 3
+; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: ; %bb.2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -1804,7 +1805,7 @@ define <3 x half> @bitcast_v3i16_to_v3f16(<3 x i16> %a, i32 %b) #0 {
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-NEXT: v_pk_add_u16 v1, v1, 3
+; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: ; %bb.2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
@@ -1912,7 +1913,7 @@ define inreg <3 x half> @bitcast_v3i16_to_v3f16_scalar(<3 x i16> inreg %a, i32 i
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB11_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
-; GFX9-NEXT: v_pk_add_u16 v1, s17, 3
+; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: .LBB11_5:
@@ -1935,7 +1936,7 @@ define inreg <3 x half> @bitcast_v3i16_to_v3f16_scalar(<3 x i16> inreg %a, i32 i
; GFX11-NEXT: s_cmp_lg_u32 s2, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB11_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-NEXT: v_pk_add_u16 v1, s1, 3
+; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB11_4:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 280a0f17a4bc8a..7fa6cf22d1ee53 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -6462,296 +6462,298 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB22_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v21, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v19, v21 :: v_dual_and_b32 v19, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v21 :: v_dual_and_b32 v20, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v18, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v16.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_and_b32 v21, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v17.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v17, v19 :: v_dual_and_b32 v18, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v18.l
-; GFX11-TRUE16-NEXT: .LBB22_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16i32:
@@ -9720,51 +9722,35 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -9781,44 +9767,28 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB24_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -9849,96 +9819,96 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -21434,296 +21404,298 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v21, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v19, v21 :: v_dual_and_b32 v19, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v21 :: v_dual_and_b32 v20, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v18, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v16.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_and_b32 v21, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v17.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v17, v19 :: v_dual_and_b32 v18, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v18.l
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16f32:
@@ -24692,51 +24664,35 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -24753,44 +24709,28 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -24813,96 +24753,96 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -35720,296 +35660,298 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB66_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v21, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v19, v21 :: v_dual_and_b32 v19, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v21 :: v_dual_and_b32 v20, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v18, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v16.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_and_b32 v21, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v17.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v17, v19 :: v_dual_and_b32 v18, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v18.l
-; GFX11-TRUE16-NEXT: .LBB66_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8i64:
@@ -38978,51 +38920,35 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -39039,44 +38965,28 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB68_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -39112,96 +39022,96 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -49046,296 +48956,298 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB82_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v20, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v21, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v19, v21 :: v_dual_and_b32 v19, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v21 :: v_dual_and_b32 v20, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_cndmask_b32 v12, v18, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v19, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v16.l
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_and_b32 v21, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v16.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v17.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v17, v19 :: v_dual_and_b32 v18, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_f32 v18, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v16.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v18.l
-; GFX11-TRUE16-NEXT: .LBB82_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
+; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8f64:
@@ -52280,51 +52192,35 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -52341,44 +52237,28 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB84_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -52401,96 +52281,96 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -62025,302 +61905,259 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v18, 16, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v17, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v18, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v22, v25, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v22, v24, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v21
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_lshlrev_b32 v20, 16, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v18, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v22, v23, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v22, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v21, v23, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v3, v19, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v24, v21, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v20.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v23, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v20, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v21, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v24, v25, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v21, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v19.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v24, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v23, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v21, v25, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v20, v26, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_cndmask_b32 v5, v21, v25
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v26, v23, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v24, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v26, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v21, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v20, v26, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v21, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v26, v27, v24, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v23, v25, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v21.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v26, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v25, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v22.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v21, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v20, v28, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_cndmask_b32 v7, v23, v27
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v28, v25, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v23.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_add3_u32 v25, v28, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v23, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v20, v28, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v21, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v28, v29, v26, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v25, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v22.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v28, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v27, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v24.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v9, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v21, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v20, v7, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_lshlrev_b32 v20, 16, v10
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_cndmask_b32 v9, v25, v29
+; GFX11-TRUE16-NEXT: v_add3_u32 v25, v30, v27, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v30 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v25.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v27, v30, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v25, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v10
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v21, v30, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v9, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v30, v30, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v31, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v30, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v30, v31, v28, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v27, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v25.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v24.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v30, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v21, v32, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v27.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v30, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v12, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v27, v30, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v31
+; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v29, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v12
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v13, v34, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v21, v33, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v12
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v13, v21 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v33, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v21, v31, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v27, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v13, 16, 1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v30, v31, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v33
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v35, v13, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v31, v31, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v36, v36, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v31, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v29.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v32, v34, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v31, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v27.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v31
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v21, v38, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v33, v36, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v39, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v15.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v33, v35, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v29.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v32, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v31.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v28.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -65766,51 +65603,35 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -65827,44 +65648,28 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB96_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -65895,96 +65700,96 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -74460,294 +74265,291 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v31, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v13 :: v_dual_mov_b32 v29, v12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v11 :: v_dual_mov_b32 v27, v10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v9 :: v_dual_mov_b32 v25, v8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v7 :: v_dual_mov_b32 v23, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v5 :: v_dual_mov_b32 v21, v4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v19, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_3
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_4
+; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-NEXT: .LBB102_3: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v17 :: v_dual_mov_b32 v1, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v20
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v21 :: v_dual_mov_b32 v5, v22
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v23 :: v_dual_mov_b32 v7, v24
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v25 :: v_dual_mov_b32 v9, v26
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v27 :: v_dual_mov_b32 v11, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v29 :: v_dual_mov_b32 v13, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v31 :: v_dual_mov_b32 v15, v32
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 0x40c00000, v16 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
+; GFX11-TRUE16-NEXT: .LBB102_4: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v26
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v23, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v0, v5, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v22, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v20, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v22, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v7, v9 :: v_dual_add_f32 v3, 0x40c00000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v23, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v20, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v19, v22, v23 :: v_dual_add_f32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v8, v10 :: v_dual_and_b32 v10, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v21, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v23
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v21, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v22, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v17, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v24, v25, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v22, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v5, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v21, v24, v25 :: v_dual_add_f32 v22, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v10 :: v_dual_lshlrev_b32 v6, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v7, 0x40c00000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_add_f32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v23, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v25
-; GFX11-TRUE16-NEXT: v_add3_u32 v24, v26, v22, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v21.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v24, v25, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v24, v26, v6, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v26, v27, v23, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v24, v25, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v23, v26, v27 :: v_dual_add_f32 v24, 0x40c00000, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v8, 0x40c00000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v25, v26, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v27
-; GFX11-TRUE16-NEXT: v_add3_u32 v26, v28, v24, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v25, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v23.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v26, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v26, v28, v8, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v12 :: v_dual_lshlrev_b32 v8, 16, v23
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v12, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v11, v8, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v28, v29, v25, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v26, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v20.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v25, v28, v29 :: v_dual_add_f32 v26, 0x40c00000, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v12, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 0x40c00000, v11 :: v_dual_add_f32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v27, v28, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v29
-; GFX11-TRUE16-NEXT: v_add3_u32 v28, v30, v26, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v26
-; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v27, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v25.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v28, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v28, v30, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v14 :: v_dual_lshlrev_b32 v10, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v9, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v11, 0x40c00000, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v8, v13, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v13, v10, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_add3_u32 v30, v31, v27, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v24.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v28, v29, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v11, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v27, v30, v31 :: v_dual_add_f32 v28, 0x40c00000, v28
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v29, v29, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v9, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v13 :: v_dual_add_f32 v12, 0x40c00000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v29, v30, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v31
-; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v28, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v29, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v27.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v30, v31, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v24
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v11, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v26, v10, v15 :: v_dual_add_f32 v13, 0x40c00000, v13
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v24, v11, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v13, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v12, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
+; GFX11-TRUE16-NEXT: v_add3_u32 v15, v24, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v27
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v29, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v30, v31, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v13, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_cndmask_b32 v29, v32, v33
-; GFX11-TRUE16-NEXT: v_add3_u32 v31, v31, v13, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v25.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v11, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v30, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v34
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v31, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v29.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v28 :: v_dual_lshlrev_b32 v14, 16, v29
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v24, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v33.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v13, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v27, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v28, v13, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v24.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v13, v28, v14, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v27, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v14
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v33, v36, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v28, v29, v15, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v13, v27, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v32, v37, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v31.l
-; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v29, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.h
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v28, v30 :: v_dual_lshlrev_b32 v28, 16, v31
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v29, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v29, v14, v31 :: v_dual_and_b32 v32, 0xffff0000, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v28, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v31, v34, v15, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
+; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v28, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
+; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v14, v36, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
+; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v32, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v36, v37, v32, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v31, v35, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v28.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v37, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v30.h
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -78367,51 +78169,35 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
@@ -78428,44 +78214,28 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB104_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
@@ -78496,96 +78266,96 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -87079,490 +86849,504 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[3:4]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v5.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v6.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.h, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v9.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.h, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v14.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.h, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v15.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.h, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v16.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15
; GFX11-TRUE16-NEXT: .LBB108_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v17, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v22, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v20, 0x40c00000, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v17, v24, v20, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v52, v18, v23 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v21, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v22, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v21, v22, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v21, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v52.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v23, v26, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v20 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v53.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v19, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v1, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v17
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v1, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v54.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v55.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v28.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_add_f32 v19, 0x40c00000, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v19
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v6
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v6, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v30.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v64, v3, v21 :: v_dual_and_b32 v3, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v8, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v8, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v64.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v2, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v5, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v1, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v8
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v8
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v18, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v10, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v10, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v20, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v65.h
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v5, 16, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v9, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v12, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v9, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v12, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v14, 0x40c00000, v14
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v21, v11, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v21, v22, v17, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v14, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v17
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v14, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v19, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v20, v21, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v11
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 24, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v21, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v15, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v13, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v21, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v21
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v18, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v23, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v1, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v1, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v3, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v68, v1, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v66.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v2, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v67.h
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v2, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v68.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v82, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v8 :: v_dual_lshlrev_b32 v5, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v82.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v81.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v25
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v27, v2, v3 :: v_dual_add_f32 v2, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v98, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v99, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v98.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v3, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v9 :: v_dual_lshlrev_b32 v3, 16, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v99.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[27:28]
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v115, v4, v6 :: v_dual_add_f32 v6, 0x40c00000, v8
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v117, v2, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v115.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[19:20]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v33
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v33
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v7, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v4, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v117.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v118.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[32:33]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v48
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v28, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v32, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v30, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v33, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v26, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v27, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v29, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v31, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v34, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v36, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v39, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v37, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v49, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v48, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v26, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v53.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v17.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v18.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v55.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v19.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v54.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v52.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v65.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v21.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v129, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v5, v128, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v7, v119, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v20.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v64.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v22.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v67.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v66.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v24.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v82.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v25.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v68.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v26.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v98.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v27.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v101, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v81.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v28.h
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v115.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v32.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v99.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v118.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v48.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v117.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v49.h
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
index 9b079dccf1023a..9ce295efedfc97 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
@@ -3073,52 +3073,13 @@ define <36 x i16> @bitcast_v18i32_to_v36i16(<18 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v18i32_to_v36i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
@@ -3137,45 +3098,8 @@ define <36 x i16> @bitcast_v18i32_to_v36i16(<18 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v18i32_to_v36i16:
@@ -4536,92 +4460,13 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36i16_to_v18i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -4640,6 +4485,7 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5839,52 +5685,13 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v18i32_to_v36f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
@@ -5903,45 +5710,8 @@ define <36 x half> @bitcast_v18i32_to_v36f16(<18 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v18i32_to_v36f16:
@@ -7376,92 +7146,13 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36f16_to_v18i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -7480,6 +7171,7 @@ define <18 x i32> @bitcast_v36f16_to_v18i32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -10883,52 +10575,13 @@ define <36 x i16> @bitcast_v18f32_to_v36i16(<18 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v18f32_to_v36i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
@@ -10938,45 +10591,8 @@ define <36 x i16> @bitcast_v18f32_to_v36i16(<18 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v18f32_to_v36i16:
@@ -12548,92 +12164,13 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36i16_to_v18f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -12652,6 +12189,7 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13851,52 +13389,13 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v18f32_to_v36f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
@@ -13906,45 +13405,8 @@ define <36 x half> @bitcast_v18f32_to_v36f16(<18 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v18f32_to_v36f16:
@@ -15590,92 +15052,13 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36f16_to_v18f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -15694,6 +15077,7 @@ define <18 x float> @bitcast_v36f16_to_v18f32(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17892,52 +17276,13 @@ define <36 x i16> @bitcast_v9i64_to_v36i16(<9 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v9i64_to_v36i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
@@ -17961,45 +17306,8 @@ define <36 x i16> @bitcast_v9i64_to_v36i16(<9 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v9i64_to_v36i16:
@@ -19365,92 +18673,13 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36i16_to_v9i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -19469,6 +18698,7 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20668,52 +19898,13 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v9i64_to_v36f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
@@ -20737,45 +19928,8 @@ define <36 x half> @bitcast_v9i64_to_v36f16(<9 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v9i64_to_v36f16:
@@ -22215,92 +21369,13 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36f16_to_v9i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -22319,6 +21394,7 @@ define <9 x i64> @bitcast_v36f16_to_v9i64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23561,52 +22637,13 @@ define <36 x i16> @bitcast_v9f64_to_v36i16(<9 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v9f64_to_v36i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
@@ -23616,45 +22653,8 @@ define <36 x i16> @bitcast_v9f64_to_v36i16(<9 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v9f64_to_v36i16:
@@ -25181,92 +24181,13 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36i16_to_v9f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -25285,6 +24206,7 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26457,52 +25379,13 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v9f64_to_v36f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
@@ -26512,45 +25395,8 @@ define <36 x half> @bitcast_v9f64_to_v36f16(<9 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v9f64_to_v36f16:
@@ -28151,92 +26997,13 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36f16_to_v9f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v19.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -28255,6 +27022,7 @@ define <9 x double> @bitcast_v36f16_to_v9f64(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -29752,24 +28520,6 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36i16_to_v36f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -29777,24 +28527,6 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v19.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
@@ -29808,49 +28540,13 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v17
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v36.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v36i16_to_v36f16:
@@ -31387,24 +30083,6 @@ define <36 x i16> @bitcast_v36f16_to_v36i16(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v36f16_to_v36i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v18
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -31412,24 +30090,6 @@ define <36 x i16> @bitcast_v36f16_to_v36i16(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v19.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
@@ -31443,49 +30103,13 @@ define <36 x i16> @bitcast_v36f16_to_v36i16(<36 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v17
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v19.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v36.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v36f16_to_v36i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
index 78b54755887fca..765b7eb6c2a015 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
@@ -3304,56 +3304,13 @@ define <40 x i16> @bitcast_v20i32_to_v40i16(<20 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v20i32_to_v40i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
@@ -3374,49 +3331,8 @@ define <40 x i16> @bitcast_v20i32_to_v40i16(<20 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20i32_to_v40i16:
@@ -4949,100 +4865,13 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5063,6 +4892,7 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6372,56 +6202,13 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v20i32_to_v40f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
@@ -6442,49 +6229,8 @@ define <40 x half> @bitcast_v20i32_to_v40f16(<20 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20i32_to_v40f16:
@@ -8102,100 +7848,13 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -8216,6 +7875,7 @@ define <20 x i32> @bitcast_v40f16_to_v20i32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -11870,56 +11530,13 @@ define <40 x i16> @bitcast_v20f32_to_v40i16(<20 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v20f32_to_v40i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
@@ -11930,49 +11547,8 @@ define <40 x i16> @bitcast_v20f32_to_v40i16(<20 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20f32_to_v40i16:
@@ -13738,100 +13314,13 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v20f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -13852,6 +13341,7 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -15161,56 +14651,13 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v20f32_to_v40f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
@@ -15221,49 +14668,8 @@ define <40 x half> @bitcast_v20f32_to_v40f16(<20 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v20f32_to_v40f16:
@@ -17114,100 +16520,13 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v20f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -17228,6 +16547,7 @@ define <20 x float> @bitcast_v40f16_to_v20f32(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19599,56 +18919,13 @@ define <40 x i16> @bitcast_v10i64_to_v40i16(<10 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v10i64_to_v40i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
@@ -19674,49 +18951,8 @@ define <40 x i16> @bitcast_v10i64_to_v40i16(<10 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10i64_to_v40i16:
@@ -21254,100 +20490,13 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -21368,6 +20517,7 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -22677,56 +21827,13 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v10i64_to_v40f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
@@ -22752,49 +21859,8 @@ define <40 x half> @bitcast_v10i64_to_v40f16(<10 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10i64_to_v40f16:
@@ -24417,100 +23483,13 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -24531,6 +23510,7 @@ define <10 x i64> @bitcast_v40f16_to_v10i64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -25880,56 +24860,13 @@ define <40 x i16> @bitcast_v10f64_to_v40i16(<10 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v10f64_to_v40i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
@@ -25940,49 +24877,8 @@ define <40 x i16> @bitcast_v10f64_to_v40i16(<10 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10f64_to_v40i16:
@@ -27698,100 +26594,13 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v10f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -27812,6 +26621,7 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -29091,56 +27901,13 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v10f64_to_v40f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
@@ -29151,49 +27918,8 @@ define <40 x half> @bitcast_v10f64_to_v40f16(<10 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v10f64_to_v40f16:
@@ -30994,100 +29720,13 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v10f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v21.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -31108,6 +29747,7 @@ define <10 x double> @bitcast_v40f16_to_v10f64(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -32781,26 +31421,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40i16_to_v40f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -32808,26 +31428,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
@@ -32843,53 +31443,13 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v40f16:
@@ -34595,26 +33155,6 @@ define <40 x i16> @bitcast_v40f16_to_v40i16(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v40f16_to_v40i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v20
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -34622,26 +33162,6 @@ define <40 x i16> @bitcast_v40f16_to_v40i16(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
@@ -34657,53 +33177,13 @@ define <40 x i16> @bitcast_v40f16_to_v40i16(<40 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v40i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 26821b059cb6c0..e63aa18c6cfc60 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -2393,56 +2393,58 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB22_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v9.h
+; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_i64:
@@ -2935,43 +2937,37 @@ define <8 x i8> @bitcast_i64_to_v8i8(i64 %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_i64_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, v3, 3
+; GFX11-TRUE16-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
+; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_i64_to_v8i8:
@@ -5822,56 +5818,58 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v9.h
+; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_f64:
@@ -6360,41 +6358,36 @@ define <8 x i8> @bitcast_f64_to_v8i8(double %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_f64_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
+; GFX11-TRUE16-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_f64_to_v8i8:
@@ -8903,56 +8896,58 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB66_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v9.h
+; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2i32:
@@ -9445,42 +9440,36 @@ define <8 x i8> @bitcast_v2i32_to_v8i8(<2 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2i32_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2i32_to_v8i8:
@@ -11627,56 +11616,58 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v2f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v2, 0x40c00000, v2
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v1, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_add_f32 v0, 0x40c00000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB82_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v9.h
+; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v2f32:
@@ -12169,41 +12160,35 @@ define <8 x i8> @bitcast_v2f32_to_v8i8(<2 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v2f32_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v2f32_to_v8i8:
@@ -13990,43 +13975,35 @@ define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v9, v11 :: v_dual_add_f32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v7 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -14548,42 +14525,36 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4i16_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4i16_to_v8i8:
@@ -15908,55 +15879,60 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
-; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v9.h
+; GFX11-TRUE16-NEXT: .LBB102_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v4f16:
@@ -16494,42 +16470,36 @@ define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4f16_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v2
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v8
+; GFX11-TRUE16-NEXT: ; %bb.4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4f16_to_v8i8:
@@ -17649,85 +17619,83 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v4bf16_to_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[0:1]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v1.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: .LBB108_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v3, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v6, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v10, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v6, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v9
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v9.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v4bf16_to_v8i8:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
index 2a5574397fad8e..7d99803b4c22e6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
@@ -3504,60 +3504,13 @@ define <44 x i16> @bitcast_v22i32_to_v44i16(<22 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v22i32_to_v44i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
@@ -3580,53 +3533,8 @@ define <44 x i16> @bitcast_v22i32_to_v44i16(<22 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v22i32_to_v44i16:
@@ -5324,108 +5232,13 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5448,6 +5261,7 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6871,60 +6685,13 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v22i32_to_v44f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
@@ -6947,53 +6714,8 @@ define <44 x half> @bitcast_v22i32_to_v44f16(<22 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v22i32_to_v44f16:
@@ -8790,108 +8512,13 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -8914,6 +8541,7 @@ define <22 x i32> @bitcast_v44f16_to_v22i32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -12776,60 +12404,13 @@ define <44 x i16> @bitcast_v22f32_to_v44i16(<22 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v22f32_to_v44i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
@@ -12841,53 +12422,8 @@ define <44 x i16> @bitcast_v22f32_to_v44i16(<22 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v22f32_to_v44i16:
@@ -14840,108 +14376,13 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v22f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -14964,6 +14405,7 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16387,60 +15829,13 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v22f32_to_v44f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
@@ -16452,53 +15847,8 @@ define <44 x half> @bitcast_v22f32_to_v44f16(<22 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v22f32_to_v44f16:
@@ -18550,108 +17900,13 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v22f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -18674,6 +17929,7 @@ define <22 x float> @bitcast_v44f16_to_v22f32(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -21207,60 +20463,13 @@ define <44 x i16> @bitcast_v11i64_to_v44i16(<11 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v11i64_to_v44i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
@@ -21289,53 +20498,8 @@ define <44 x i16> @bitcast_v11i64_to_v44i16(<11 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v11i64_to_v44i16:
@@ -23039,108 +22203,13 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -23163,6 +22232,7 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -24586,60 +23656,13 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v11i64_to_v44f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
@@ -24668,53 +23691,8 @@ define <44 x half> @bitcast_v11i64_to_v44f16(<11 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v11i64_to_v44f16:
@@ -26517,108 +25495,13 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -26641,6 +25524,7 @@ define <11 x i64> @bitcast_v44f16_to_v11i64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -28101,60 +26985,13 @@ define <44 x i16> @bitcast_v11f64_to_v44i16(<11 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v11f64_to_v44i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
@@ -28166,53 +27003,8 @@ define <44 x i16> @bitcast_v11f64_to_v44i16(<11 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v11f64_to_v44i16:
@@ -30110,108 +28902,13 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v11f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -30234,6 +28931,7 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -31624,60 +30322,13 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v11f64_to_v44f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
@@ -31689,53 +30340,8 @@ define <44 x half> @bitcast_v11f64_to_v44f16(<11 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v11f64_to_v44f16:
@@ -33732,108 +32338,13 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v11f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v23.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -33856,6 +32367,7 @@ define <11 x double> @bitcast_v44f16_to_v11f64(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -35708,28 +34220,6 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44i16_to_v44f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -35737,28 +34227,6 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v23.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
@@ -35776,57 +34244,13 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v21
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v44i16_to_v44f16:
@@ -37705,28 +36129,6 @@ define <44 x i16> @bitcast_v44f16_to_v44i16(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v44f16_to_v44i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v22
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -37734,28 +36136,6 @@ define <44 x i16> @bitcast_v44f16_to_v44i16(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v23.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
@@ -37773,57 +36153,13 @@ define <44 x i16> @bitcast_v44f16_to_v44i16(<44 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v21
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v23.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v44f16_to_v44i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index d7b8411c8f1460..d046cb754ce49f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -3703,64 +3703,13 @@ define <48 x i16> @bitcast_v24i32_to_v48i16(<24 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v24i32_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
@@ -3785,57 +3734,8 @@ define <48 x i16> @bitcast_v24i32_to_v48i16(<24 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24i32_to_v48i16:
@@ -5709,116 +5609,13 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -5843,6 +5640,7 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7384,64 +7182,13 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v24i32_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
@@ -7466,57 +7213,8 @@ define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24i32_to_v48f16:
@@ -9502,116 +9200,13 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -9636,6 +9231,7 @@ define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13709,64 +13305,13 @@ define <48 x i16> @bitcast_v24f32_to_v48i16(<24 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
@@ -13779,57 +13324,8 @@ define <48 x i16> @bitcast_v24f32_to_v48i16(<24 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48i16:
@@ -15980,116 +15476,13 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -16114,6 +15507,7 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17655,64 +17049,13 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
@@ -17725,57 +17068,8 @@ define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48f16:
@@ -20038,116 +19332,13 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -20172,6 +19363,7 @@ define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -22870,64 +22062,13 @@ define <48 x i16> @bitcast_v12i64_to_v48i16(<12 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v12i64_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
@@ -22958,57 +22099,8 @@ define <48 x i16> @bitcast_v12i64_to_v48i16(<12 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12i64_to_v48i16:
@@ -24888,116 +23980,13 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -25022,6 +24011,7 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26563,64 +25553,13 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v12i64_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
@@ -26651,57 +25590,8 @@ define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12i64_to_v48f16:
@@ -28693,116 +27583,13 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -28827,6 +27614,7 @@ define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -30402,64 +29190,13 @@ define <48 x i16> @bitcast_v12f64_to_v48i16(<12 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
@@ -30472,57 +29209,8 @@ define <48 x i16> @bitcast_v12f64_to_v48i16(<12 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48i16:
@@ -32613,116 +31301,13 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -32747,6 +31332,7 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -34252,64 +32838,13 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
@@ -34322,57 +32857,8 @@ define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48f16:
@@ -36575,116 +35061,13 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -36709,6 +35092,7 @@ define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -38742,30 +37126,6 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -38773,30 +37133,6 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v25.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
@@ -38816,61 +37152,13 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v64.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v48f16:
@@ -40919,30 +39207,6 @@ define <48 x i16> @bitcast_v48f16_to_v48i16(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -40950,30 +39214,6 @@ define <48 x i16> @bitcast_v48f16_to_v48i16(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v25.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
@@ -40993,61 +39233,13 @@ define <48 x i16> @bitcast_v48f16_to_v48i16(<48 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v64.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v48i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index d070d09aa3dc39..047cddc9c2d8f3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -3939,68 +3939,13 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v26i32_to_v52i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v25
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v24
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
@@ -4027,61 +3972,8 @@ define <52 x i16> @bitcast_v26i32_to_v52i16(<26 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v26i32_to_v52i16:
@@ -6132,124 +6024,13 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6276,6 +6057,7 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7971,68 +7753,13 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v26i32_to_v52f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v25
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v24
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
@@ -8059,61 +7786,8 @@ define <52 x half> @bitcast_v26i32_to_v52f16(<26 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v26i32_to_v52f16:
@@ -10285,124 +9959,13 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -10429,6 +9992,7 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -14750,68 +14314,13 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v26f32_to_v52i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
@@ -14825,61 +14334,8 @@ define <52 x i16> @bitcast_v26f32_to_v52i16(<26 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v26f32_to_v52i16:
@@ -17263,124 +16719,13 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v26f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -17407,6 +16752,7 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19102,68 +18448,13 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v26f32_to_v52f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
@@ -19177,61 +18468,8 @@ define <52 x half> @bitcast_v26f32_to_v52f16(<26 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v26f32_to_v52f16:
@@ -21736,124 +20974,13 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v26f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -21880,6 +21007,7 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -24780,68 +23908,13 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v13i64_to_v52i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v24, vcc_lo, v24, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v25, vcc_lo
@@ -24875,61 +23948,8 @@ define <52 x i16> @bitcast_v13i64_to_v52i16(<13 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v13i64_to_v52i16:
@@ -26987,124 +26007,13 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -27131,6 +26040,7 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -28826,68 +27736,13 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v13i64_to_v52f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v24, vcc_lo, v24, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v25, null, 0, v25, vcc_lo
@@ -28921,61 +27776,8 @@ define <52 x half> @bitcast_v13i64_to_v52f16(<13 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v13i64_to_v52f16:
@@ -31154,124 +29956,13 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -31298,6 +29989,7 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -33024,68 +31716,13 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v13f64_to_v52i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
@@ -33099,61 +31736,8 @@ define <52 x i16> @bitcast_v13f64_to_v52i16(<13 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v13f64_to_v52i16:
@@ -35476,124 +34060,13 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v13f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -35620,6 +34093,7 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -37276,68 +35750,13 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v13f64_to_v52f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
@@ -37351,61 +35770,8 @@ define <52 x half> @bitcast_v13f64_to_v52f16(<13 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v13f64_to_v52f16:
@@ -39849,124 +38215,13 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v13f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -39993,6 +38248,7 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -42230,32 +40486,6 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52i16_to_v52f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -42263,32 +40493,6 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v27.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
@@ -42310,65 +40514,13 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v25
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v68.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v52f16:
@@ -44636,32 +42788,6 @@ define <52 x i16> @bitcast_v52f16_to_v52i16(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v52f16_to_v52i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v26
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -44669,32 +42795,6 @@ define <52 x i16> @bitcast_v52f16_to_v52i16(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v27.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
@@ -44716,65 +42816,13 @@ define <52 x i16> @bitcast_v52f16_to_v52i16(<52 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v25
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v68.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v52i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index 8319358c1e3563..7ff802e2b21212 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -4168,72 +4168,13 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v28i32_to_v56i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v26
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v25
@@ -4262,65 +4203,8 @@ define <56 x i16> @bitcast_v28i32_to_v56i16(<28 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v28i32_to_v56i16:
@@ -6553,132 +6437,13 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -6707,6 +6472,7 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8627,72 +8393,13 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v28i32_to_v56f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v26
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v25
@@ -8721,65 +8428,8 @@ define <56 x half> @bitcast_v28i32_to_v56f16(<28 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v28i32_to_v56f16:
@@ -11149,132 +10799,13 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -11303,6 +10834,7 @@ define <28 x i32> @bitcast_v56f16_to_v28i32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -15884,72 +15416,13 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v28f32_to_v56i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v26, 1.0, v26
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
@@ -15964,65 +15437,8 @@ define <56 x i16> @bitcast_v28f32_to_v56i16(<28 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v28f32_to_v56i16:
@@ -18636,132 +18052,13 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v28f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -18790,6 +18087,7 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20710,72 +20008,13 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v28f32_to_v56f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v26, 1.0, v26
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
@@ -20790,65 +20029,8 @@ define <56 x half> @bitcast_v28f32_to_v56f16(<28 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v28f32_to_v56f16:
@@ -23599,132 +22781,13 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v28f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -23753,6 +22816,7 @@ define <28 x float> @bitcast_v56f16_to_v28f32(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26867,72 +25931,13 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v14i64_to_v56i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v26, vcc_lo, v26, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v27, null, 0, v27, vcc_lo
@@ -26968,65 +25973,8 @@ define <56 x i16> @bitcast_v14i64_to_v56i16(<14 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v14i64_to_v56i16:
@@ -29266,132 +28214,13 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -29420,6 +28249,7 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -31340,72 +30170,13 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v14i64_to_v56f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v26, vcc_lo, v26, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v27, null, 0, v27, vcc_lo
@@ -31441,65 +30212,8 @@ define <56 x half> @bitcast_v14i64_to_v56f16(<14 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v14i64_to_v56f16:
@@ -33876,132 +32590,13 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -34030,6 +32625,7 @@ define <14 x i64> @bitcast_v56f16_to_v14i64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -35920,72 +34516,13 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v14f64_to_v56i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
@@ -36000,65 +34537,8 @@ define <56 x i16> @bitcast_v14f64_to_v56i16(<14 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v14f64_to_v56i16:
@@ -38609,132 +37089,13 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v14f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -38763,6 +37124,7 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -40641,72 +39003,13 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v14f64_to_v56f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
@@ -40721,65 +39024,8 @@ define <56 x half> @bitcast_v14f64_to_v56f16(<14 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v28.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v14f64_to_v56f16:
@@ -43467,132 +41713,13 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v14f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -43621,6 +41748,7 @@ define <14 x double> @bitcast_v56f16_to_v14f64(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -46071,34 +44199,6 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56i16_to_v56f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -46106,34 +44206,6 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v29.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0]
@@ -46157,69 +44229,13 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v27
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v80.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v56i16_to_v56f16:
@@ -48706,34 +46722,6 @@ define <56 x i16> @bitcast_v56f16_to_v56i16(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v56f16_to_v56i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v28
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -48741,34 +46729,6 @@ define <56 x i16> @bitcast_v56f16_to_v56i16(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v29.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1]
@@ -48792,69 +46752,13 @@ define <56 x i16> @bitcast_v56f16_to_v56i16(<56 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v27
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v80.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v56f16_to_v56i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index deced731f537bd..4d6c87f4a66190 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -4424,76 +4424,13 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v30i32_to_v60i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v29
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v28
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v27
@@ -4524,69 +4461,8 @@ define <60 x i16> @bitcast_v30i32_to_v60i16(<30 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB12_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v30i32_to_v60i16:
@@ -7013,140 +6889,13 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB14_4
-; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
-; GFX11-TRUE16-NEXT: .LBB14_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -7177,6 +6926,7 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -9247,76 +8997,13 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v30i32_to_v60f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v29
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v28
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v27
@@ -9347,69 +9034,8 @@ define <60 x half> @bitcast_v30i32_to_v60f16(<30 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB16_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v30i32_to_v60f16:
@@ -11980,140 +11606,13 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB18_4
-; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB18_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
-; GFX11-TRUE16-NEXT: .LBB18_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -12144,6 +11643,7 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17009,76 +16509,13 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v30f32_to_v60i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v29, 1.0, v29 :: v_dual_add_f32 v28, 1.0, v28
; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v26, 1.0, v26
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
@@ -17094,69 +16531,8 @@ define <60 x i16> @bitcast_v30f32_to_v60i16(<30 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB28_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v30f32_to_v60i16:
@@ -20009,140 +19385,13 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v30f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB30_4
-; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB30_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
-; GFX11-TRUE16-NEXT: .LBB30_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -20173,6 +19422,7 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -22243,76 +21493,13 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v30f32_to_v60f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v29, 1.0, v29 :: v_dual_add_f32 v28, 1.0, v28
; GFX11-TRUE16-NEXT: v_dual_add_f32 v27, 1.0, v27 :: v_dual_add_f32 v26, 1.0, v26
; GFX11-TRUE16-NEXT: v_dual_add_f32 v25, 1.0, v25 :: v_dual_add_f32 v24, 1.0, v24
@@ -22328,69 +21515,8 @@ define <60 x half> @bitcast_v30f32_to_v60f16(<30 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB32_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v30f32_to_v60f16:
@@ -25387,140 +24513,13 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v30f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB34_4
-; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
-; GFX11-TRUE16-NEXT: .LBB34_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -25551,6 +24550,7 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -28871,76 +27871,13 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v15i64_to_v60i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v28, vcc_lo, v28, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v29, null, 0, v29, vcc_lo
@@ -28979,69 +27916,8 @@ define <60 x i16> @bitcast_v15i64_to_v60i16(<15 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB40_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v15i64_to_v60i16:
@@ -31476,140 +30352,13 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB42_4
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB42_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
-; GFX11-TRUE16-NEXT: .LBB42_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -31640,6 +30389,7 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -33710,76 +32460,13 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v15i64_to_v60f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v28, vcc_lo, v28, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v29, null, 0, v29, vcc_lo
@@ -33818,69 +32505,8 @@ define <60 x half> @bitcast_v15i64_to_v60f16(<15 x i64> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB44_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v15i64_to_v60f16:
@@ -36459,140 +35085,13 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB46_4
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB46_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
-; GFX11-TRUE16-NEXT: .LBB46_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -36623,6 +35122,7 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -38652,76 +37152,13 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v15f64_to_v60i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
@@ -38737,69 +37174,8 @@ define <60 x i16> @bitcast_v15f64_to_v60i16(<15 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v15f64_to_v60i16:
@@ -41584,140 +39960,13 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v15f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
-; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
-; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
@@ -41748,6 +39997,7 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -43773,76 +42023,13 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v15f64_to_v60f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v30
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
-; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
+; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_2: ; %Flow
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_4
-; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[28:29], v[28:29], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[26:27], v[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[24:25], v[24:25], 1.0
@@ -43858,69 +42045,8 @@ define <60 x half> @bitcast_v15f64_to_v60f16(<15 x double> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v0
-; GFX11-TRUE16-NEXT: .LBB52_4: ; %end
+; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v15f64_to_v60f16:
@@ -46849,140 +44975,13 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v15f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_3
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
-; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_4
-; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
-; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-; GFX11-TRUE16-NEXT: .LBB54_3: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
-; GFX11-TRUE16-NEXT: .LBB54_4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v31.l
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
@@ -47013,6 +45012,7 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -49656,36 +47656,6 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60i16_to_v60f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -49693,36 +47663,6 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0]
@@ -49748,73 +47688,13 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v84.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v60f16:
@@ -52517,36 +50397,6 @@ define <60 x i16> @bitcast_v60f16_to_v60i16(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v60f16_to_v60i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v30
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
@@ -52554,36 +50404,6 @@ define <60 x i16> @bitcast_v60f16_to_v60i16(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1]
@@ -52609,73 +50429,13 @@ define <60 x i16> @bitcast_v60f16_to_v60i16(<60 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v31.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v83.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v84.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v60i16:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 374626a2578fb5..969385f9b0fe2b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -554,53 +554,48 @@ define <12 x i8> @bitcast_v3i32_to_v12i8(<3 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v3i32_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v11, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v1
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB4_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[10:11]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
-; GFX11-TRUE16-NEXT: .LBB4_2: ; %Flow
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB4_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
; GFX11-TRUE16-NEXT: .LBB4_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v11.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v10.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v13.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2111,74 +2106,75 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v3i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v3
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v5 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v11 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: .LBB10_2: ; %end
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
+; GFX11-TRUE16-NEXT: .LBB10_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v3i32:
@@ -3873,52 +3869,47 @@ define <12 x i8> @bitcast_v3f32_to_v12i8(<3 x float> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v3f32_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v11, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v11, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v1
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB20_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[10:11]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
-; GFX11-TRUE16-NEXT: .LBB20_2: ; %Flow
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB20_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 1.0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
; GFX11-TRUE16-NEXT: .LBB20_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v11.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v10.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v13.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5459,74 +5450,75 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v3f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v3
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v4, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB26_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB26_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v5 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v11 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v6, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v7 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_cndmask_b32 v1, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v11, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: .LBB26_2: ; %end
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
+; GFX11-TRUE16-NEXT: .LBB26_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v3f32:
@@ -8143,110 +8135,112 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v14, v1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8_hi16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB38_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[2:3]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.h
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
; GFX11-TRUE16-NEXT: .LBB38_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB38_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v14.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v13.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, 0x7fc07fc0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, 0x7fc07fc0
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v7, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v9, v10 :: v_dual_lshlrev_b32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v4 :: v_dual_add_f32 v4, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v6.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v12, v4, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v0, v0, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v10.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v12, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v10, v9, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v0, v7, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v0, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[16:17]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v16
; GFX11-TRUE16-NEXT: .LBB38_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v8.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v16.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v14.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v12i8:
@@ -9919,57 +9913,50 @@ define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6f16_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v2 :: v_dual_mov_b32 v14, v1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v13
-; GFX11-TRUE16-NEXT: .LBB42_2: ; %Flow
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[12:13]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, 0x7e007e00
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0x7e007e00
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[12:13]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v12
; GFX11-TRUE16-NEXT: .LBB42_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v14.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6f16_to_v12i8:
@@ -11329,56 +11316,50 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6i16_to_v12i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v11, v0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v13, v1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v0
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14_lo16
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
-; GFX11-TRUE16-NEXT: .LBB46_2: ; %Flow
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[10:11]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[12:13]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v12
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v0, 3 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v0, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[8:9]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[10:11]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[12:13]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v12
; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v12.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v10.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v14.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6i16_to_v12i8:
@@ -11962,72 +11943,74 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v6bf16_to_v6f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
-; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v3
-; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6
+; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v5, v2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
+; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
-; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
+; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v7 :: v_dual_add_f32 v4, 0x40c00000, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v11, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v0, v7, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_f32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v11, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v5, v8, v9
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
+; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v6bf16_to_v6f16:
@@ -13081,67 +13064,58 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v6, v7 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v6, v7 :: v_dual_and_b32 v1, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v4, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v4, 0x7fff
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_add3_u32 v8, v9, v5, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v8, v9 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v8, v10, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v11, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v13, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.h
; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 3e3b5ac65eabc2..dc1801f9b549f8 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -16259,11 +16259,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-TRUE16-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX1164-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
-; GFX1164-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX1164-TRUE16-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX1164-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX1164-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1164-TRUE16-NEXT: v_add_f32_e32 v0, s11, v0
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164-TRUE16-NEXT: v_add_f32_e32 v2, s11, v2
+; GFX1164-TRUE16-NEXT: v_add_f32_e32 v2, s10, v2
; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX1164-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1164-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
@@ -16273,16 +16273,14 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1164-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1164-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0)
-; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
-; GFX1164-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1164-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
+; GFX1164-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX1164-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1164-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16383,11 +16381,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1132-TRUE16-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX1132-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1132-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
-; GFX1132-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX1132-TRUE16-NEXT: v_add_f32_e32 v0, s9, v0
+; GFX1132-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX1132-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1132-TRUE16-NEXT: v_add_f32_e32 v0, s10, v0
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132-TRUE16-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX1132-TRUE16-NEXT: v_add_f32_e32 v2, s9, v2
; GFX1132-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
@@ -16396,15 +16394,12 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1132-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
; GFX1132-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1132-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1132-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1132-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1132-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
-; GFX1132-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX1132-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
; GFX1132-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1132-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1132-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1132-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
; GFX1132-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc
; GFX1132-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16498,11 +16493,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264-TRUE16-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX1264-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
-; GFX1264-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX1264-TRUE16-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX1264-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX1264-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1264-TRUE16-NEXT: v_add_f32_e32 v0, s11, v0
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1264-TRUE16-NEXT: v_add_f32_e32 v2, s11, v2
+; GFX1264-TRUE16-NEXT: v_add_f32_e32 v2, s10, v2
; GFX1264-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
@@ -16512,15 +16507,12 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1264-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc
+; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX1264-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1264-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
-; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1264-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX1264-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1264-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
+; GFX1264-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v3, v1
; GFX1264-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1264-TRUE16-NEXT: v_mov_b32_e32 v2, v0
@@ -16615,11 +16607,11 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-TRUE16-NEXT: .LBB21_1: ; %atomicrmw.start
; GFX1232-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1232-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
-; GFX1232-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX1232-TRUE16-NEXT: v_add_f32_e32 v0, s9, v0
+; GFX1232-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
+; GFX1232-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
+; GFX1232-TRUE16-NEXT: v_add_f32_e32 v0, s10, v0
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1232-TRUE16-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX1232-TRUE16-NEXT: v_add_f32_e32 v2, s9, v2
; GFX1232-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1232-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
@@ -16629,15 +16621,12 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1232-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX1232-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1232-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
-; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1232-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX1232-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1232-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
+; GFX1232-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX1232-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1232-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
; GFX1232-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
index f53877ed0d240b..d9546ee37ec35f 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
@@ -21,7 +21,7 @@ define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, 0xffff, s2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s3
; GFX11-TRUE16-NEXT: s_not_b32 s3, s4
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-math.ll b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
index f0b3e305e76209..ec4a623f43007b 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-math.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
@@ -515,7 +515,7 @@ define amdgpu_ps float @test_clamp_bf16_hi16(<2 x bfloat> %src) {
; TRUE16-NEXT: s_mov_b64 s[64:65], 0
; TRUE16-NEXT: v_nop
; TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index d3e89cd1e469ba..38bf0c95bd77e3 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -9220,22 +9220,39 @@ define bfloat @v_fadd_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fadd_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fadd_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fadd_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fadd_bf16:
; GFX1250: ; %bb.0:
@@ -9360,10 +9377,10 @@ define <2 x bfloat> @v_fadd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fadd_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
@@ -9375,14 +9392,12 @@ define <2 x bfloat> @v_fadd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v2bf16:
@@ -9575,38 +9590,36 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fadd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v3bf16:
@@ -9844,49 +9857,41 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fadd_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
; GFX11TRUE16-NEXT: v_dual_add_f32 v3, v7, v6 :: v_dual_add_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v4bf16:
@@ -10290,86 +10295,77 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v12, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v9 :: v_dual_and_b32 v9, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11TRUE16-NEXT: v_dual_add_f32 v7, v11, v10 :: v_dual_and_b32 v10, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v3, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v10, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v6, v2, v6
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v11, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v12, v11
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v9, v14, v13
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v10, v11 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v8.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v8bf16:
@@ -11122,175 +11118,152 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_dual_add_f32 v15, v19, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v6, v6, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_and_b32 v21, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11TRUE16-NEXT: v_bfe_u32 v17, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v16, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v14, v6, v14 :: v_dual_add_f32 v15, v7, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v6, v17, v18 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_add_f32_e32 v14, v19, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v15.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v17, v18 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_dual_add_f32 v13, v20, v13 :: v_dual_and_b32 v20, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v12, v4, v12 :: v_dual_add_f32 v13, v5, v13
+; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v19, v18 :: v_dual_add_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v3, v11
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v14.l
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_add_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_dual_add_f32 v12, v21, v20 :: v_dual_and_b32 v21, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_add_f32_e32 v12, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v17, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v20, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v13.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v11.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v12, v17 :: v_dual_and_b32 v17, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v12, v19, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v16, v20, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v21, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v18, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v9, 16, 1
+; GFX11TRUE16-NEXT: v_dual_add_f32 v10, v2, v10 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v11, v3, v11
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v19, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v10, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v18, v19 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v2, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v9, v20, v19
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_add_f32 v17, v22, v21 :: v_dual_add_f32 v0, v0, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v17, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v16bf16:
@@ -12751,317 +12724,274 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_add_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_add_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_dual_add_f32 v18, v84, v83 :: v_dual_add_f32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_add_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_add_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_add_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_add_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_add_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_add_f32 v26, v52, v51 :: v_dual_add_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_dual_add_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_add_f32_e32 v22, v6, v22
+; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_add_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_dual_add_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_dual_add_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_dual_add_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_add_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_dual_add_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_add_f32_e32 v34, v36, v35
+; GFX11TRUE16-NEXT: v_add_f32_e32 v36, v48, v39
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX11TRUE16-NEXT: v_dual_add_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_add_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_add_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_add_f32_e32 v35, v38, v37
+; GFX11TRUE16-NEXT: v_dual_add_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11TRUE16-NEXT: v_add_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_add_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_dual_add_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11TRUE16-NEXT: v_add_f32_e32 v25, v9, v25
+; GFX11TRUE16-NEXT: v_dual_add_f32 v28, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v29, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v149, v13, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
+; GFX11TRUE16-NEXT: v_add_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v49, v66, v65
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_add_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_add_f32_e32 v51, v70, v69
+; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
+; GFX11TRUE16-NEXT: v_add_f32_e32 v52, v80, v71
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v25.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.h, v29.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v24.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v23.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v22.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v19.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v18.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v28.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v33.h
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_f32_e32 v15, v15, v18
-; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v31, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_add_f32 v15, v15, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11TRUE16-NEXT: v_add_f32_e32 v17, v31, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v15
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v17, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v16, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v18.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fadd_v32bf16:
@@ -13436,21 +13366,37 @@ define bfloat @v_fadd_bf16_fpimm_0(bfloat %arg0) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fadd_bf16_fpimm_0:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fadd_bf16_fpimm_0:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fadd_bf16_fpimm_0:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fadd_bf16_fpimm_0:
; GFX1250: ; %bb.0:
@@ -13528,21 +13474,37 @@ define bfloat @v_fadd_bf16_fpimm_1(bfloat %arg0) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fadd_bf16_fpimm_1:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v0, 0x42280000, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fadd_bf16_fpimm_1:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, 0x42280000, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fadd_bf16_fpimm_1:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, 0x42280000, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fadd_bf16_fpimm_1:
; GFX1250: ; %bb.0:
@@ -13626,22 +13588,39 @@ define bfloat @v_fsub_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fsub_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fsub_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fsub_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fsub_bf16:
; GFX1250: ; %bb.0:
@@ -13766,10 +13745,10 @@ define <2 x bfloat> @v_fsub_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fsub_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_sub_f32_e32 v2, v3, v2
@@ -13781,14 +13760,12 @@ define <2 x bfloat> @v_fsub_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fsub_v2bf16:
@@ -13981,38 +13958,36 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fsub_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11TRUE16-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fsub_v3bf16:
@@ -14250,49 +14225,41 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fsub_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX11TRUE16-NEXT: v_dual_sub_f32 v3, v7, v6 :: v_dual_sub_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fsub_v4bf16:
@@ -14421,22 +14388,39 @@ define bfloat @v_fmul_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fmul_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fmul_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fmul_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fmul_bf16:
; GFX1250: ; %bb.0:
@@ -14561,10 +14545,10 @@ define <2 x bfloat> @v_fmul_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fmul_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v3, v2
@@ -14576,14 +14560,12 @@ define <2 x bfloat> @v_fmul_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v2bf16:
@@ -14776,38 +14758,36 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fmul_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v3bf16:
@@ -15045,49 +15025,41 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_fmul_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX11TRUE16-NEXT: v_dual_mul_f32 v3, v7, v6 :: v_dual_mul_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v4bf16:
@@ -15491,86 +15463,77 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v2, v2, v6 :: v_dual_mul_f32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v12, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v9 :: v_dual_and_b32 v9, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v7, v11, v10 :: v_dual_and_b32 v10, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v3, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v10, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v2, v6
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v11, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v12, v11
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v9, v14, v13
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v10, v11 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v8.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v8bf16:
@@ -16323,175 +16286,152 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v15, v19, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v6, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_and_b32 v21, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11TRUE16-NEXT: v_bfe_u32 v17, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v16, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v14, v6, v14 :: v_dual_mul_f32 v15, v7, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v6, v17, v18 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v14, v19, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v15.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v17, v18 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v13, v20, v13 :: v_dual_and_b32 v20, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v12, v4, v12 :: v_dual_mul_f32 v13, v5, v13
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v19, v18 :: v_dual_mul_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v3, v11
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v14.l
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_mul_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v12, v21, v20 :: v_dual_and_b32 v21, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v12, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v17, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v20, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v13.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v11.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v12, v17 :: v_dual_and_b32 v17, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v12, v19, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v16, v20, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v21, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v18, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v9, 16, 1
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v10, v2, v10 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v11, v3, v11
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v19, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v10, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v18, v19 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v2, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v9, v20, v19
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v17, v22, v21 :: v_dual_mul_f32 v0, v0, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v17, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v16bf16:
@@ -17952,317 +17892,274 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v18, v84, v83 :: v_dual_mul_f32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v26, v52, v51 :: v_dual_mul_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v22, v6, v22
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v34, v36, v35
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v36, v48, v39
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v35, v38, v37
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v25, v9, v25
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v28, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v29, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v149, v13, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v49, v66, v65
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v51, v70, v69
+; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v52, v80, v71
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v25.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.h, v29.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v24.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v23.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v22.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v19.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v18.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v28.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v33.h
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v15, v15, v18
-; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v31, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_mul_f32 v15, v15, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v17, v31, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v15
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v17, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v16, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v18.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmul_v32bf16:
@@ -18703,37 +18600,69 @@ define bfloat @v_fdiv_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fdiv_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
-; GFX11-NEXT: v_rcp_f32_e32 v3, v2
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
-; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
-; GFX11-NEXT: v_mul_f32_e32 v4, v5, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v6, -v2, v4, v5
-; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v2, -v2, v4, v5
-; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fdiv_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11TRUE16-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v4, v5, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v6, -v2, v4, v5
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v6, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v2, -v2, v4, v5
+; GFX11TRUE16-NEXT: v_div_fmas_f32 v2, v2, v3, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fdiv_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11FAKE16-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11FAKE16-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v4, v5, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v6, -v2, v4, v5
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v4, v6, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v2, -v2, v4, v5
+; GFX11FAKE16-NEXT: v_div_fmas_f32 v2, v2, v3, v4
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fdiv_bf16:
; GFX1250: ; %bb.0:
@@ -19192,22 +19121,39 @@ define bfloat @v_minnum_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_minnum_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_minnum_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_minnum_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_minnum_bf16:
; GFX1250: ; %bb.0:
@@ -19340,10 +19286,10 @@ define <2 x bfloat> @v_minnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_minnum_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v3, v2
@@ -19355,14 +19301,12 @@ define <2 x bfloat> @v_minnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v2bf16:
@@ -19567,38 +19511,36 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_minnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v3bf16:
@@ -19852,49 +19794,41 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_minnum_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
; GFX11TRUE16-NEXT: v_dual_min_f32 v3, v7, v6 :: v_dual_min_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v4bf16:
@@ -20330,86 +20264,77 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v2, v2, v6 :: v_dual_min_f32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v12, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v9 :: v_dual_and_b32 v9, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11TRUE16-NEXT: v_dual_min_f32 v7, v11, v10 :: v_dual_and_b32 v10, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v3, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v10, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v6, v2, v6
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v11, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v12, v11
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_min_f32 v0, v0, v4 :: v_dual_min_f32 v9, v14, v13
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v10, v11 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v8.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v8bf16:
@@ -21226,175 +21151,152 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_dual_min_f32 v15, v19, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v6, v6, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_and_b32 v21, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11TRUE16-NEXT: v_bfe_u32 v17, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v16, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v14, v6, v14 :: v_dual_min_f32 v15, v7, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v6, v17, v18 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_min_f32_e32 v14, v19, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v15.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v17, v18 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_dual_min_f32 v13, v20, v13 :: v_dual_and_b32 v20, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v12, v4, v12 :: v_dual_min_f32 v13, v5, v13
+; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v19, v18 :: v_dual_min_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v3, v11
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v14.l
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_min_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_dual_min_f32 v12, v21, v20 :: v_dual_and_b32 v21, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_min_f32_e32 v12, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v17, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v20, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v13.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v11.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v12, v17 :: v_dual_and_b32 v17, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v12, v19, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v16, v20, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v21, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v18, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v9, 16, 1
+; GFX11TRUE16-NEXT: v_dual_min_f32 v10, v2, v10 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v11, v3, v11
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v19, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v10, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v18, v19 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v2, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_f32_e32 v9, v20, v19
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_min_f32 v17, v22, v21 :: v_dual_min_f32 v0, v0, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v17, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v16bf16:
@@ -22983,317 +22885,274 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_min_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_min_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_dual_min_f32 v18, v84, v83 :: v_dual_min_f32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_min_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_min_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_min_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_min_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_min_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_min_f32 v26, v52, v51 :: v_dual_min_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_dual_min_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_min_f32_e32 v22, v6, v22
+; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_min_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_dual_min_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_dual_min_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_dual_min_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_min_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_dual_min_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_min_f32_e32 v34, v36, v35
+; GFX11TRUE16-NEXT: v_min_f32_e32 v36, v48, v39
+; GFX11TRUE16-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX11TRUE16-NEXT: v_dual_min_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_min_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_min_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_min_f32_e32 v35, v38, v37
+; GFX11TRUE16-NEXT: v_dual_min_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11TRUE16-NEXT: v_min_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_min_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_dual_min_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11TRUE16-NEXT: v_min_f32_e32 v25, v9, v25
+; GFX11TRUE16-NEXT: v_dual_min_f32 v28, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v29, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v149, v13, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
+; GFX11TRUE16-NEXT: v_min_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v49, v66, v65
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_min_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_min_f32_e32 v51, v70, v69
+; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
+; GFX11TRUE16-NEXT: v_min_f32_e32 v52, v80, v71
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
+; GFX11TRUE16-NEXT: v_min_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v25.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.h, v29.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v24.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v23.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v22.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v19.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v18.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v28.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v33.h
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_f32_e32 v15, v15, v18
-; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v31, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_min_f32 v15, v15, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11TRUE16-NEXT: v_min_f32_e32 v17, v31, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v15
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v17, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v16, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v18.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_minnum_v32bf16:
@@ -23687,22 +23546,39 @@ define bfloat @v_maxnum_bf16(bfloat %a, bfloat %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_maxnum_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_maxnum_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_maxnum_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_maxnum_bf16:
; GFX1250: ; %bb.0:
@@ -23835,10 +23711,10 @@ define <2 x bfloat> @v_maxnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_maxnum_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v1
; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v3, v2
@@ -23850,14 +23726,12 @@ define <2 x bfloat> @v_maxnum_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v2bf16:
@@ -24062,38 +23936,36 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_maxnum_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v3
; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v3bf16:
@@ -24347,49 +24219,41 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX11TRUE16-LABEL: v_maxnum_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
; GFX11TRUE16-NEXT: v_dual_max_f32 v3, v7, v6 :: v_dual_max_f32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v4bf16:
@@ -24825,86 +24689,77 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v2, v2, v6 :: v_dual_max_f32 v3, v3, v7
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
-; GFX11TRUE16-NEXT: v_bfe_u32 v12, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v9, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v12, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v9 :: v_dual_and_b32 v9, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v8.l
-; GFX11TRUE16-NEXT: v_dual_max_f32 v7, v11, v10 :: v_dual_and_b32 v10, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v3, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v10, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v8, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v10, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v6, v2, v6
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v11, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v12, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v6, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v12, v11
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_max_f32 v0, v0, v4 :: v_dual_max_f32 v9, v14, v13
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v5, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v10, v11 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v9, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v5, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v13, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v8.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v12, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v8bf16:
@@ -25721,175 +25576,152 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v7, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_dual_max_f32 v15, v19, v15 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v6, v6, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_and_b32 v21, 0xffff0000, v13
; GFX11TRUE16-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
; GFX11TRUE16-NEXT: v_bfe_u32 v17, v16, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v16, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v14, v6, v14 :: v_dual_max_f32 v15, v7, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v17, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v16.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v6
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v6, v17, v18 :: v_dual_lshlrev_b32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_max_f32_e32 v14, v19, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v17, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v14
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v15.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v17, v18 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v5, v13
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v14, v16, v20 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_dual_max_f32 v13, v20, v13 :: v_dual_and_b32 v20, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v13, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v14.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v12, v4, v12 :: v_dual_max_f32 v13, v5, v13
+; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v19, v18 :: v_dual_max_f32 v17, v22, v21
+; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
+; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v16 :: v_dual_and_b32 v20, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v19, v13, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v3, v11
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v14.l
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v13, v17, v22 :: v_dual_max_f32 v4, v4, v12
-; GFX11TRUE16-NEXT: v_dual_max_f32 v12, v21, v20 :: v_dual_and_b32 v21, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v4, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_max_f32_e32 v12, v22, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v3, 16, 1
-; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v2, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v17, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v2, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v10, v17, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v20, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v13.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v11.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v12, v17 :: v_dual_and_b32 v17, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v22, v12, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v12, v19, v18
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v21, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v16, v20, v19
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v12.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v16, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v21, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v12, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v18, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_max_f32_e32 v1, v1, v9
-; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v18, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v19, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v9, 16, 1
+; GFX11TRUE16-NEXT: v_dual_max_f32 v10, v2, v10 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v11, v3, v11
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v16
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11TRUE16-NEXT: v_add3_u32 v17, v20, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v19, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v20, v10, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v18, v19 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v2, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v20, v10, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v17, v19 :: v_dual_lshlrev_b32 v19, 16, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v11.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v9, v20, v19
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v16, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v16, v1, 16, 1
+; GFX11TRUE16-NEXT: v_dual_max_f32 v17, v22, v21 :: v_dual_max_f32 v0, v0, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v1, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v21, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v20, v21, v0, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v17, v17, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v17, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v9.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v20, v21, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v16bf16:
@@ -27478,317 +27310,274 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: scratch_load_b32 v32, off, s32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_max_f32_e32 v5, v5, v21
-; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
+; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v20, v4, v20 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v17
; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v103, v5, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v3, v3, v19
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v119, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_dual_max_f32 v19, v82, v81 :: v_dual_lshlrev_b32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v129, v19, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v19
-; GFX11TRUE16-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX11TRUE16-NEXT: v_dual_max_f32 v18, v84, v83 :: v_dual_max_f32 v9, v9, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v19, 0x7fff
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_u32 v131, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v2
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v86, v85
-; GFX11TRUE16-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v39, 0xffff0000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v133, v18, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
-; GFX11TRUE16-NEXT: v_bfe_u32 v83, v8, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v18
-; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v23
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v20, 16, 1
; GFX11TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11TRUE16-NEXT: v_dual_max_f32 v24, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
-; GFX11TRUE16-NEXT: v_max_f32_e32 v7, v7, v23
-; GFX11TRUE16-NEXT: v_dual_max_f32 v23, v66, v65 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v85, v24, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v97, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v23
-; GFX11TRUE16-NEXT: v_bfe_u32 v87, v7, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_max_f32_e32 v4, v4, v20
-; GFX11TRUE16-NEXT: v_max_f32_e32 v20, v80, v71
-; GFX11TRUE16-NEXT: v_bfe_u32 v71, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v9
-; GFX11TRUE16-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_lshlrev_b32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_dual_max_f32 v26, v52, v51 :: v_dual_max_f32 v25, v54, v53
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v6, v6, v22
-; GFX11TRUE16-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v24
+; GFX11TRUE16-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v24, 16, v24
+; GFX11TRUE16-NEXT: v_dual_max_f32 v23, v7, v23 :: v_dual_and_b32 v82, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_max_f32_e32 v22, v6, v22
+; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v86, v85
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v20
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v27
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v22, 16, 1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v19
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v23
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v22
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v26
+; GFX11TRUE16-NEXT: v_dual_max_f32 v21, v5, v21 :: v_dual_lshlrev_b32 v26, 16, v26
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v19, v3, v19 :: v_dual_and_b32 v52, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_dual_max_f32 v27, v11, v27 :: v_dual_and_b32 v36, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v25
+; GFX11TRUE16-NEXT: v_dual_max_f32 v26, v10, v26 :: v_dual_lshlrev_b32 v13, 16, v13
+; GFX11TRUE16-NEXT: v_dual_max_f32 v24, v8, v24 :: v_dual_and_b32 v35, 0xffff0000, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v30
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX11TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_max_f32_e32 v22, v68, v67
-; GFX11TRUE16-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v21, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v19, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v29, v13, v29 :: v_dual_and_b32 v38, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_dual_max_f32 v33, v34, v33 :: v_dual_lshlrev_b32 v30, 16, v30
+; GFX11TRUE16-NEXT: v_max_f32_e32 v34, v36, v35
+; GFX11TRUE16-NEXT: v_max_f32_e32 v36, v48, v39
+; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX11TRUE16-NEXT: v_dual_max_f32 v48, v64, v55 :: v_dual_and_b32 v37, 0xffff0000, v28
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_max_f32 v29, v38, v37 :: v_dual_lshlrev_b32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX11TRUE16-NEXT: v_max_f32_e32 v28, v48, v39
-; GFX11TRUE16-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
-; GFX11TRUE16-NEXT: v_bfe_u32 v39, v13, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v35, v14, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v128, 0x400000, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11TRUE16-NEXT: v_max_f32_e32 v35, v38, v37
+; GFX11TRUE16-NEXT: v_dual_max_f32 v30, v14, v30 :: v_dual_and_b32 v31, 0xffff0000, v15
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v37, v30, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v33, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v33
+; GFX11TRUE16-NEXT: v_max_f32_e32 v18, v2, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v33, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v33
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v27, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v30, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v35, v35, v14, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v33, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v37, v37, v30, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v49, v29, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v39, v39, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v34, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11TRUE16-NEXT: v_or_b32_e32 v50, 0x400000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v51, v12, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v49, v49, v29, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v12
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v35, v36, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v30
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v34, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v30, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v27, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v53, v28, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v51, v51, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v54, 0x400000, v28
-; GFX11TRUE16-NEXT: v_bfe_u32 v55, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v37, v38, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_add3_u32 v53, v53, v28, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v11
-; GFX11TRUE16-NEXT: v_bfe_u32 v65, v27, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v55, v55, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v39, v48, vcc_lo
+; GFX11TRUE16-NEXT: v_dual_max_f32 v39, v54, v53 :: v_dual_lshlrev_b32 v12, 16, v12
+; GFX11TRUE16-NEXT: v_dual_max_f32 v54, v84, v83 :: v_dual_lshlrev_b32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v34
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v29, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v36, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
+; GFX11TRUE16-NEXT: v_max_f32_e32 v25, v9, v25
+; GFX11TRUE16-NEXT: v_dual_max_f32 v28, v12, v28 :: v_dual_lshlrev_b32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v29
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v29, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v149, v13, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v27
-; GFX11TRUE16-NEXT: v_bfe_u32 v67, v10, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v27, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v49, v50, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v69, v26, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v26
-; GFX11TRUE16-NEXT: v_bfe_u32 v81, v25, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v51, v52, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v35
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v28, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v35, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v28
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v8, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
+; GFX11TRUE16-NEXT: v_add3_u32 v148, v12, v28, 0x7fff
+; GFX11TRUE16-NEXT: v_max_f32_e32 v37, v50, v49
+; GFX11TRUE16-NEXT: v_or_b32_e32 v55, 0x400000, v36
+; GFX11TRUE16-NEXT: v_or_b32_e32 v64, 0x400000, v27
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v10, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v26, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v25
-; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v25, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v99, v6, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v6
-; GFX11TRUE16-NEXT: v_bfe_u32 v101, v22, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v55, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v49, v66, v65
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v37, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v37
+; GFX11TRUE16-NEXT: v_max_f32_e32 v38, v52, v51
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v148, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_max_f32_e32 v51, v70, v69
+; GFX11TRUE16-NEXT: v_bfe_u32 v69, v38, 16, 1
+; GFX11TRUE16-NEXT: v_max_f32_e32 v52, v80, v71
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v149, v55, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v113, v21, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v115, v4, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v65, v66, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v117, v20, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v25, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v38, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v25
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v150, v64, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v25, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v24, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v48, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v65, v66, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v50, v68, v67
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v26, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v26
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v20
-; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v48, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v49, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v49
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v67, v68, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v50
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v51, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v69, v70, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v51
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v52, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v52
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v71, v80, vcc_lo
+; GFX11TRUE16-NEXT: v_max_f32_e32 v53, v82, v81
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v39, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v39
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v129, v53, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v130, 0x400000, v53
+; GFX11TRUE16-NEXT: v_bfe_u32 v131, v18, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v132, 0x400000, v18
+; GFX11TRUE16-NEXT: v_add3_u32 v129, v129, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v81, v82, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_bfe_u32 v135, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v131, v131, v18, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v144, 0x400000, v1
; GFX11TRUE16-NEXT: v_bfe_u32 v147, v0, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v69, v70, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v83, v84, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11TRUE16-NEXT: v_add3_u32 v135, v135, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v133, v54, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_add3_u32 v147, v147, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v71, v80, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v81, v82, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v83, v84, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v85, v86, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v25.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v26.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v28.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.h, v29.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.h, v30.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v97, v98, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v24.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.h, v16.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v134, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v145, v17, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v133, v133, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v146, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v87, v96, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11TRUE16-NEXT: v_add3_u32 v145, v145, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v24.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v101, v102, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v23.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v25.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v26.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v27.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v99, v100, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v113, v114, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v22.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v103, v112, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v117, v118, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v129, v130, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v20.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v131, v132, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v119, v128, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v129, v130, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v131, v132, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v19.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v135, v144, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v135, v144, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v18.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v147, v33, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v133, v134, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v28.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v145, v146, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v33.h
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v32
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_max_f32_e32 v15, v15, v18
-; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v31, v17
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_dual_max_f32 v15, v15, v17 :: v_dual_and_b32 v18, 0xffff0000, v32
+; GFX11TRUE16-NEXT: v_max_f32_e32 v17, v31, v18
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v15
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v15, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v17, 0x7fff
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v15, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v15, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v19, v16, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.h, v17.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.l, v18.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_maxnum_v32bf16:
@@ -28270,42 +28059,79 @@ define bfloat @v_sqrt_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_sqrt_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sqrt_f32_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_add_nc_u32_e32 v2, -1, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 1, v1
-; GFX11-NEXT: v_fma_f32 v4, -v2, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f32 v5, -v3, v1, v0
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
-; GFX11-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_sqrt_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11TRUE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11TRUE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_sqrt_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11FAKE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_sqrt_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -28586,67 +28412,129 @@ define bfloat @v_rsq_bf16(bfloat %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rsq_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sqrt_f32_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_add_nc_u32_e32 v2, -1, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 1, v1
-; GFX11-NEXT: v_fma_f32 v4, -v2, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f32 v5, -v3, v1, v0
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
-; GFX11-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
-; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
-; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v5, -v1, v3, v4
-; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v1, -v1, v3, v4
-; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_rsq_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11TRUE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11TRUE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
+; GFX11TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
+; GFX11TRUE16-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v4, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v5, -v1, v3, v4
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v5, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v1, -v1, v3, v4
+; GFX11TRUE16-NEXT: v_div_fmas_f32 v1, v1, v2, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_rsq_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11FAKE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
+; GFX11FAKE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
+; GFX11FAKE16-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v4, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v5, -v1, v3, v4
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v1, -v1, v3, v4
+; GFX11FAKE16-NEXT: v_div_fmas_f32 v1, v1, v2, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_rsq_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -28928,67 +28816,129 @@ define bfloat @v_neg_rsq_bf16(bfloat %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_neg_rsq_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sqrt_f32_e32 v1, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_add_nc_u32_e32 v2, -1, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 1, v1
-; GFX11-NEXT: v_fma_f32 v4, -v2, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_fma_f32 v5, -v3, v1, v0
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
-; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
-; GFX11-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, -1.0
-; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -1.0, v0, -1.0
-; GFX11-NEXT: v_rcp_f32_e32 v2, v1
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
-; GFX11-NEXT: v_mul_f32_e32 v3, v4, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v5, -v1, v3, v4
-; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fma_f32 v1, -v1, v3, v4
-; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_neg_rsq_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11TRUE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11TRUE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_div_scale_f32 v1, null, v0, v0, -1.0
+; GFX11TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, -1.0, v0, -1.0
+; GFX11TRUE16-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v3, v4, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v5, -v1, v3, v4
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v5, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fma_f32 v1, -v1, v3, v4
+; GFX11TRUE16-NEXT: v_div_fmas_f32 v1, v1, v2, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_neg_rsq_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_sqrt_f32_e32 v1, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v1
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v3, 1, v1
+; GFX11FAKE16-NEXT: v_fma_f32 v4, -v2, v1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_fma_f32 v5, -v3, v1, v0
+; GFX11FAKE16-NEXT: v_cmp_ge_f32_e64 s0, 0, v4
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v2, s0
+; GFX11FAKE16-NEXT: v_cmp_lt_f32_e64 s0, 0, v5
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v2, 0x37800000, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_class_f32_e64 vcc_lo, v0, 0x260
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_div_scale_f32 v1, null, v0, v0, -1.0
+; GFX11FAKE16-NEXT: v_div_scale_f32 v4, vcc_lo, -1.0, v0, -1.0
+; GFX11FAKE16-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v3, v4, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v5, -v1, v3, v4
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fma_f32 v1, -v1, v3, v4
+; GFX11FAKE16-NEXT: v_div_fmas_f32 v1, v1, v2, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_neg_rsq_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -29082,21 +29032,37 @@ define bfloat @v_ldexp_bf16_i32(bfloat %a, i32 %b) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_ldexp_bf16_i32:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_ldexp_bf16_i32:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_ldexp_bf16_i32:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_ldexp_bf16_i32:
; GFX1250: ; %bb.0:
@@ -29190,22 +29156,39 @@ define { bfloat, i16 } @v_frexp_bf16_i16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_frexp_bf16_i16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_frexp_mant_f32_e32 v0, v1
-; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
-; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_frexp_bf16_i16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_frexp_mant_f32_e32 v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_frexp_bf16_i16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_frexp_mant_f32_e32 v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
+; GFX11FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_frexp_bf16_i16:
; GFX1250: ; %bb.0:
@@ -29388,36 +29371,67 @@ define bfloat @v_log_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_log_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX11-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_log_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX11TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_log_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX11FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_log_bf16:
; GFX1250: ; %bb.0:
@@ -29555,28 +29569,51 @@ define bfloat @v_log2_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_log2_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_log2_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_log2_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_log2_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -29757,36 +29794,67 @@ define bfloat @v_log10_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_log10_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX11-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, vcc_lo
-; GFX11-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_log10_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX11TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_log10_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX11FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_log10_bf16:
; GFX1250: ; %bb.0:
@@ -29986,37 +30054,69 @@ define bfloat @v_exp_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_exp_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX11-NEXT: v_rndne_f32_e32 v2, v1
-; GFX11-NEXT: v_fma_f32 v3, 0x3fb8aa3b, v0, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
-; GFX11-NEXT: v_fmamk_f32 v3, v0, 0x32a5705f, v3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_exp_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
+; GFX11TRUE16-NEXT: v_rndne_f32_e32 v2, v1
+; GFX11TRUE16-NEXT: v_fma_f32 v3, 0x3fb8aa3b, v0, -v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11TRUE16-NEXT: v_fmamk_f32 v3, v0, 0x32a5705f, v3
+; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_exp_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
+; GFX11FAKE16-NEXT: v_rndne_f32_e32 v2, v1
+; GFX11FAKE16-NEXT: v_fma_f32 v3, 0x3fb8aa3b, v0, -v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11FAKE16-NEXT: v_fmamk_f32 v3, v0, 0x32a5705f, v3
+; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_exp_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -30194,28 +30294,51 @@ define bfloat @v_exp2_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_exp2_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_exp2_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_exp2_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_exp2_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -30399,37 +30522,69 @@ define bfloat @v_exp10_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_exp10_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
-; GFX11-NEXT: v_rndne_f32_e32 v2, v1
-; GFX11-NEXT: v_fma_f32 v3, 0x40549a78, v0, -v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2
-; GFX11-NEXT: v_fmamk_f32 v3, v0, 0x33979a37, v3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX11-NEXT: v_exp_f32_e32 v1, v1
-; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
-; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v0
-; GFX11-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_exp10_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
+; GFX11TRUE16-NEXT: v_rndne_f32_e32 v2, v1
+; GFX11TRUE16-NEXT: v_fma_f32 v3, 0x40549a78, v0, -v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11TRUE16-NEXT: v_fmamk_f32 v3, v0, 0x33979a37, v3
+; GFX11TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_exp10_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_mul_f32_e32 v1, 0x40549a78, v0
+; GFX11FAKE16-NEXT: v_rndne_f32_e32 v2, v1
+; GFX11FAKE16-NEXT: v_fma_f32 v3, 0x40549a78, v0, -v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2
+; GFX11FAKE16-NEXT: v_fmamk_f32 v3, v0, 0x33979a37, v3
+; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX11FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11FAKE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX11FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11FAKE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo
+; GFX11FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v0
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250TRUE16-LABEL: v_exp10_bf16:
; GFX1250TRUE16: ; %bb.0:
@@ -30564,21 +30719,37 @@ define bfloat @v_ceil_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_ceil_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ceil_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_ceil_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_ceil_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_ceil_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_ceil_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_ceil_bf16:
; GFX1250: ; %bb.0:
@@ -30661,21 +30832,37 @@ define bfloat @v_trunc_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_trunc_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_trunc_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_trunc_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_trunc_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_trunc_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_trunc_bf16:
; GFX1250: ; %bb.0:
@@ -30758,21 +30945,37 @@ define bfloat @v_rint_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_rint_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_rint_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_rint_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_rint_bf16:
; GFX1250: ; %bb.0:
@@ -30855,21 +31058,37 @@ define bfloat @v_nearbyint_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_nearbyint_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_nearbyint_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_nearbyint_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_nearbyint_bf16:
; GFX1250: ; %bb.0:
@@ -30988,28 +31207,51 @@ define bfloat @v_round_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_round_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_trunc_f32_e32 v1, v0
-; GFX11-NEXT: v_sub_f32_e32 v2, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_round_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11TRUE16-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11TRUE16-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_round_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11FAKE16-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11FAKE16-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_round_bf16:
; GFX1250: ; %bb.0:
@@ -31100,21 +31342,37 @@ define bfloat @v_roundeven_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_roundeven_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_rndne_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_roundeven_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_roundeven_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_rndne_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_roundeven_bf16:
; GFX1250: ; %bb.0:
@@ -31197,21 +31455,37 @@ define bfloat @v_floor_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_floor_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_floor_f32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_floor_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_floor_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_floor_f32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_floor_bf16:
; GFX1250: ; %bb.0:
@@ -31294,21 +31568,37 @@ define bfloat @v_canonicalize_bf16(bfloat %a) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_canonicalize_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_canonicalize_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_canonicalize_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_max_f32_e32 v0, v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_canonicalize_bf16:
; GFX1250: ; %bb.0:
@@ -34459,21 +34749,37 @@ define bfloat @v_sitofp_i16_to_bf16(i16 %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_sitofp_i16_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_sitofp_i16_to_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_sitofp_i16_to_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_sitofp_i16_to_bf16:
; GFX1250: ; %bb.0:
@@ -34581,8 +34887,8 @@ define <2 x bfloat> @v_sitofp_v2i16_to_v2bf16(<2 x i16> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v2i16_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11TRUE16-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
@@ -34598,11 +34904,8 @@ define <2 x bfloat> @v_sitofp_v2i16_to_v2bf16(<2 x i16> %x) #0 {
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v2i16_to_v2bf16:
@@ -34768,37 +35071,34 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v3i16_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v2, 16, v0
-; GFX11TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11TRUE16-NEXT: v_bfe_i32 v2, v0, 0, 16
; GFX11TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i16_to_v3bf16:
@@ -35032,35 +35332,30 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v4i16_to_v4bf16:
@@ -35184,19 +35479,33 @@ define bfloat @v_sitofp_i32_to_bf16(i32 %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_sitofp_i32_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_sitofp_i32_to_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_sitofp_i32_to_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_sitofp_i32_to_bf16:
; GFX1250: ; %bb.0:
@@ -35299,25 +35608,22 @@ define <2 x bfloat> @v_sitofp_v2i32_to_v2bf16(<2 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v2i32_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v2i32_to_v2bf16:
@@ -35472,32 +35778,29 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v3i32_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i32_to_v3bf16:
@@ -35699,39 +36002,33 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v4i32_to_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v3, v3
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v4i32_to_v4bf16:
@@ -35910,35 +36207,65 @@ define bfloat @v_sitofp_i64_to_bf16(i64 %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_sitofp_i64_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v2, v0, v1
-; GFX11-NEXT: v_cls_i32_e32 v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v2
-; GFX11-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 32, v2
-; GFX11-NEXT: v_min_u32_e32 v2, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
-; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v2
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_sitofp_i64_to_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v2, v0, v1
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v3, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v2, 32, v2
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v2
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_sitofp_i64_to_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_xor_b32_e32 v2, v0, v1
+; GFX11FAKE16-NEXT: v_cls_i32_e32 v3, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add_nc_u32_e32 v2, 32, v2
+; GFX11FAKE16-NEXT: v_min_u32_e32 v2, v3, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v1, 32, v2
+; GFX11FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_sitofp_i64_to_bf16:
; GFX1250: ; %bb.0:
@@ -36187,10 +36514,10 @@ define <2 x bfloat> @v_sitofp_v2i64_to_v2bf16(<2 x i64> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v2i64_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v4, v2, v3
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v5, v0, v1
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v6, v3
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v7, v1
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v4, v0, v1
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v5, v2, v3
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v6, v1
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v7, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v4, 31, v4
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v5
@@ -36204,39 +36531,36 @@ define <2 x bfloat> @v_sitofp_v2i64_to_v2bf16(<2 x i64> %x) #0 {
; GFX11TRUE16-NEXT: v_min_u32_e32 v4, v6, v4
; GFX11TRUE16-NEXT: v_min_u32_e32 v5, v7, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v2, 32, v4
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v2i64_to_v2bf16:
@@ -36646,71 +36970,70 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX11TRUE16-LABEL: v_sitofp_v3i64_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v6, v2, v3
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v9, v0, v1
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v3
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v7, v4, v5
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v11, v1
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v6, 31, v6
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v7, v0, v1
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v8, v4, v5
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v9, v2, v3
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v1
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v6, v5
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v11, v3
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v9
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, -1, v10
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v8, v5
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v7
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, 32, v6
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v7, 32, v7
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v7, 32, v7
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, v10, v6
+; GFX11TRUE16-NEXT: v_min_u32_e32 v7, v10, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v9, v11, v9
-; GFX11TRUE16-NEXT: v_min_u32_e32 v7, v8, v7
+; GFX11TRUE16-NEXT: v_min_u32_e32 v6, v6, v8
+; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v11, v9
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v7, v[4:5]
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v3, 1, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v6
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v9
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v7
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v7
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v3i64_to_v3bf16:
@@ -37295,84 +37618,89 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) #0 {
; GFX11TRUE16-NEXT: v_xor_b32_e32 v8, v6, v7
; GFX11TRUE16-NEXT: v_cls_i32_e32 v9, v7
; GFX11TRUE16-NEXT: v_xor_b32_e32 v11, v4, v5
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v13, v2, v3
; GFX11TRUE16-NEXT: v_cls_i32_e32 v10, v5
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v13, v2, v3
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v12, v3
; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v11
-; GFX11TRUE16-NEXT: v_xor_b32_e32 v14, v0, v1
+; GFX11TRUE16-NEXT: v_xor_b32_e32 v15, v0, v1
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v14, v1
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, -1, v10
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v12
+; GFX11TRUE16-NEXT: v_cls_i32_e32 v12, v3
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v11, 32, v11
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v13
-; GFX11TRUE16-NEXT: v_cls_i32_e32 v13, v1
-; GFX11TRUE16-NEXT: v_min_u32_e32 v10, v10, v11
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v14, 32, v14
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v10
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v10, 31, v13
+; GFX11TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v15
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v8, v[6:7]
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v13, -1, v13
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v9, v12, v9
-; GFX11TRUE16-NEXT: v_min_u32_e32 v11, v13, v14
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v9, v9, v11
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, 32, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v13, 32, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v9, v[4:5]
+; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v7, 32, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v8, 32, v10
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v9
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v6, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v14, -1, v14
+; GFX11TRUE16-NEXT: v_min_u32_e32 v11, v14, v13
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_ldexp_f32 v3, v6, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v4
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v6, 32, v11
-; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v6, v7
; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v7, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v12
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v10, v12, v10
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v11
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v9, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v5.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_sitofp_v4i64_to_v4bf16:
@@ -37596,7 +37924,7 @@ define bfloat @v_uitofp_i16_to_bf16(i16 %x) #0 {
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_i16_to_bf16:
@@ -37731,8 +38059,8 @@ define <2 x bfloat> @v_uitofp_v2i16_to_v2bf16(<2 x i16> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v2i16_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
@@ -37748,11 +38076,8 @@ define <2 x bfloat> @v_uitofp_v2i16_to_v2bf16(<2 x i16> %x) #0 {
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v2i16_to_v2bf16:
@@ -37919,38 +38244,34 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v3i16_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i16_to_v3bf16:
@@ -38176,47 +38497,39 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v3, v8, v9 :: v_dual_and_b32 v0, 0xffff, v0
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v4i16_to_v4bf16:
@@ -38342,19 +38655,33 @@ define bfloat @v_uitofp_i32_to_bf16(i32 %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_uitofp_i32_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_uitofp_i32_to_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_uitofp_i32_to_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_uitofp_i32_to_bf16:
; GFX1250: ; %bb.0:
@@ -38457,25 +38784,22 @@ define <2 x bfloat> @v_uitofp_v2i32_to_v2bf16(<2 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v2i32_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v2i32_to_v2bf16:
@@ -38630,32 +38954,29 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v3i32_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i32_to_v3bf16:
@@ -38857,39 +39178,33 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v4i32_to_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v4, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v4, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v4i32_to_v4bf16:
@@ -39044,29 +39359,53 @@ define bfloat @v_uitofp_i64_to_bf16(i64 %x) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_uitofp_i64_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_clz_i32_u32_e32 v2, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_min_u32_e32 v2, 32, v2
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_uitofp_i64_to_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v2, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 32, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_uitofp_i64_to_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_clz_i32_u32_e32 v2, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_min_u32_e32 v2, 32, v2
+; GFX11FAKE16-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11FAKE16-NEXT: v_sub_nc_u32_e32 v1, 32, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11FAKE16-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_uitofp_i64_to_bf16:
; GFX1250: ; %bb.0:
@@ -39262,45 +39601,42 @@ define <2 x bfloat> @v_uitofp_v2i64_to_v2bf16(<2 x i64> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v2i64_to_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v4, v3
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v5, v1
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v4, v1
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v5, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 32, v4
; GFX11TRUE16-NEXT: v_min_u32_e32 v5, 32, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v5, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v2, 32, v4
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v2i64_to_v2bf16:
@@ -39621,61 +39957,57 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v3i64_to_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v6, v3
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v7, v1
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v5
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v6, v1
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v7, v5
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 32, v6
; GFX11TRUE16-NEXT: v_min_u32_e32 v7, 32, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v7, v[4:5]
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11TRUE16-NEXT: v_min_u32_e32 v3, 1, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v1, 32, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, v5, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v6
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v7
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, v5, v3
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v3, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v3i64_to_v3bf16:
@@ -40128,75 +40460,68 @@ define <4 x bfloat> @v_uitofp_v4i64_to_v4bf16(<4 x i64> %x) #0 {
; GFX11TRUE16-LABEL: v_uitofp_v4i64_to_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v7
; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v9, v5
; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v10, v3
; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v11, v1
+; GFX11TRUE16-NEXT: v_clz_i32_u32_e32 v8, v7
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_min_u32_e32 v8, 32, v8
; GFX11TRUE16-NEXT: v_min_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_u32_e32 v10, 32, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_min_u32_e32 v11, 32, v11
+; GFX11TRUE16-NEXT: v_min_u32_e32 v8, 32, v8
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v8, v[6:7]
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[4:5], v9, v[4:5]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_lshlrev_b64 v[0:1], v11, v[0:1]
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8
+; GFX11TRUE16-NEXT: v_lshlrev_b64 v[6:7], v8, v[6:7]
; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v9, 32, v9
-; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8
; GFX11TRUE16-NEXT: v_min_u32_e32 v4, 1, v4
; GFX11TRUE16-NEXT: v_min_u32_e32 v2, 1, v2
; GFX11TRUE16-NEXT: v_min_u32_e32 v0, 1, v0
+; GFX11TRUE16-NEXT: v_min_u32_e32 v6, 1, v6
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11TRUE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v7, 32, v10
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v6
-; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v3, 32, v11
-; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v4, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v10
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v4
+; GFX11TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v11
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v8
+; GFX11TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v6
+; GFX11TRUE16-NEXT: v_ldexp_f32 v3, v3, v9
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v4, v4, v9
-; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v7
+; GFX11TRUE16-NEXT: v_ldexp_f32 v2, v2, v5
+; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
+; GFX11TRUE16-NEXT: v_ldexp_f32 v1, v1, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v9, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v8.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_uitofp_v4i64_to_v4bf16:
@@ -40771,13 +41096,11 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -40802,12 +41125,11 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v1, 16, v2 :: v_dual_lshrrev_b32 v4, 16, v3
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v1.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -42524,21 +42846,19 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX11TRUE16-LABEL: v_vselect_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX11TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l
+; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
+; GFX11TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; GFX11TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v1.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v7
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.h
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v5.h, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v1.l, s0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.h, s0
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v4.l, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v5.l, s2
@@ -42572,20 +42892,19 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX1250TRUE16: ; %bb.0:
; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l
+; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
+; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v3, 16, v4 :: v_dual_lshrrev_b32 v8, 16, v6
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v1.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v1, 16, v5 :: v_dual_lshrrev_b32 v2, 16, v7
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.h
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v3.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v5.h, vcc_lo
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v1.l, s0
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.h, s0
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v4.l, s1
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v5.l, s2
@@ -42859,35 +43178,27 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX11TRUE16-NEXT: v_and_b16 v1.l, 1, v5.l
-; GFX11TRUE16-NEXT: v_and_b16 v1.h, 1, v7.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v9
+; GFX11TRUE16-NEXT: v_and_b16 v1.l, 1, v2.l
+; GFX11TRUE16-NEXT: v_and_b16 v1.h, 1, v4.l
+; GFX11TRUE16-NEXT: v_and_b16 v2.l, 1, v6.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v2.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v4.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v1.l
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l
+; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v7.l
+; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v5.l
+; GFX11TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v1.h
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
-; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.h
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v11
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v15
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v10
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v2.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.l
-; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v6.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v12
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v0.l
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v2.l, v1.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v4.l, v3.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v5.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v16.l, v7.l, s0
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v1.l
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v8.h, s0
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v12.l, v8.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v15.h, v11.h, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v14.h, v10.h, s3
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v9.h, s4
; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v13.l, v9.l, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s3
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s5
; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v15.l, v11.l, s6
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -42939,33 +43250,27 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo
; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
-; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v5.l
-; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v7.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v5, 16, v9 :: v_dual_lshrrev_b32 v7, 16, v8
+; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v2.l
+; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v4.l
+; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v6.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v2.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v4.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v1.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l
+; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v7.l
+; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v5.l
+; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v1.h
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
-; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.h
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v1, 16, v11 :: v_dual_lshrrev_b32 v3, 16, v10
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v2, 16, v15 :: v_dual_lshrrev_b32 v4, 16, v14
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v2.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.l
-; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v6.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v6, 16, v13 :: v_dual_lshrrev_b32 v16, 16, v12
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v2.l, v1.l, s5
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v4.l, v3.l, s4
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v0.l
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v5.l, s2
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v16.l, v7.l, s0
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v1.l
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v8.h, s0
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v12.l, v8.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v15.h, v11.h, s2
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v14.h, v10.h, s3
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v9.h, s4
; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v13.l, v9.l, s1
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s3
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s5
; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v15.l, v11.l, s6
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -43493,21 +43798,6 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11TRUE16-NEXT: v_and_b16 v6.h, 1, v13.l
; GFX11TRUE16-NEXT: v_and_b16 v7.l, 1, v14.l
; GFX11TRUE16-NEXT: v_and_b16 v7.h, 1, v15.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v30
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v29
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v20
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v28
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v27
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v26
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v25
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v24
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l
@@ -43524,25 +43814,23 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v5.h
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v7.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v7.h
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v34.l, v33.l, s10
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v30.h, v22.h, s10
; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v30.l, v22.l, s11
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v36.l, v35.l, s12
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v29.h, v21.h, s12
; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v29.l, v21.l, s9
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v38.l, v37.l, s8
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v28.h, v20.h, s8
; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v28.l, v20.l, s7
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v48.l, v39.l, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v27.h, v19.h, s6
; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v27.l, v19.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v50.l, v49.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v52.l, v51.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v54.l, v53.l, s0
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v26.h, v18.h, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v25.h, v17.h, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v24.h, v16.h, s0
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v24.l, v16.l, vcc_lo
; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v25.l, v17.l, s1
; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v26.l, v18.l, s3
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v31
+; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v31.h, v23.h, s14
; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v31.l, v23.l, s13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v32.l, s14
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v16bf16:
@@ -43646,14 +43934,6 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX1250TRUE16-NEXT: v_and_b16 v6.h, 1, v13.l
; GFX1250TRUE16-NEXT: v_and_b16 v7.l, 1, v14.l
; GFX1250TRUE16-NEXT: v_and_b16 v7.h, 1, v15.l
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v32, 16, v23 :: v_dual_lshrrev_b32 v33, 16, v22
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v34, 16, v30 :: v_dual_lshrrev_b32 v35, 16, v21
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v36, 16, v29 :: v_dual_lshrrev_b32 v37, 16, v20
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v38, 16, v28 :: v_dual_lshrrev_b32 v39, 16, v19
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v48, 16, v27 :: v_dual_lshrrev_b32 v49, 16, v18
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v50, 16, v26 :: v_dual_lshrrev_b32 v51, 16, v17
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v52, 16, v25 :: v_dual_lshrrev_b32 v53, 16, v16
-; GFX1250TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v24
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l
@@ -43670,25 +43950,23 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v5.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v7.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v7.h
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v34.l, v33.l, s10
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v30.h, v22.h, s10
; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.l, v30.l, v22.l, s11
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v36.l, v35.l, s12
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v29.h, v21.h, s12
; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.l, v29.l, v21.l, s9
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v38.l, v37.l, s8
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v28.h, v20.h, s8
; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.l, v28.l, v20.l, s7
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v48.l, v39.l, s6
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v27.h, v19.h, s6
; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v27.l, v19.l, s5
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v50.l, v49.l, s4
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v52.l, v51.l, s2
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v26.h, v18.h, s4
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v25.h, v17.h, s2
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v24.h, v16.h, s0
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v24.l, v16.l, vcc_lo
; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v25.l, v17.l, s1
; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v26.l, v18.l, s3
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v31
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v54.l, v53.l, s0
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v31.h, v23.h, s14
; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.l, v31.l, v23.l, s13
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v32.l, s14
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250FAKE16-LABEL: v_vselect_v16bf16:
@@ -45078,30 +45356,22 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: v_and_b16 v7.l, 1, v14.l
; GFX11TRUE16-NEXT: v_and_b16 v7.h, 1, v15.l
; GFX11TRUE16-NEXT: v_and_b16 v8.l, 1, v16.l
-; GFX11TRUE16-NEXT: v_and_b16 v9.l, 1, v18.l
-; GFX11TRUE16-NEXT: v_and_b16 v10.l, 1, v20.l
-; GFX11TRUE16-NEXT: v_and_b16 v11.l, 1, v22.l
-; GFX11TRUE16-NEXT: v_and_b16 v12.l, 1, v24.l
-; GFX11TRUE16-NEXT: v_and_b16 v13.l, 1, v26.l
-; GFX11TRUE16-NEXT: v_and_b16 v14.l, 1, v28.l
-; GFX11TRUE16-NEXT: v_and_b16 v15.l, 1, v30.l
; GFX11TRUE16-NEXT: v_and_b16 v8.h, 1, v17.l
+; GFX11TRUE16-NEXT: v_and_b16 v9.l, 1, v18.l
; GFX11TRUE16-NEXT: v_and_b16 v9.h, 1, v19.l
+; GFX11TRUE16-NEXT: v_and_b16 v10.l, 1, v20.l
; GFX11TRUE16-NEXT: v_and_b16 v10.h, 1, v21.l
+; GFX11TRUE16-NEXT: v_and_b16 v11.l, 1, v22.l
; GFX11TRUE16-NEXT: v_and_b16 v11.h, 1, v23.l
+; GFX11TRUE16-NEXT: v_and_b16 v12.l, 1, v24.l
; GFX11TRUE16-NEXT: v_and_b16 v12.h, 1, v25.l
+; GFX11TRUE16-NEXT: v_and_b16 v13.l, 1, v26.l
; GFX11TRUE16-NEXT: v_and_b16 v13.h, 1, v27.l
+; GFX11TRUE16-NEXT: v_and_b16 v14.l, 1, v28.l
; GFX11TRUE16-NEXT: v_and_b16 v14.h, 1, v29.l
+; GFX11TRUE16-NEXT: v_and_b16 v15.l, 1, v30.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 1, v8.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 1, v9.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 1, v10.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 1, v11.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 1, v12.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 1, v13.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 1, v14.l
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 1, v15.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v2.l
@@ -45116,112 +45386,73 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v6.h
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v7.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v7.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 1, v8.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 1, v8.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 1, v9.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 1, v9.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 1, v10.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 1, v10.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 1, v11.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 1, v11.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 1, v12.l
; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 1, v12.h
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 1, v13.h
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 1, v14.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 1, v13.l
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 1, v15.l
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 1, v14.h
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 1, v14.l
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 1, v13.h
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(32)
-; GFX11TRUE16-NEXT: v_and_b16 v0.h, 1, v31.l
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(31)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v32
+; GFX11TRUE16-NEXT: v_and_b16 v0.l, 1, v31.l
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(30)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v33
-; GFX11TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v32.l, s28
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(29)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v34
+; GFX11TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v32.l, s26
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(28)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v35
-; GFX11TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v34.l, s27
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(27)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v36
+; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v35.h, v34.h, s27
+; GFX11TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v34.l, s28
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(26)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v37
+; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v37.h, v36.h, s29
; GFX11TRUE16-NEXT: v_cndmask_b16 v13.l, v37.l, v36.l, s25
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(25)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v38
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(24)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v39
+; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v39.h, v38.h, s24
; GFX11TRUE16-NEXT: v_cndmask_b16 v12.l, v39.l, v38.l, s23
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(23)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v48
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(22)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v49
+; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v49.h, v48.h, s22
; GFX11TRUE16-NEXT: v_cndmask_b16 v11.l, v49.l, v48.l, s21
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(21)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v50
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(20)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v51
+; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v51.h, v50.h, s20
; GFX11TRUE16-NEXT: v_cndmask_b16 v10.l, v51.l, v50.l, s19
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(19)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v52
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(18)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v53
+; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v53.h, v52.h, s18
; GFX11TRUE16-NEXT: v_cndmask_b16 v9.l, v53.l, v52.l, s17
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(17)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v54
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(16)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v55
+; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v55.h, v54.h, s16
; GFX11TRUE16-NEXT: v_cndmask_b16 v8.l, v55.l, v54.l, s15
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(15)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v64
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(14)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v65
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(13)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v66
+; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v65.h, v64.h, s14
+; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v65.l, v64.l, s13
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(12)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v67
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v68
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v67.h, v66.h, s12
+; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(10)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v69
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(9)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v70
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v69.h, v68.h, s10
+; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(8)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v71
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(7)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v80
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v71.h, v70.h, s8
+; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(6)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v81
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(5)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v82
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v81.h, v80.h, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v83
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v84
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v83.h, v82.h, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v85
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v86
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v85.h, v84.h, s2
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s1
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v87
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v87.h, v86.h, s0
+; GFX11TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, v87.l, v86.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.l, v65.l, v64.l, s13
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s1
-; GFX11TRUE16-NEXT: v_cndmask_b16 v14.h, v19.l, v18.l, s29
-; GFX11TRUE16-NEXT: v_cndmask_b16 v13.h, v21.l, v20.l, s26
-; GFX11TRUE16-NEXT: v_cndmask_b16 v12.h, v23.l, v22.l, s24
-; GFX11TRUE16-NEXT: v_cndmask_b16 v11.h, v25.l, v24.l, s22
-; GFX11TRUE16-NEXT: v_cndmask_b16 v10.h, v27.l, v26.l, s20
-; GFX11TRUE16-NEXT: v_cndmask_b16 v9.h, v29.l, v28.l, s18
-; GFX11TRUE16-NEXT: v_cndmask_b16 v8.h, v31.l, v30.l, s16
-; GFX11TRUE16-NEXT: v_cndmask_b16 v7.h, v33.l, v32.l, s14
-; GFX11TRUE16-NEXT: v_cndmask_b16 v6.h, v35.l, v34.l, s12
-; GFX11TRUE16-NEXT: v_cndmask_b16 v5.h, v37.l, v36.l, s10
-; GFX11TRUE16-NEXT: v_cndmask_b16 v4.h, v39.l, v38.l, s8
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, v55.l, v54.l, s0
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, v53.l, v52.l, s2
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v50.l, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v3.h, v49.l, v48.l, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v17.l, v16.l, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v15.h, v33.h, v32.h, s0
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_vselect_v32bf16:
@@ -45463,49 +45694,41 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX1250TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:68
; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
+; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v2.l
+; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v3.l
+; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v8.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v4.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v1.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h
+; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v5.l
; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v6.l
; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v7.l
; GFX1250TRUE16-NEXT: v_and_b16 v2.h, 1, v9.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v2.l
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
-; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v8.l
; GFX1250TRUE16-NEXT: v_and_b16 v3.l, 1, v10.l
; GFX1250TRUE16-NEXT: v_and_b16 v3.h, 1, v11.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.h
-; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v4.l
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v5.l
; GFX1250TRUE16-NEXT: v_and_b16 v4.l, 1, v12.l
; GFX1250TRUE16-NEXT: v_and_b16 v4.h, 1, v13.l
-; GFX1250TRUE16-NEXT: v_and_b16 v6.l, 1, v16.l
-; GFX1250TRUE16-NEXT: v_and_b16 v7.l, 1, v18.l
-; GFX1250TRUE16-NEXT: v_and_b16 v8.l, 1, v20.l
-; GFX1250TRUE16-NEXT: v_and_b16 v9.l, 1, v22.l
-; GFX1250TRUE16-NEXT: v_and_b16 v10.l, 1, v24.l
-; GFX1250TRUE16-NEXT: v_and_b16 v11.l, 1, v26.l
-; GFX1250TRUE16-NEXT: v_and_b16 v12.l, 1, v28.l
-; GFX1250TRUE16-NEXT: v_and_b16 v13.l, 1, v30.l
; GFX1250TRUE16-NEXT: v_and_b16 v5.l, 1, v14.l
; GFX1250TRUE16-NEXT: v_and_b16 v5.h, 1, v15.l
+; GFX1250TRUE16-NEXT: v_and_b16 v6.l, 1, v16.l
; GFX1250TRUE16-NEXT: v_and_b16 v6.h, 1, v17.l
+; GFX1250TRUE16-NEXT: v_and_b16 v7.l, 1, v18.l
; GFX1250TRUE16-NEXT: v_and_b16 v7.h, 1, v19.l
+; GFX1250TRUE16-NEXT: v_and_b16 v8.l, 1, v20.l
; GFX1250TRUE16-NEXT: v_and_b16 v8.h, 1, v21.l
+; GFX1250TRUE16-NEXT: v_and_b16 v9.l, 1, v22.l
; GFX1250TRUE16-NEXT: v_and_b16 v9.h, 1, v23.l
+; GFX1250TRUE16-NEXT: v_and_b16 v10.l, 1, v24.l
; GFX1250TRUE16-NEXT: v_and_b16 v10.h, 1, v25.l
+; GFX1250TRUE16-NEXT: v_and_b16 v11.l, 1, v26.l
; GFX1250TRUE16-NEXT: v_and_b16 v11.h, 1, v27.l
+; GFX1250TRUE16-NEXT: v_and_b16 v12.l, 1, v28.l
; GFX1250TRUE16-NEXT: v_and_b16 v12.h, 1, v29.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v0.h
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 1, v6.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 1, v7.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 1, v8.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 1, v9.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 1, v10.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 1, v11.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 1, v13.l
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 1, v12.l
+; GFX1250TRUE16-NEXT: v_and_b16 v13.l, 1, v30.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v0.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v1.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v1.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 1, v2.l
@@ -45516,80 +45739,73 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v4.h
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v5.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v5.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 1, v6.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 1, v6.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 1, v7.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 1, v7.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 1, v8.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 1, v8.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 1, v9.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 1, v9.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 1, v10.l
; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 1, v10.h
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 1, v11.h
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 1, v12.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 1, v11.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 1, v13.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 1, v12.h
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 1, v12.l
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 1, v11.h
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x20
-; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v31.l
+; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v31.l
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x1e
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v16, 16, v32 :: v_dual_lshrrev_b32 v17, 16, v33
; GFX1250TRUE16-NEXT: v_cndmask_b16 v15.l, v33.l, v32.l, s26
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x1c
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v18, 16, v34 :: v_dual_lshrrev_b32 v19, 16, v35
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v14.h, v35.h, v34.h, s27
; GFX1250TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v34.l, s28
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x1a
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v20, 16, v36 :: v_dual_lshrrev_b32 v21, 16, v37
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v13.h, v37.h, v36.h, s29
; GFX1250TRUE16-NEXT: v_cndmask_b16 v13.l, v37.l, v36.l, s25
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x18
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v22, 16, v38 :: v_dual_lshrrev_b32 v23, 16, v39
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v12.h, v39.h, v38.h, s24
; GFX1250TRUE16-NEXT: v_cndmask_b16 v12.l, v39.l, v38.l, s23
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x16
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v24, 16, v48 :: v_dual_lshrrev_b32 v25, 16, v49
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v11.h, v49.h, v48.h, s22
; GFX1250TRUE16-NEXT: v_cndmask_b16 v11.l, v49.l, v48.l, s21
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x14
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v26, 16, v50 :: v_dual_lshrrev_b32 v27, 16, v51
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v10.h, v51.h, v50.h, s20
; GFX1250TRUE16-NEXT: v_cndmask_b16 v10.l, v51.l, v50.l, s19
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x12
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v28, 16, v52 :: v_dual_lshrrev_b32 v29, 16, v53
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v9.h, v53.h, v52.h, s18
; GFX1250TRUE16-NEXT: v_cndmask_b16 v9.l, v53.l, v52.l, s17
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x10
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v30, 16, v54 :: v_dual_lshrrev_b32 v31, 16, v55
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v8.h, v55.h, v54.h, s16
; GFX1250TRUE16-NEXT: v_cndmask_b16 v8.l, v55.l, v54.l, s15
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xe
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v32, 16, v64 :: v_dual_lshrrev_b32 v33, 16, v65
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v65.h, v64.h, s14
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.l, v65.l, v64.l, s13
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xc
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v34, 16, v66 :: v_dual_lshrrev_b32 v35, 16, v67
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v67.h, v66.h, s12
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xa
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v36, 16, v68 :: v_dual_lshrrev_b32 v37, 16, v69
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v69.h, v68.h, s10
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x8
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v38, 16, v70 :: v_dual_lshrrev_b32 v39, 16, v71
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v71.h, v70.h, s8
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x6
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v48, 16, v80 :: v_dual_lshrrev_b32 v49, 16, v81
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v81.h, v80.h, s6
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x4
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v50, 16, v82 :: v_dual_lshrrev_b32 v51, 16, v83
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v83.h, v82.h, s4
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x2
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v52, 16, v84 :: v_dual_lshrrev_b32 v53, 16, v85
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v85.h, v84.h, s2
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s0
; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1250TRUE16-NEXT: v_dual_lshrrev_b32 v54, 16, v86 :: v_dual_lshrrev_b32 v55, 16, v87
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v87.h, v86.h, s1
+; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v87.l, v86.l, vcc_lo
-; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.l, v65.l, v64.l, s13
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.l, v67.l, v66.l, s11
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.l, v69.l, v68.l, s9
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.l, v71.l, v70.l, s7
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v81.l, v80.l, s5
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v83.l, v82.l, s3
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v85.l, v84.l, s1
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v14.h, v19.l, v18.l, s29
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v13.h, v21.l, v20.l, s27
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v12.h, v23.l, v22.l, s24
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v11.h, v25.l, v24.l, s22
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v10.h, v27.l, v26.l, s20
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v9.h, v29.l, v28.l, s18
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v8.h, v31.l, v30.l, s16
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v33.l, v32.l, s14
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v35.l, v34.l, s12
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v37.l, v36.l, s10
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v39.l, v38.l, s8
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v55.l, v54.l, s0
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v53.l, v52.l, s2
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v50.l, s4
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v49.l, v48.l, s6
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v15.h, v17.l, v16.l, vcc_lo
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v15.h, v33.h, v32.h, s1
; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250FAKE16-LABEL: v_vselect_v32bf16:
@@ -45858,23 +46074,41 @@ define bfloat @v_fma_bf16(bfloat %a, bfloat %b, bfloat %c) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fma_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v2, v0, v1
-; GFX11-NEXT: v_bfe_u32 v0, v2, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v1, 0x400000, v2
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fma_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v2, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fma_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v2, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fma_bf16:
; GFX1250: ; %bb.0:
@@ -46011,12 +46245,12 @@ define <2 x bfloat> @v_fma_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v2, v0, v1 :: v_dual_fmac_f32 v3, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
@@ -46027,14 +46261,12 @@ define <2 x bfloat> @v_fma_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat>
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v2bf16:
@@ -46246,43 +46478,40 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v6, v8, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, 0x400000, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v7, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v0, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v3bf16:
@@ -46550,52 +46779,48 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_and_b32 v7, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v9, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v10, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v9, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v7, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v9, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v7, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v0, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v4bf16:
@@ -47050,93 +47275,92 @@ define <8 x bfloat> @v_fma_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b, <8 x bfloat>
; GFX11TRUE16-LABEL: v_fma_v8bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v6
+; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v11, v3, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v3, v15, v7 :: v_dual_lshlrev_b32 v6, 16, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v2, v6
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v12, v14, v13
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v11
; GFX11TRUE16-NEXT: v_bfe_u32 v13, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_add3_u32 v13, v13, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc_lo
-; GFX11TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v3, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v13, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v10
+; GFX11TRUE16-NEXT: v_bfe_u32 v10, v11, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v7, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v11
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v14, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v5
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v14, v16, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v10, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v9
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v12.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v11, v7, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
+; GFX11TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v2, v6, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v15, v14, 0x7fff
+; GFX11TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v14
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.h
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v1, v5
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v7, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v13, v15, v14 :: v_dual_and_b32 v14, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v9, v1, v5 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v13, 16, 1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v13
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v10, v14, v11
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v7, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v8, v0, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v9, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v10, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v8, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v4, v10, v11 :: v_dual_and_b32 v5, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v7.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v15, v17, v16
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v12, v15, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v13, v16, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v0, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v15, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v13, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v5, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v13, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v11, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v0, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v11.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v8bf16:
@@ -47996,166 +48220,153 @@ define <16 x bfloat> @v_fma_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, <16 x bf
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v15
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v24, v26, v25 :: v_dual_lshlrev_b32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v22
-; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v26, v28, v27 :: v_dual_and_b32 v27, 0xffff0000, v5
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v22, v6, v14 :: v_dual_lshlrev_b32 v15, 16, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v26, v28, v27
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v22, v6, v14
+; GFX11TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v13
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_add3_u32 v25, v25, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v24
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v23, v7, v15
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v25, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v25, v23, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v23
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v25, v29, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v15, v23, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v24, v26, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v25, v23, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v13
-; GFX11TRUE16-NEXT: v_bfe_u32 v23, v26, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_and_b32 v24, 0xffff0000, v21
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v23, v26, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v26
+; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v23, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v24, v24, v26, 0x7fff
; GFX11TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v14, v29, v28 :: v_dual_cndmask_b32 v15, v15, v25
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v26
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v27, v25
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v14.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v15, vcc_lo
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v23, v22, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v21, v5, v13
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v20
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v6, v15, v23 :: v_dual_and_b32 v13, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_bfe_u32 v15, v24, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v24
-; GFX11TRUE16-NEXT: v_bfe_u32 v26, v21, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v15, v24, 0x7fff
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v22, v13
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v12
+; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v4
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v13, v15, v23 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v15, v26, v21, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v23, v5, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
-; GFX11TRUE16-NEXT: v_add3_u32 v21, v23, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v24, v27, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v20
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v15
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_fmac_f32 v20, v4, v12
+; GFX11TRUE16-NEXT: v_add3_u32 v23, v23, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v22
+; GFX11TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v20, v4, v12
; GFX11TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v19
; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v15.h
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v21, v5, v13
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v23, v27, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v28, v14, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v21, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v27, v20, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
+; GFX11TRUE16-NEXT: v_add3_u32 v14, v23, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11TRUE16-NEXT: v_add3_u32 v23, v25, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v21, v27, v20, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v14, v22, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v20
+; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v18
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v14.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v12, v25, v4
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v23, v26, vcc_lo
+; GFX11TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
+; GFX11TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v22, v20, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v20
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v12, v23, v4 :: v_dual_lshlrev_b32 v11, 16, v11
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v12, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v22, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v13.l
-; GFX11TRUE16-NEXT: v_bfe_u32 v22, v12, 16, 1
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v19, v3, v11
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v4, v4, v21 :: v_dual_and_b32 v3, 0xffff0000, v18
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v12
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v22, v12, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v24, v26, v25
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v3, v22, v11 :: v_dual_cndmask_b32 v12, v20, v21
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v19, 16, 1
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v20, v21, v22 :: v_dual_and_b32 v25, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v21, v23, v12, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v24, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v23, v24, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v19, v3, v11
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v3, v21, v22 :: v_dual_and_b32 v22, 0xffff0000, v17
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v18
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v19, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v22, v25, v23 :: v_dual_fmac_f32 v11, v2, v10
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v19
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v18, v19, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v24
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v8
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v11, 16, 1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v21, v3, 16, 1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v20, v19, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v11, v2, v10
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v21, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v2, v18, v20 :: v_dual_lshlrev_b32 v9, 16, v9
-; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v19, v11, 16, 1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v10, v10, v18 :: v_dual_lshlrev_b32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v19, v11, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v11
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v17, v1, v9 :: v_dual_cndmask_b32 v10, v2, v10
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v16
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v21, v11, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v11
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v20, v22, v21 :: v_dual_and_b32 v21, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v17, v1, v9 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v18, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v16
-; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v20, 16, 1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v20
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v18, v21, v19
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v11, v20, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v16, v0, v8
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v17, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v18, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v18
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11TRUE16-NEXT: v_bfe_u32 v9, v16, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v18, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v17, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
-; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v16, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v17, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v21, v24, v23
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v9, v0, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v12, v18, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v11, v11, v17, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v21, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v19, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v10.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v12.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v20, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v11.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v15.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v8.l
+; GFX11TRUE16-NEXT: v_add3_u32 v12, v19, v22, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v18, v9, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v21, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v22
+; GFX11TRUE16-NEXT: v_add3_u32 v16, v18, v9, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v9
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v8.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v0, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v11.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v18.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v16bf16:
@@ -50061,8 +50272,6 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: v_and_b32_e32 v103, 0xffff0000, v19
; GFX11TRUE16-NEXT: v_and_b32_e32 v112, 0xffff0000, v3
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
@@ -50072,16 +50281,17 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v2
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(16)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v119, 0xffff0000, v31
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(15)
; GFX11TRUE16-NEXT: v_and_b32_e32 v128, 0xffff0000, v32
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(14)
; GFX11TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v33
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX11TRUE16-NEXT: v_and_b32_e32 v68, 0xffff0000, v13
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(11)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v36
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(12)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v35
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(10)
; GFX11TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v37
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(9)
@@ -50092,13 +50302,13 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v50
+; GFX11TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v49
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(4)
; GFX11TRUE16-NEXT: v_and_b32_e32 v147, 0xffff0000, v51
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX11TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v7
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v49
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11TRUE16-NEXT: v_and_b32_e32 v148, 0xffff0000, v55
; GFX11TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
@@ -50108,273 +50318,250 @@ define <32 x bfloat> @v_fma_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b, <32 x bf
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; GFX11TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v51, v4, v20 :: v_dual_and_b32 v84, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_and_b32_e32 v84, 0xffff0000, v9
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v48, v7, v23
; GFX11TRUE16-NEXT: v_and_b32_e32 v135, 0xffff0000, v39
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v48, v7, v23 :: v_dual_fmac_f32 v49, v6, v22
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v49, v6, v22
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v134, v84, v83 :: v_dual_lshlrev_b32 v13, 16, v13
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v148, v118, v117 :: v_dual_and_b32 v81, 0xffff0000, v26
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v144, v96, v87
+; GFX11TRUE16-NEXT: v_bfe_u32 v83, v146, 16, 1
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v51, v4, v20 :: v_dual_fmac_f32 v148, v118, v117
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v144, v96, v87 :: v_dual_and_b32 v81, 0xffff0000, v26
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v55, v0, v16 :: v_dual_lshlrev_b32 v26, 16, v26
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v145, v98, v97
-; GFX11TRUE16-NEXT: v_or_b32_e32 v83, 0x400000, v146
+; GFX11TRUE16-NEXT: v_or_b32_e32 v84, 0x400000, v146
+; GFX11TRUE16-NEXT: v_add3_u32 v83, v83, v146, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v8
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v10
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v147, v102, v101 :: v_dual_lshlrev_b32 v10, 16, v10
-; GFX11TRUE16-NEXT: v_bfe_u32 v96, v51, 16, 1
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v50, v5, v21 :: v_dual_and_b32 v71, 0xffff0000, v27
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX11TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v28
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v37, v10, v26 :: v_dual_lshlrev_b32 v28, 16, v28
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v135, v86, v85
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v39, v8, v24
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v133, v82, v81 :: v_dual_and_b32 v70, 0xffff0000, v12
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11TRUE16-NEXT: v_or_b32_e32 v97, 0x400000, v51
-; GFX11TRUE16-NEXT: v_add3_u32 v96, v96, v51, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v131, 0xffff0000, v35
+; GFX11TRUE16-NEXT: v_bfe_u32 v97, v51, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v23, v37, 16, 1
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v135, v86, v85 :: v_dual_lshlrev_b32 v12, 16, v12
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX11TRUE16-NEXT: v_and_b32_e32 v80, 0xffff0000, v11
+; GFX11TRUE16-NEXT: v_and_b32_e32 v132, 0xffff0000, v36
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
+; GFX11TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v133
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v37
+; GFX11TRUE16-NEXT: v_or_b32_e32 v98, 0x400000, v51
+; GFX11TRUE16-NEXT: v_add3_u32 v23, v23, v37, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v27
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11TRUE16-NEXT: v_add3_u32 v97, v97, v51, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v35, v12, v28
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v132, v80, v71 :: v_dual_and_b32 v67, 0xffff0000, v29
-; GFX11TRUE16-NEXT: v_bfe_u32 v80, v49, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v84, v50, 16, 1
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v36, v11, v27 :: v_dual_lshlrev_b32 v29, 16, v29
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v34
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11TRUE16-NEXT: v_or_b32_e32 v81, 0x400000, v49
-; GFX11TRUE16-NEXT: v_or_b32_e32 v85, 0x400000, v50
-; GFX11TRUE16-NEXT: v_add3_u32 v80, v80, v49, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v119, 0xffff0000, v31
-; GFX11TRUE16-NEXT: v_add3_u32 v84, v84, v50, 0x7fff
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v15
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v34, v13, v29 :: v_dual_lshlrev_b32 v15, 16, v15
+; GFX11TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v34
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v35, v12, v28 :: v_dual_lshlrev_b32 v34, 16, v34
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v36, v11, v27
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v50, v5, v21
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v132, v80, v71 :: v_dual_and_b32 v67, 0xffff0000, v29
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v130, v68, v67 :: v_dual_and_b32 v65, 0xffff0000, v30
-; GFX11TRUE16-NEXT: v_bfe_u32 v16, v132, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v31, v15, v32 :: v_dual_and_b32 v66, 0xffff0000, v14
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v119, v64, v128
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v36
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v34, v13, v29 :: v_dual_fmac_f32 v31, v15, v32
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v119, v64, v128 :: v_dual_and_b32 v66, 0xffff0000, v14
; GFX11TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v52
; GFX11TRUE16-NEXT: v_and_b32_e32 v128, 0xffff0000, v53
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v54
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v119, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v129, v66, v65 :: v_dual_lshlrev_b32 v30, 16, v30
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
+; GFX11TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v54
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v64, v112, v103
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v38, v9, v25
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v131, v70, v69 :: v_dual_lshlrev_b32 v14, 16, v14
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v53, v2, v18 :: v_dual_fmac_f32 v54, v1, v17
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v119
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v53, v2, v18
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v119, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v2, v31, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v33, v14, v30 :: v_dual_fmac_f32 v52, v3, v19
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v54, v1, v17
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v119
; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v31
; GFX11TRUE16-NEXT: v_bfe_u32 v4, v129, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v119, 0x7fff
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v119, v119
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v31, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e64 s0, v31, v31
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v129
; GFX11TRUE16-NEXT: v_bfe_u32 v6, v33, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v129, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v33
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v132, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v15, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v149, v2, v3, s0
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v4, v129, 0x7fff
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v129
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v33
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v130, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v6, v33, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v150, v14, v132, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v14, v2, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v130
; GFX11TRUE16-NEXT: v_bfe_u32 v10, v34, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v130, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v13, v35, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v8, v130, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v3, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v34
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v131, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v34, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v130
-; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v131
-; GFX11TRUE16-NEXT: v_bfe_u32 v14, v35, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v12, v12, v131, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v35
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v8, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v10, v34, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v13, v35, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v4, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11TRUE16-NEXT: v_add3_u32 v14, v14, v35, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v132
-; GFX11TRUE16-NEXT: v_bfe_u32 v18, v36, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v16, v16, v132, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v131
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v12, v131, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v35
+; GFX11TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v132
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v34, v6, v11, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v131, v131
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v36
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v133, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v18, v18, v36, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v133
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v12, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v36, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v21, v133, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v25, v134, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v134
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v12, v8, v16, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
-; GFX11TRUE16-NEXT: v_bfe_u32 v22, v37, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v20, v20, v133, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v37
-; GFX11TRUE16-NEXT: v_bfe_u32 v24, v134, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v14, v15, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v19, v19, v36, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v21, v21, v133, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v27, v38, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v25, v25, v134, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v10, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v132, v132
-; GFX11TRUE16-NEXT: v_add3_u32 v22, v22, v37, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v134
-; GFX11TRUE16-NEXT: v_bfe_u32 v26, v38, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v24, v24, v134, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v16, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v38
+; GFX11TRUE16-NEXT: v_bfe_u32 v29, v135, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v27, v27, v38, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v135
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v11, v150, v18, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36
-; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v38
-; GFX11TRUE16-NEXT: v_bfe_u32 v28, v135, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v26, v26, v38, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v135
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v18, v19, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v65, v39, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v29, v29, v135, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v66, 0x400000, v39
+; GFX11TRUE16-NEXT: v_bfe_u32 v67, v144, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v133
-; GFX11TRUE16-NEXT: v_bfe_u32 v30, v39, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v28, v28, v135, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v65, 0x400000, v39
-; GFX11TRUE16-NEXT: v_bfe_u32 v66, v144, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v20, v21, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v65, v65, v39, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v68, 0x400000, v144
+; GFX11TRUE16-NEXT: v_bfe_u32 v69, v48, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v67, v67, v144, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v21, v22, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
-; GFX11TRUE16-NEXT: v_add3_u32 v30, v30, v39, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v67, 0x400000, v144
-; GFX11TRUE16-NEXT: v_bfe_u32 v68, v48, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v66, v66, v144, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v16, v22, v23, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v70, 0x400000, v48
+; GFX11TRUE16-NEXT: v_bfe_u32 v71, v145, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v69, v69, v48, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v80, 0x400000, v145
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v23, v24, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v134
-; GFX11TRUE16-NEXT: v_or_b32_e32 v69, 0x400000, v48
-; GFX11TRUE16-NEXT: v_bfe_u32 v70, v145, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v68, v68, v48, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v71, 0x400000, v145
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v17, v24, v25, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v81, v49, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v71, v71, v145, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v82, 0x400000, v49
+; GFX11TRUE16-NEXT: v_bfe_u32 v85, v50, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v9, v25, v26, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38
-; GFX11TRUE16-NEXT: v_add3_u32 v70, v70, v145, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v82, v146, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v86, v147, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v87, 0x400000, v147
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v18, v26, v27, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v81, v81, v49, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v86, 0x400000, v50
+; GFX11TRUE16-NEXT: v_bfe_u32 v87, v147, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v85, v85, v50, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v27, v28, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v135, v135
-; GFX11TRUE16-NEXT: v_add3_u32 v82, v82, v146, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v86, v86, v147, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v98, v64, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v99, 0x400000, v64
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v19, v28, v29, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v96, 0x400000, v147
+; GFX11TRUE16-NEXT: v_add3_u32 v87, v87, v147, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v99, v64, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v100, 0x400000, v64
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v8, v29, v30, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11TRUE16-NEXT: v_bfe_u32 v100, v52, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v98, v98, v64, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v101, 0x400000, v52
-; GFX11TRUE16-NEXT: v_bfe_u32 v112, v53, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v30, v65, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v101, v52, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v99, v99, v64, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v102, 0x400000, v52
+; GFX11TRUE16-NEXT: v_bfe_u32 v117, v54, 16, 1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v20, v65, v66, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v144, v144
-; GFX11TRUE16-NEXT: v_add3_u32 v100, v100, v52, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v112, v112, v53, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v1, v148, 16, 1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v66, v67, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v101, v101, v52, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v118, 0x400000, v54
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v55, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v117, v117, v54, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v67, v68, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v0
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v68, v69, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v55
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v55, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v119, v148, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v148
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v21, v69, v70, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v145
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v54, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v148, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v70, v71, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.l, v20.h
+; GFX11TRUE16-NEXT: v_add3_u32 v119, v119, v148, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v19.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.l, v21.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v71, v80, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v128, v114, v113
-; GFX11TRUE16-NEXT: v_or_b32_e32 v113, 0x400000, v53
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v54, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v80, v81, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.l, v18.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.l, v17.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.l, v16.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.l, v34.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v22, v81, v82, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v146
-; GFX11TRUE16-NEXT: v_bfe_u32 v102, v128, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v103, 0x400000, v128
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v18
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v24
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v82, v83, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.l, v33.h
+; GFX11TRUE16-NEXT: v_mov_b16_e64 v15.l, v149.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v83, v84, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50
-; GFX11TRUE16-NEXT: v_add3_u32 v102, v102, v128, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v24, v55, 16, 1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v21
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v25
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v84, v85, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v23, v85, v86, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v147, v147
-; GFX11TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v148
-; GFX11TRUE16-NEXT: v_add3_u32 v24, v24, v55, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v26
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v86, v87, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v23.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v87, v96, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v54
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v27
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v96, v97, vcc_lo
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v128, v114, v113
+; GFX11TRUE16-NEXT: v_bfe_u32 v113, v53, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v114, 0x400000, v53
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v97, v98, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v64
-; GFX11TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v55
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v16
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v17
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v19
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v29, v98, v99, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v103, v128, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v112, 0x400000, v128
+; GFX11TRUE16-NEXT: v_add3_u32 v113, v113, v53, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v24.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v99, v100, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v32, v116, v115
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v22
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v23
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v29
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v30, v100, v101, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v103, v103, v128, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v25, v101, v102, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v128, v128
-; GFX11TRUE16-NEXT: v_bfe_u32 v114, v32, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v115, 0x400000, v32
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v28
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v31, v102, v103, vcc_lo
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v32, v116, v115
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v25.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v103, v112, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v53
-; GFX11TRUE16-NEXT: v_add3_u32 v114, v114, v32, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v30
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v22.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v31
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v33, v112, v113, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v20.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v19.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v18.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v114, v115, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v148, v148
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v17.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v16.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v39.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v25, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v115, v32, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v116, 0x400000, v32
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v26, v113, v114, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v54
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v14.h, v35.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v26, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v115, v115, v32, 0x7fff
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v26.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v27, v117, v118, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v55
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v33
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v23.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v24, v24, v27, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v26.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v24
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v25.l
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v28, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v115, v116, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v148, v148
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v27.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v119, v31, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v28.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fma_v32bf16:
@@ -50855,23 +51042,41 @@ define bfloat @v_fmuladd_bf16(bfloat %a, bfloat %b, bfloat %c) #0 {
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_fmuladd_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v2, v0, v1
-; GFX11-NEXT: v_bfe_u32 v0, v2, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v1, 0x400000, v2
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11TRUE16-LABEL: v_fmuladd_bf16:
+; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v2, v0, v1
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11FAKE16-LABEL: v_fmuladd_bf16:
+; GFX11FAKE16: ; %bb.0:
+; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_fmac_f32_e32 v2, v0, v1
+; GFX11FAKE16-NEXT: v_bfe_u32 v0, v2, 16, 1
+; GFX11FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v2
+; GFX11FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_add3_u32 v0, v0, v2, 0x7fff
+; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-LABEL: v_fmuladd_bf16:
; GFX1250: ; %bb.0:
@@ -51016,12 +51221,12 @@ define <2 x bfloat> @v_fmuladd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfl
; GFX11TRUE16-LABEL: v_fmuladd_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_dual_fmac_f32 v2, v0, v1 :: v_dual_fmac_f32 v3, v5, v4
; GFX11TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
@@ -51032,14 +51237,12 @@ define <2 x bfloat> @v_fmuladd_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfl
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v3, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmuladd_v2bf16:
@@ -51263,43 +51466,40 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX11TRUE16-LABEL: v_fmuladd_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_lshlrev_b32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v6, v8, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v5, 16, v5
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v0, 0x400000, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v7, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v4
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11TRUE16-NEXT: v_bfe_u32 v1, v6, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v1, v1, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v7.l
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v0, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmuladd_v3bf16:
@@ -51583,52 +51783,48 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX11TRUE16-LABEL: v_fmuladd_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v1
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v5, v1, v3
-; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_and_b32 v7, 0xffff0000, v4
-; GFX11TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_dual_fmac_f32 v6, v8, v7 :: v_dual_lshlrev_b32 v7, 16, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
+; GFX11TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v9, v6, 0x7fff
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
+; GFX11TRUE16-NEXT: v_fmac_f32_e32 v3, v0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_fmac_f32_e32 v7, v10, v8
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11TRUE16-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v1, v9, v6, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v0, v5, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v7, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX11TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v0, v7, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v7, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v9, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v0, v0, v7, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v7, v0, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_fmuladd_v4bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll b/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
index faf08793163a13..36fe26ea5bcb9f 100644
--- a/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
@@ -201,11 +201,6 @@ define <10 x i16> @bitcast_i160_to_v10i16(i160 %int) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: bitcast_i160_to_v10i16:
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index ab9dd628ff83c6..42524d04e7f7dc 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -905,9 +905,8 @@ define float @missing_truncate_promote_bitreverse(i32 %arg) {
; GFX11-FLAT-TRUE16: ; %bb.0: ; %bb
; GFX11-FLAT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FLAT-TRUE16-NEXT: v_bfrev_b32_e32 v0, v0
-; GFX11-FLAT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FLAT-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-FLAT-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-FLAT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FLAT-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-FLAT-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FLAT-FAKE16-LABEL: missing_truncate_promote_bitreverse:
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index 4719d6edbaaa50..39c7ce1d45d833 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -8976,28 +8976,25 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
@@ -9451,10 +9448,10 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_add_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -9464,14 +9461,11 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -10009,12 +10003,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-TRUE16-NEXT: ; Child Loop BB28_6 Depth 2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX11-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v8
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, v6, v8 :: v_dual_add_f32 v5, v5, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
@@ -10027,11 +10021,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB28_6: ; Parent Loop BB28_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
@@ -10801,28 +10792,25 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
@@ -11276,10 +11264,10 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace
; GFX11-TRUE16-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_add_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -11289,14 +11277,11 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -11743,28 +11728,25 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
@@ -12218,10 +12200,10 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re
; GFX11-TRUE16-NEXT: .LBB32_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_add_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -12231,14 +12213,11 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -12682,10 +12661,10 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: .LBB33_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v3 :: v_dual_add_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_add_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -12695,14 +12674,11 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index fbfbf7249f2fd5..a53dc42db180b6 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -7343,30 +7343,27 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v1, v1, v3
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v1, v1, v2
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v0, v0, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v0, v0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -7510,28 +7507,25 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v1, v1, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
@@ -7924,11 +7918,11 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v3 :: v_dual_max_num_f32 v0, v0, v2
+; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v2 :: v_dual_max_num_f32 v0, v0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -7939,14 +7933,11 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8086,10 +8077,10 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v3 :: v_dual_max_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v2 :: v_dual_max_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -8099,14 +8090,11 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -8523,14 +8511,14 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v9 :: v_dual_max_num_f32 v5, v5, v8
+; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v6, v6, v8 :: v_dual_max_num_f32 v5, v5, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
@@ -8545,10 +8533,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
@@ -8827,12 +8812,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-TRUE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX11-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v9 :: v_dual_max_f32 v5, v5, v8
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v6, v6, v8 :: v_dual_max_f32 v5, v5, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
@@ -8845,11 +8830,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index b7efd8ea18d8cb..629333653b6332 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -7343,30 +7343,27 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v1, v1, v3
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v1, v1, v2
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v0, v0, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v0, v0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -7510,28 +7507,25 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v1, v1, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v6 :: v_dual_mov_b32 v0, v5
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[0:1], v4, s[0:3], 0 offen offset:1024 glc
@@ -7924,11 +7918,11 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v3 :: v_dual_min_num_f32 v0, v0, v2
+; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v2 :: v_dual_min_num_f32 v0, v0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -7939,14 +7933,11 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX12-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], null offen offset:1024 th:TH_ATOMIC_RETURN
@@ -8086,10 +8077,10 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: .LBB20_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v3 :: v_dual_min_f32 v0, v0, v2
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v2 :: v_dual_min_f32 v0, v0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
@@ -8099,14 +8090,11 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
; GFX11-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[5:6], v4, s[0:3], 0 offen offset:1024 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -8523,14 +8511,14 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX12-TRUE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX12-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v6, v6, v9 :: v_dual_min_num_f32 v5, v5, v8
+; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v6, v6, v8 :: v_dual_min_num_f32 v5, v5, v9
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
@@ -8545,10 +8533,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX12-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
@@ -8827,12 +8812,12 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: ; =>This Loop Header: Depth=1
; GFX11-TRUE16-NEXT: ; Child Loop BB21_6 Depth 2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v7
; GFX11-TRUE16-NEXT: s_mov_b32 s5, exec_lo
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s5
-; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v9 :: v_dual_min_f32 v5, v5, v8
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v6, v6, v8 :: v_dual_min_f32 v5, v5, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
@@ -8845,11 +8830,8 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v11, v13, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.h
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v6, v7
; GFX11-TRUE16-NEXT: .LBB21_6: ; Parent Loop BB21_5 Depth=1
; GFX11-TRUE16-NEXT: ; => This Inner Loop Header: Depth=2
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
index f38ac4dee69c21..466b475ed487d2 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
@@ -528,26 +528,14 @@ define void @undef_lo2_v4i16(<2 x i16> %arg0) {
; GFX11-FAKE16-NEXT: ;;#ASMEND
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-SDAG-LABEL: undef_lo2_v4i16:
-; GFX11-TRUE16-SDAG: ; %bb.0:
-; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-SDAG-NEXT: ; use v[0:1]
-; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-GISEL-LABEL: undef_lo2_v4i16:
-; GFX11-TRUE16-GISEL: ; %bb.0:
-; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-GISEL-NEXT: ; use v[0:1]
-; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: undef_lo2_v4i16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-NEXT: ; use v[0:1]
+; GFX11-TRUE16-NEXT: ;;#ASMEND
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
%undef.lo = shufflevector <2 x i16> %arg0, <2 x i16> poison, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.lo);
ret void
@@ -594,25 +582,14 @@ define void @undef_lo2_v4f16(<2 x half> %arg0) {
; GFX11-FAKE16-NEXT: ;;#ASMEND
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-SDAG-LABEL: undef_lo2_v4f16:
-; GFX11-TRUE16-SDAG: ; %bb.0:
-; GFX11-TRUE16-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-TRUE16-SDAG-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-SDAG-NEXT: ; use v[0:1]
-; GFX11-TRUE16-SDAG-NEXT: ;;#ASMEND
-; GFX11-TRUE16-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-TRUE16-GISEL-LABEL: undef_lo2_v4f16:
-; GFX11-TRUE16-GISEL: ; %bb.0:
-; GFX11-TRUE16-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-GISEL-NEXT: ;;#ASMSTART
-; GFX11-TRUE16-GISEL-NEXT: ; use v[0:1]
-; GFX11-TRUE16-GISEL-NEXT: ;;#ASMEND
-; GFX11-TRUE16-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: undef_lo2_v4f16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: ;;#ASMSTART
+; GFX11-TRUE16-NEXT: ; use v[0:1]
+; GFX11-TRUE16-NEXT: ;;#ASMEND
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
%undef.lo = shufflevector <2 x half> %arg0, <2 x half> poison, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.lo);
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
index bf3e662e08d9b6..81425059a46a7f 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
@@ -30,9 +30,7 @@ define amdgpu_kernel void @build_vector_bfi (ptr addrspace(1) %a, ptr addrspace(
; GFX11-REAL16-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[REG_SEQUENCE]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s32) from %ir.in.gep1, addrspace 1)
; GFX11-REAL16-NEXT: [[GLOBAL_LOAD_DWORD_SADDR1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[REG_SEQUENCE1]], [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s32) from %ir.in.gep2, addrspace 1)
; GFX11-REAL16-NEXT: [[COPY8:%[0-9]+]]:vgpr_16 = COPY [[GLOBAL_LOAD_DWORD_SADDR]].lo16
- ; GFX11-REAL16-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GFX11-REAL16-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_2]], killed [[GLOBAL_LOAD_DWORD_SADDR1]], implicit $exec
- ; GFX11-REAL16-NEXT: [[COPY9:%[0-9]+]]:vgpr_16 = COPY [[V_LSHRREV_B32_e64_]].lo16
+ ; GFX11-REAL16-NEXT: [[COPY9:%[0-9]+]]:vgpr_16 = COPY [[GLOBAL_LOAD_DWORD_SADDR1]].hi16
; GFX11-REAL16-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[COPY8]], %subreg.lo16, killed [[COPY9]], %subreg.hi16
; GFX11-REAL16-NEXT: GLOBAL_STORE_DWORD_SADDR killed [[V_MOV_B32_e32_]], killed [[REG_SEQUENCE3]], killed [[REG_SEQUENCE2]], 0, 0, implicit $exec :: (store (s32) into %ir.3, addrspace 1)
; GFX11-REAL16-NEXT: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index 9a3bc328226bba..5ba67249c534be 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -681,7 +681,7 @@ define amdgpu_kernel void @vload2_private(ptr addrspace(1) nocapture readonly %i
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: scratch_load_b32 v0, off, off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v1, off, off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[2:3]
@@ -819,9 +819,7 @@ define <2 x i16> @chain_hi_to_lo_group_other_dep_multi_chain(ptr addrspace(3) %p
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 12 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -955,9 +953,7 @@ define <2 x i16> @chain_hi_to_lo_global_other_dep(ptr addrspace(1) %ptr) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 12 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.h
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1031,9 +1027,7 @@ define <2 x i16> @chain_hi_to_lo_flat_other_dep(ptr addrspace(0) %ptr) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 12 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.h
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
index f8b1448a612e09..2ce5ae6a93bb9d 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
@@ -1326,12 +1326,10 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1382,12 +1380,10 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1480,12 +1476,10 @@ define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v2.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1620,12 +1614,10 @@ define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3.l, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.h, v2.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
index f526cc470b893b..550cfec413d79a 100644
--- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
@@ -521,12 +521,10 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GCN-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1
+; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3.l, v1.l
+; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -557,12 +555,10 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1
+; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3.l, v1.l
+; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -617,12 +613,10 @@ define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GCN-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1
+; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3.l, v1.l
+; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -701,12 +695,10 @@ define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) {
; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
-; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GCN-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l
+; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1
+; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3.l, v1.l
+; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.h
; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index fdfade8417b718..5e14d351e1706d 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1732,29 +1732,26 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX11-TRUE16-NEXT: global_load_b32 v5, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v5.l, 9
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff00, v5.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v5.h, 9
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v5.l, 9
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff00, v5.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff00, v5.l
; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte3_e32 v3, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v2.l, 9
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff00, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte2_e32 v2, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte2_e32 v2, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v1.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v1.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte1_e32 v1, v5
; GFX11-TRUE16-NEXT: v_cvt_f32_ubyte0_e32 v0, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x900, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x900, v4.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x900, v4.l
+; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x900, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b128 v6, v[0:3], s[0:1]
-; GFX11-TRUE16-NEXT: global_store_b32 v6, v4, s[2:3]
+; GFX11-TRUE16-NEXT: global_store_b32 v6, v5, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: load_v4i8_to_v4f32_2_uses:
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index d776749dcdbce0..87ed1342096574 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -2852,7 +2852,7 @@ define bfloat @fmul_select_bf16_test1(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test1:
@@ -3038,7 +3038,7 @@ define bfloat @fmul_select_bf16_test2(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test2:
@@ -3274,16 +3274,16 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0x3f80
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, 0x4000, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, 0x4000, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
@@ -3298,11 +3298,8 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2bf16_test3:
@@ -3576,16 +3573,16 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, 0x3f80
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, 0x3f00, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, 0x3f00, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v3, v1
; GFX11-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
@@ -3600,11 +3597,8 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_v2bf16_test4:
@@ -3829,7 +3823,7 @@ define bfloat @fmul_select_bf16_test5(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test5:
@@ -4017,7 +4011,7 @@ define bfloat @fmul_select_bf16_test6(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test6:
@@ -4204,7 +4198,7 @@ define bfloat @fmul_select_bf16_test7(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test7:
@@ -4386,7 +4380,7 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test8:
@@ -4571,7 +4565,7 @@ define bfloat @fmul_select_bf16_test9(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test9:
@@ -4759,7 +4753,7 @@ define bfloat @fmul_select_bf16_test10_sel_log2val_pos65_pos56(bfloat %x, i32 %b
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
@@ -4947,7 +4941,7 @@ define bfloat @fmul_select_bf16_test11_sel_log2val_neg22_pos25(bfloat %x, i32 %b
; GFX11-SDAG-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
index 60f7125f9b628d..015185fcea7d90 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
@@ -549,9 +549,9 @@ define i32 @divergent_vec_i16_LH(i16 %a, i32 %b) {
; GFX11-TRUE16-LABEL: divergent_vec_i16_LH:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: divergent_vec_i16_LH:
@@ -647,10 +647,9 @@ define i32 @divergent_vec_i16_HH(i32 %a, i32 %b) {
; GFX11-TRUE16-LABEL: divergent_vec_i16_HH:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: divergent_vec_i16_HH:
diff --git a/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll b/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
new file mode 100644
index 00000000000000..a5c1f520f36eec
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 -global-isel < %s | FileCheck -check-prefixes=GFX12-GISEL %s
+
+define amdgpu_cs void @extract_hi16_i16_add(i32 %x, i32 %y, ptr addrspace(1) %out) {
+; GFX12-TRUE16-LABEL: extract_hi16_i16_add:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.h, v1.l
+; GFX12-TRUE16-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: extract_hi16_i16_add:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX12-FAKE16-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: extract_hi16_i16_add:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.h, v1.l
+; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-GISEL-NEXT: s_endpgm
+ %shift = lshr i32 %x, 16
+ %trunc = trunc i32 %shift to i16
+ %ylo = trunc i32 %y to i16
+ %add = add i16 %trunc, %ylo
+ store i16 %add, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @extract_hi16_f16_fadd(<2 x half> %v, ptr addrspace(1) %out) {
+; GFX12-TRUE16-LABEL: extract_hi16_f16_fadd:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-TRUE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: extract_hi16_f16_fadd:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v0, v3
+; GFX12-FAKE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: extract_hi16_f16_fadd:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-GISEL-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-NEXT: s_endpgm
+ %lo = extractelement <2 x half> %v, i32 0
+ %hi = extractelement <2 x half> %v, i32 1
+ %add = fadd half %lo, %hi
+ store half %add, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @extract_hi16_uitofp_v2i16(<2 x i16> %v, ptr addrspace(1) %out) {
+; GFX12-TRUE16-LABEL: extract_hi16_uitofp_v2i16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: global_store_b32 v[1:2], v0, off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: extract_hi16_uitofp_v2i16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v3, v3
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v3
+; GFX12-FAKE16-NEXT: global_store_b32 v[1:2], v0, off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: extract_hi16_uitofp_v2i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
+; GFX12-GISEL-NEXT: global_store_b32 v[1:2], v0, off
+; GFX12-GISEL-NEXT: s_endpgm
+ %r = uitofp nneg <2 x i16> %v to <2 x half>
+ store <2 x half> %r, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @extract_hi16_uitofp_v4i16(<4 x i16> %v, ptr addrspace(1) %out) {
+; GFX12-TRUE16-LABEL: extract_hi16_uitofp_v4i16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: extract_hi16_uitofp_v4i16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v4, v4
+; GFX12-FAKE16-NEXT: v_cvt_f16_u16_e32 v5, v5
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v4
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v5
+; GFX12-FAKE16-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: extract_hi16_uitofp_v4i16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v1.l, v1.l
+; GFX12-GISEL-NEXT: v_cvt_f16_u16_e32 v1.h, v1.h
+; GFX12-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX12-GISEL-NEXT: s_endpgm
+ %r = uitofp nneg <4 x i16> %v to <4 x half>
+ store <4 x half> %r, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @no_extract_hi16_multi_use_shift(i32 %x, i32 %y, ptr addrspace(1) %out0, ptr addrspace(1) %out1) {
+; GFX12-TRUE16-LABEL: no_extract_hi16_multi_use_shift:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_add_nc_u16 v0.l, v6.l, v1.l
+; GFX12-TRUE16-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-TRUE16-NEXT: global_store_b32 v[4:5], v6, off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: no_extract_hi16_multi_use_shift:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_add_nc_u16 v1, v0, v1
+; GFX12-FAKE16-NEXT: global_store_b16 v[2:3], v1, off
+; GFX12-FAKE16-NEXT: global_store_b32 v[4:5], v0, off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: no_extract_hi16_multi_use_shift:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v6.l, v1.l
+; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-GISEL-NEXT: global_store_b32 v[4:5], v6, off
+; GFX12-GISEL-NEXT: s_endpgm
+ %shift = lshr i32 %x, 16
+ %trunc = trunc i32 %shift to i16
+ %ylo = trunc i32 %y to i16
+ %add = add i16 %trunc, %ylo
+ store i16 %add, ptr addrspace(1) %out0
+ store i32 %shift, ptr addrspace(1) %out1
+ ret void
+}
+
+define amdgpu_cs void @no_extract_hi16_shift_amount_8(i32 %x, ptr addrspace(1) %out) {
+; GFX12-TRUE16-LABEL: no_extract_hi16_shift_amount_8:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX12-TRUE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: no_extract_hi16_shift_amount_8:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX12-FAKE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: no_extract_hi16_shift_amount_8:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX12-GISEL-NEXT: global_store_b16 v[1:2], v0, off
+; GFX12-GISEL-NEXT: s_endpgm
+ %shift = lshr i32 %x, 8
+ %trunc = trunc i32 %shift to i16
+ store i16 %trunc, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_cs void @no_extract_hi16_uniform_sgpr(<2 x half> inreg %v, ptr addrspace(1) inreg %out) {
+; GFX12-TRUE16-LABEL: no_extract_hi16_uniform_sgpr:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: s_cmp_eq_f16 s0, s1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, s0
+; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX12-TRUE16-NEXT: s_endpgm
+;
+; GFX12-FAKE16-LABEL: no_extract_hi16_uniform_sgpr:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX12-FAKE16-NEXT: s_cmp_eq_f16 s0, s1
+; GFX12-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, s1, v0, vcc_lo
+; GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX12-FAKE16-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: no_extract_hi16_uniform_sgpr:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_mov_b32 s4, s1
+; GFX12-GISEL-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GISEL-NEXT: s_cmp_eq_f16 s0, s1
+; GFX12-GISEL-NEXT: s_mov_b32 s5, s2
+; GFX12-GISEL-NEXT: s_cselect_b32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-GISEL-NEXT: global_store_b16 v1, v0, s[4:5]
+; GFX12-GISEL-NEXT: s_endpgm
+ %lo = extractelement <2 x half> %v, i32 0
+ %hi = extractelement <2 x half> %v, i32 1
+ %cmp = fcmp oeq half %lo, %hi
+ %sel = select i1 %cmp, half %lo, half %hi
+ store half %sel, ptr addrspace(1) %out
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index 176dffac4abc5a..a0a8b7c26ddd3c 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -152,15 +152,11 @@ define <4 x i16> @vec_8xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1)
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v3.l
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v2, 15, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16:
@@ -365,16 +361,14 @@ define <4 x i16> @vec_8xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB1_5: ; %exit
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_8xi16_extract_4xi16_2:
@@ -579,18 +573,17 @@ define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB2_5: ; %exit
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3900
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s0, 0.5, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, 0.5, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3d00
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s1, 0.5, v2.l
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s1, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v1.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, 0x3d00, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0x3d00, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, 0x3900, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3900, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3900, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3900, v1.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_8xf16_extract_4xf16:
@@ -841,15 +834,11 @@ define <4 x i16> @vec_16xi16_extract_4xi16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 15, v3.l
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v2, 15, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16:
@@ -1101,16 +1090,14 @@ define <4 x i16> @vec_16xi16_extract_4xi16_2(ptr addrspace(1) %p0, ptr addrspace
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB4_5: ; %exit
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, 15, v5 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 15, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xi16_extract_4xi16_2:
@@ -1362,18 +1349,17 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB5_5: ; %exit
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3900
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s0, 0.5, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, 0.5, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3d00
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s1, 0.5, v2.l
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s1, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v1.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, 0x3d00, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0x3d00, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, 0x3900, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3900, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3900, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3900, v1.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xf16_extract_4xf16:
@@ -1758,27 +1744,23 @@ define amdgpu_gfx <8 x i16> @vec_16xi16_extract_8xi16_0(i1 inreg %cond, ptr addr
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB7_5: ; %exit
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x3801, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x3900
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 0x3801, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_cmp_lt_u16_e64 s1, 0x3800, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 0x3801, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s2, 0x3801, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s3, 0x3801, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_u16_e32 vcc_lo, 0x3800, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x3d00
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 0x3801, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s1, 0x3801, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s2, 0x3801, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s3, 0x3801, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.l, 0x3900, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x3900, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e32 vcc_lo, 0x3801, v5.h
+; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s0, 0x3801, v4.h
; GFX11-TRUE16-NEXT: v_cmp_gt_u16_e64 s34, 0x3801, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, 0x3d00, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, 0x3d00, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, 0x3d00, s34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x3d00, v3.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3900, v3.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3900, v3.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3900, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3900, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x3900, v3.l, s34
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x3900, v3.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xi16_extract_8xi16_0:
@@ -2100,27 +2082,23 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB8_5: ; %exit
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x3900
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s1, 0.5, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s3, 0.5, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, 0.5, v7.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x3d00
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s1, 0.5, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s3, 0.5, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.l, 0x3900, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x3900, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v5.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v4.h
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s34, 0.5, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, 0x3d00, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, 0x3d00, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, 0x3d00, s34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x3d00, v3.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3900, v3.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3900, v3.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3900, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3900, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x3900, v3.l, s34
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x3900, v3.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xf16_extract_8xf16_0:
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
index e95de144525cc7..0c9553f9b7faa3 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
@@ -670,34 +670,30 @@ define amdgpu_kernel void @v_extractelement_v8f16_dynamic_sgpr(ptr addrspace(1)
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 1, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.h, s2
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_extractelement_v8f16_dynamic_sgpr:
@@ -912,67 +908,59 @@ define amdgpu_kernel void @v_extractelement_v16f16_dynamic_sgpr(ptr addrspace(1)
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v9.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 1, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 1, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 9
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v5.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v6
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v6.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v6.h, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v7.l, s2
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v7.h, s2
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_extractelement_v16f16_dynamic_sgpr:
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
index be4d3e4c0fcdb5..043a3361944f49 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
@@ -618,34 +618,29 @@ define amdgpu_kernel void @v_fabs_fold_self_v2bf16(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v2.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_dual_mul_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v3, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b32 v2, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -804,18 +799,17 @@ define amdgpu_kernel void @v_fabs_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, 0xffff0000
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[2:3]
+; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s4, 16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, s2, v0
-; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s4, 16
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, 0xffff0000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
@@ -831,10 +825,7 @@ define amdgpu_kernel void @v_fabs_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v3, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: global_store_b32 v2, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -988,16 +979,15 @@ define amdgpu_kernel void @v_extract_fabs_fold_v2bf16(ptr addrspace(1) %in) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 2.0, v1 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, 4.0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
index 2cb7c5d8690822..c14a3231eebb63 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
@@ -733,10 +733,8 @@ define amdgpu_kernel void @v_extract_fabs_fold_v2f16(ptr addrspace(1) %in) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, |v0.l|, 4.0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.h, |v1.l|, 2.0
+; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.h, |v0.h|, 2.0
; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v[0:1], v0, off dlc
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 04632801c6ed14..07d6db5bb3d271 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -3292,13 +3292,10 @@ define <2 x float> @v_copysign_out_v2f32_mag_v2f32_sign_v2bf16(<2 x float> %mag,
; GFX11TRUE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2bf16:
@@ -3371,13 +3368,10 @@ define <2 x double> @v_copysign_out_v2f64_mag_v2f64_sign_v2bf16(<2 x double> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v4.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v5.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v4
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v5
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2bf16:
@@ -3490,23 +3484,20 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f32_sign_v2bf16(<2 x float> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v2bf16_mag_v2f32_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v2
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2bf16_mag_v2f32_sign_v2bf16:
@@ -3687,18 +3678,18 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX11TRUE16-LABEL: v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v9, v[2:3]
-; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v10, v[0:1]
+; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v9, v[0:1]
+; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v10, v[2:3]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[5:6], v9
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[7:8], v10
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[5:6]|
-; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[2:3], v[5:6]
-; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[0:1], v[7:8]
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[5:6]|
+; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[5:6]
+; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[2:3], v[7:8]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v5, -1, 1, s1
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[0:1]|, |v[7:8]|
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s1, |v[2:3]|, |v[7:8]|
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v5, v9, v5
; GFX11TRUE16-NEXT: v_and_b32_e32 v6, 1, v10
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -3712,7 +3703,7 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc_lo
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s0, s2
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -3721,16 +3712,13 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16(<2 x double> %m
; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v5
; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v6
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc_lo
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v4
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v4
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2bf16_mag_v2f64_sign_v2bf16:
@@ -3876,23 +3864,20 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2bf16_sign_v2f32(<2 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f32:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v1, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.h
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f32:
@@ -3977,11 +3962,9 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64(<2 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v4
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64:
@@ -5034,15 +5017,12 @@ define <3 x float> @v_copysign_out_v3f32_mag_v3f32_sign_v3bf16(<3 x float> %mag,
; GFX11TRUE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l
; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v5
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3bf16:
@@ -5127,15 +5107,12 @@ define <3 x double> @v_copysign_out_v3f64_mag_v3f64_sign_v3bf16(<3 x double> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v6
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v8.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v6
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v6
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v7
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v7
+; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v8
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3bf16:
@@ -5281,31 +5258,27 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f32_sign_v3bf16(<3 x float> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v3bf16_mag_v3f32_sign_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v8, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v3
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v4
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3bf16_mag_v3f32_sign_v3bf16:
@@ -5553,68 +5526,65 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16(<3 x double> %m
; GFX11TRUE16-LABEL: v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v16, v[4:5]
-; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v14, v[2:3]
-; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v15, v[0:1]
+; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v14, v[0:1]
+; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v15, v[4:5]
+; GFX11TRUE16-NEXT: v_cvt_f32_f64_e32 v16, v[2:3]
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[8:9], v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[10:11], v15
-; GFX11TRUE16-NEXT: v_and_b32_e32 v18, 1, v16
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s4, |v[4:5]|, |v[12:13]|
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s2, |v[2:3]|, |v[8:9]|
-; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[2:3], v[8:9]
-; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s1, v[4:5], v[12:13]
-; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[0:1], v[10:11]
-; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[10:11]|
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cvt_f64_f32_e32 v[12:13], v16
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[0:1]|, |v[8:9]|
+; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e32 vcc_lo, v[0:1], v[8:9]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s0, v[4:5], v[10:11]
+; GFX11TRUE16-NEXT: v_cmp_nlg_f64_e64 s1, v[2:3], v[12:13]
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v8, -1, 1, s3
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[4:5]|, |v[10:11]|
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v9, -1, 1, s3
+; GFX11TRUE16-NEXT: v_cmp_gt_f64_e64 s3, |v[2:3]|, |v[12:13]|
+; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v10, -1, 1, s3
; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v10, v16, v10
-; GFX11TRUE16-NEXT: v_and_b32_e32 v17, 1, v14
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v8, v14, v8
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
-; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s2
-; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_and_b32 v19, 1, v15
-; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v19, 1, v14
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 1, v19
+; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, vcc_lo, s3
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_and_b32 v17, 1, v15
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 1, v17
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
-; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s1, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s0, s2
+; GFX11TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_and_b32 v18, 1, v16
+; GFX11TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v8
; GFX11TRUE16-NEXT: v_add3_u32 v8, v11, v8, 0x7fff
-; GFX11TRUE16-NEXT: s_or_b32 s0, s0, s3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_bfe_u32 v11, v10, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v10
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v13, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v11, v10, 0x7fff
-; GFX11TRUE16-NEXT: v_add_nc_u32_e32 v9, v15, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e64 v9, v9, v15, s0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 1, v18
; GFX11TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s1, s4
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v9, v12, v9, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v14, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
+; GFX11TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_add3_u32 v10, v14, v10, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v8, v15, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v6
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v7
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v2, v6
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3bf16_mag_v3f64_sign_v3bf16:
@@ -5810,31 +5780,27 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3bf16_sign_v3f32(<3 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v3bf16_mag_v3bf16_sign_v3f32:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v8, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v9, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v3
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v7, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v2
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v3bf16_mag_v3bf16_sign_v3f32:
@@ -5952,7 +5918,7 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3bf16_sign_v3f64(<3 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v3bf16_mag_v3bf16_sign_v3f64:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
@@ -6149,19 +6115,13 @@ define <4 x float> @v_copysign_out_v4f32_mag_v4f32_sign_v4bf16(<4 x float> %mag,
; GFX11TRUE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v4.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v5.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
-; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v5
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
+; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v6
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v7
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v6
+; GFX11TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v7
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4bf16:
@@ -6261,19 +6221,13 @@ define <4 x double> @v_copysign_out_v4f64_mag_v4f64_sign_v4bf16(<4 x double> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v8.h, v8.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.h, v9.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v10.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v11.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v8
-; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v9
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v10.h, v8.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v11.h, v9.l
+; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
+; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v9
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v10
-; GFX11TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v11
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v10
+; GFX11TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v11
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4bf16:
@@ -6454,37 +6408,31 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f32_sign_v4bf16(<4 x float> %ma
; GFX11TRUE16-LABEL: v_copysign_out_v4bf16_mag_v4f32_sign_v4bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v0, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v1, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v0
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v10, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v4
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v1, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v9, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v4
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v3, v5
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4bf16_mag_v4f32_sign_v4bf16:
@@ -6852,34 +6800,28 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16(<4 x double> %m
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 1, v25
; GFX11TRUE16-NEXT: v_bfe_u32 v18, v12, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v12
+; GFX11TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v12
; GFX11TRUE16-NEXT: s_or_b32 vcc_lo, s2, s6
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_add3_u32 v12, v18, v12, 0x7fff
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[6:7]
-; GFX11TRUE16-NEXT: v_bfe_u32 v20, v13, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_add3_u32 v13, v20, v13, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v6, v10, v15, vcc_lo
-; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v19, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[4:5], v[4:5]
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v11, v17, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v19, v13, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_add3_u32 v13, v19, v13, 0x7fff
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v11, v17, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[0:1], v[0:1]
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v13, v21, vcc_lo
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v3, v9
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v8
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[6:7], v[6:7]
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f64_e32 vcc_lo, v[2:3], v[2:3]
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v9
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v12, v20, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v2, v8
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4bf16_mag_v4f64_sign_v4bf16:
@@ -7123,37 +7065,31 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f32(<4 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f32:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
-; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v8, v8, v3, 0x7fff
-; GFX11TRUE16-NEXT: v_bfe_u32 v10, v2, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v2
-; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v9, vcc_lo
-; GFX11TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11TRUE16-NEXT: v_add3_u32 v10, v10, v2, 0x7fff
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v9, v2, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
+; GFX11TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
+; GFX11TRUE16-NEXT: v_bfe_u32 v11, v3, 16, 1
+; GFX11TRUE16-NEXT: v_add3_u32 v9, v9, v2, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v2
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v4, v7, v10, vcc_lo
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v10, v11, vcc_lo
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v4
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
+; GFX11TRUE16-NEXT: v_add3_u32 v7, v11, v3, 0x7fff
+; GFX11TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v2, v9, v12, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v8, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v5
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f32:
@@ -7277,16 +7213,11 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64(<4 x bfloat> %m
; GFX11TRUE16-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v9
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.h
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v5
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v5
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v9
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64:
@@ -7972,23 +7903,20 @@ define <2 x bfloat> @v_copysign_v2bf16_0_v2bf32(<2 x float> %sign) {
; GFX11TRUE16-LABEL: v_copysign_v2bf16_0_v2bf32:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX11TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v0
+; GFX11TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX11TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v1
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_v2bf16_0_v2bf32:
@@ -8118,11 +8046,9 @@ define <2 x bfloat> @v_copysign_v2bf16_0_v2bf64(<2 x double> %sign) {
; GFX11TRUE16-LABEL: v_copysign_v2bf16_0_v2bf64:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
-; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v1
+; GFX11TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v3
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11FAKE16-LABEL: v_copysign_v2bf16_0_v2bf64:
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 9db4987fc82108..8b386d61472407 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -2726,13 +2726,11 @@ define <2 x float> @v_copysign_out_v2f32_mag_v2f16_sign_v2f32(<2 x half> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v3, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v3, v1
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f32_mag_v2f16_sign_v2f32:
@@ -2788,13 +2786,10 @@ define <2 x float> @v_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float> %mag,
; GFX11-TRUE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f32_mag_v2f32_sign_v2f16:
@@ -2850,13 +2845,10 @@ define <2 x double> @v_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x double> %mag
; GFX11-TRUE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v5.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f64_mag_v2f64_sign_v2f16:
@@ -3470,11 +3462,9 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f64(<2 x half> %mag, <2
; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:
@@ -4280,15 +4270,14 @@ define <3 x float> @v_copysign_out_v3f32_mag_v3f16_sign_v3f32(<3 x half> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v6, v4
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v5, v3
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v5, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v6, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v7, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f32_mag_v3f16_sign_v3f32:
@@ -4352,15 +4341,12 @@ define <3 x float> @v_copysign_out_v3f32_mag_v3f32_sign_v3f16(<3 x float> %mag,
; GFX11-TRUE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v5
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f32_mag_v3f32_sign_v3f16:
@@ -4424,15 +4410,12 @@ define <3 x double> @v_copysign_out_v3f64_mag_v3f64_sign_v3f16(<3 x double> %mag
; GFX11-TRUE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v6
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v7.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v7
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v7
+; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f64_mag_v3f64_sign_v3f16:
@@ -5267,7 +5250,7 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f64(<3 x half> %mag, <3
; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
@@ -5346,19 +5329,16 @@ define <4 x float> @v_copysign_out_v4f32_mag_v4f16_sign_v4f32(<4 x half> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v1.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v7.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v6, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v7, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v1, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v6, v3
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v7, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v8, v4
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v9, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v4f32_mag_v4f16_sign_v4f32:
@@ -5435,19 +5415,13 @@ define <4 x float> @v_copysign_out_v4f32_mag_v4f32_sign_v4f16(<4 x float> %mag,
; GFX11-TRUE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v5.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v4
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v4
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v6
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v7
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v6
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, v7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v4f32_mag_v4f32_sign_v4f16:
@@ -5524,19 +5498,13 @@ define <4 x double> @v_copysign_out_v4f64_mag_v4f64_sign_v4f16(<4 x double> %mag
; GFX11-TRUE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v9.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v11.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v8
-; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v9.l
+; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v8
+; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, v10
-; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, v11
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v10
+; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fffffff, v5, v11
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v4f64_mag_v4f64_sign_v4f16:
@@ -6597,16 +6565,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f16_sign_v4f64(<4 x half> %mag, <4
; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v9
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:
@@ -7272,11 +7235,9 @@ define <2 x half> @v_copysign_v2f16_0_v2bf64(<2 x double> %sign) {
; GFX11-TRUE16-LABEL: v_copysign_v2f16_0_v2bf64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x80008000, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_v2f16_0_v2bf64:
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
index d3a526dfbe4259..260ee9c514fabb 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
@@ -281,10 +281,8 @@ define <2 x bfloat> @v_rsq_v2bf16(<2 x bfloat> %a) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.h, v0.h
; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.l, v0.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.h, v1.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: v_rsq_v2bf16:
@@ -308,15 +306,13 @@ define <2 x bfloat> @v_neg_rsq_v2bf16(<2 x bfloat> %a) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.h, v0.h
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1250-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.h
; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.l, v0.l
; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1250-TRUE16-NEXT: v_rsq_bf16_e32 v0.h, v1.l
-; GFX1250-TRUE16-NEXT: v_nop
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GFX1250-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.h
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: v_neg_rsq_v2bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
index aeca505f7c5046..7ecae7e1cf8067 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
@@ -2154,10 +2154,8 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX11-TRUE16-LABEL: v_rsq_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_rsq_v2f16:
@@ -2367,13 +2365,11 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX11-TRUE16-LABEL: v_neg_rsq_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, 0x8000, v0.h
+; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_neg_rsq_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index 760308608c7d80..c228100ab7c0cd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -17632,19 +17632,18 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB68_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -17655,12 +17654,9 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17672,7 +17668,6 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB68_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -17964,19 +17959,18 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB69_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -17987,12 +17981,9 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18004,7 +17995,6 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB69_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18307,19 +18297,17 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v0, v[3:4]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB70_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v0, 16, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18331,11 +18319,8 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v0, v[3:4], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18347,7 +18332,6 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB70_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -18653,16 +18637,15 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB71_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18671,15 +18654,12 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18692,7 +18672,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB71_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -18973,16 +18952,15 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB72_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18991,15 +18969,12 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -19012,7 +18987,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB72_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19306,16 +19280,15 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB73_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -19324,15 +19297,12 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -19345,7 +19315,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB73_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -19647,19 +19616,18 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB74_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -19670,12 +19638,9 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -19687,7 +19652,6 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB74_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -19988,16 +19952,15 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB75_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -20006,15 +19969,12 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -20027,7 +19987,6 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB75_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20318,19 +20277,18 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB76_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -20341,12 +20299,9 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -20358,7 +20313,6 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB76_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -20650,16 +20604,15 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB77_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -20668,15 +20621,12 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -20689,7 +20639,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB77_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -20970,19 +20919,18 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB78_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -20993,12 +20941,9 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -21010,7 +20955,6 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB78_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -21302,16 +21246,15 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB79_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -21320,15 +21263,12 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -21341,7 +21281,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB79_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 91d75d70772591..bfaee0bbbee808 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -15169,12 +15169,12 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15186,13 +15186,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15309,19 +15306,18 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15332,12 +15328,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15349,7 +15342,6 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15627,12 +15619,12 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15644,13 +15636,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15767,19 +15756,18 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15790,12 +15778,9 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15807,7 +15792,6 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16090,12 +16074,12 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -16107,13 +16091,10 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16238,19 +16219,17 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v0, v[3:4]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v0, 16, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -16262,11 +16241,8 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v0, v[3:4], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16278,7 +16254,6 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16568,11 +16543,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16582,15 +16557,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16705,16 +16677,15 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16723,15 +16694,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16744,7 +16712,6 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17009,11 +16976,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17023,15 +16990,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -17146,16 +17110,15 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17164,15 +17127,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17185,7 +17145,6 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17457,11 +17416,11 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17471,15 +17430,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -17603,16 +17559,15 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17621,15 +17576,12 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17642,7 +17594,6 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17929,12 +17880,12 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -17946,13 +17897,10 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18071,19 +18019,18 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB60_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18094,12 +18041,9 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18111,7 +18055,6 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18395,11 +18338,11 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18409,15 +18352,12 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18534,16 +18474,15 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18552,15 +18491,12 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18573,7 +18509,6 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index f5564f14eee24f..c73b17d190f9af 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -15169,12 +15169,12 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15186,13 +15186,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15309,19 +15306,18 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15332,12 +15328,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15349,7 +15342,6 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15627,12 +15619,12 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15644,13 +15636,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15767,19 +15756,18 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15790,12 +15778,9 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15807,7 +15792,6 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16090,12 +16074,12 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -16107,13 +16091,10 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16238,19 +16219,17 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v0, v[3:4]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v0, 16, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -16262,11 +16241,8 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v0, v[3:4], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16278,7 +16254,6 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16568,11 +16543,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16582,15 +16557,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16705,16 +16677,15 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16723,15 +16694,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16744,7 +16712,6 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17009,11 +16976,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17023,15 +16990,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -17146,16 +17110,15 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17164,15 +17127,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17185,7 +17145,6 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17457,11 +17416,11 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17471,15 +17430,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -17603,16 +17559,15 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17621,15 +17576,12 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17642,7 +17594,6 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17929,12 +17880,12 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -17946,13 +17897,10 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18071,19 +18019,18 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB60_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18094,12 +18041,9 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18111,7 +18055,6 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18395,11 +18338,11 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18409,15 +18352,12 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18534,16 +18474,15 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18552,15 +18491,12 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -18573,7 +18509,6 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index 5f078cb96c5780..cc5204d00efdda 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -14587,12 +14587,12 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -14604,13 +14604,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -14727,19 +14724,18 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -14750,12 +14746,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -14767,7 +14760,6 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15045,12 +15037,12 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15062,13 +15054,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15185,19 +15174,18 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15208,12 +15196,9 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15225,7 +15210,6 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15508,12 +15492,12 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15525,13 +15509,10 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -15656,19 +15637,17 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v0, v[3:4]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_lshlrev_b32 v0, 16, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15680,11 +15659,8 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v0, v[3:4], v[5:6] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -15696,7 +15672,6 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -15986,11 +15961,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-TRUE16-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16000,15 +15975,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16123,16 +16095,15 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16141,15 +16112,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16162,7 +16130,6 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16427,11 +16394,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16441,15 +16408,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -16564,16 +16528,15 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16582,15 +16545,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -16603,7 +16563,6 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16875,11 +16834,11 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16889,15 +16848,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -17021,16 +16977,15 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
; GFX11-TRUE16-NEXT: flat_load_b32 v3, v[0:1]
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17039,15 +16994,12 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17060,7 +17012,6 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17347,12 +17298,12 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -17364,13 +17315,10 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -17489,19 +17437,18 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -17512,12 +17459,9 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[5:6] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17529,7 +17473,6 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -17813,11 +17756,11 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17827,15 +17770,12 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -17952,16 +17892,15 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17970,15 +17909,12 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: flat_atomic_cmpswap_b32 v2, v[0:1], v[2:3] offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -17991,7 +17927,6 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
index 0aada3a1c29767..e7d4f25c5db83c 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
@@ -4856,13 +4856,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase,
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[0:1]
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi:
@@ -4923,13 +4921,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inre
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[0:1] offset:-128
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_reg_hi_immneg128:
@@ -4991,13 +4987,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg %
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[0:1]
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi:
@@ -5059,13 +5053,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(p
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[0:1] offset:-128
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-NOECC-LABEL: flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128:
@@ -5130,13 +5122,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg %
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[0:1]
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi:
@@ -5217,13 +5207,11 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p
; GFX1250-SDAG-TRUE16-NEXT: v_nop
; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[0:1] offset:-128
-; GFX1250-SDAG-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX1250-SDAG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128:
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
index d4288ae2362e70..b9ac9dce0696c2 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
@@ -1832,135 +1832,133 @@ define <2 x i8> @to_fp8_v2f16_saturate(<2 x half> %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.h, v0.l
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x400
-; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v0
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.h, v0.l
+; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.h, v0.h
+; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v3.l, v0.h
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v4.h, 2, v2.l
; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v2.h, 8, v0.l
-; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v3.l, 2, v1.h
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v2.l, v1.l, 0x3ff bitop3:0xec
-; GFX1250-TRUE16-NEXT: v_and_b16 v4.l, 0x3ff, v2.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v5.l, 6, v2.l
-; GFX1250-TRUE16-NEXT: v_min_u16 v3.l, v3.l, 15
-; GFX1250-TRUE16-NEXT: v_and_b16 v2.l, v2.l, 63
-; GFX1250-TRUE16-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1250-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v6.h, 7, v4.l
-; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v7.l, v3.l, 1 clamp
-; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v5.h, v1.l, 0x3ff bitop3:0xec
-; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v2.l, 2, v6.l
-; GFX1250-TRUE16-NEXT: v_and_b16 v7.h, 0x3ff, v5.h
-; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v4.l, v1.h, v1.l, 0x3ff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.l, 0x3ff, v1.h
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v6.l, 6, v1.h
+; GFX1250-TRUE16-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1250-TRUE16-NEXT: v_and_b16 v1.h, v1.h, 63
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v6.h, 2, v3.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v3.l, v1.l, 0x3ff bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_and_b16 v7.l, 0x3ff, v3.l
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v8.l, v4.h, 1 clamp
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.h
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v7.h, 6, v3.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v3.l, v3.l, 63
+; GFX1250-TRUE16-NEXT: v_min_u16 v6.h, v6.h, 15
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.h, v8.l, 1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v8.h, 7, v5.l
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v8.h, 6, v5.h
-; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v5.h, 63
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v9.l, v3.l, v3.h
; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v8.l, -1
-; GFX1250-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 15
-; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1250-TRUE16-NEXT: v_and_b16 v8.l, v6.h, 1
-; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v9.l, 1
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v4.l, v3.l, 0x400 bitop3:0xc8
-; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v4.l, v2.l, 1 clamp
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v5.l, v5.l, v10.l, v8.l bitop3:0xe0
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.h, v7.l, v3.h
-; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
-; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v3.l, v4.l, 1
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v9.h, 7, v7.h
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v5.l, v6.h, v5.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v7.l, v2.l, v1.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.l, -1
-; GFX1250-TRUE16-NEXT: v_and_b16 v10.l, v9.h, 1
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, v4.l, v1.l
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v8.l, v13.l
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v7.h, v3.l, 0x400 bitop3:0xc8
-; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, 0x80, v2.h
+; GFX1250-TRUE16-NEXT: v_sub_nc_u16 v9.h, v6.h, 1 clamp
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, -1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v3.l, v4.h, v4.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v9.l, 7, v7.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v5.l, v1.h, 0x400 bitop3:0xc8
+; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, v8.h, 1
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v5.l, v10.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v11.l, v9.h, 1
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v4.l, v8.l, v4.l
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s0, 0, v1.h
+; GFX1250-TRUE16-NEXT: v_and_b16 v10.h, v9.l, 1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v6.l, v5.l, v4.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v5.l, v11.l, -1
+; GFX1250-TRUE16-NEXT: v_and_b16 v4.h, v3.l, 1
; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v3.h, v8.l, v5.h bitop3:0xe0
-; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, v7.l, 1
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v13.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v8.h, v11.l, v10.l bitop3:0xe0
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, v4.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, 0, s0
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.h, v9.l, v3.h
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v9.h, v3.l
-; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.h, 6
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 7, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v8.l, v14.l
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v8.h, v1.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v5.l, v7.l, v5.l, 0x400 bitop3:0xc8
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v10.l, v6.h, v1.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b16 v1.l, v9.h, v1.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v1.h
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v7.l, v10.l, 1
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v4.l, v4.l, v6.l, v4.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v4.h, v7.h, v8.l, v10.h bitop3:0xe0
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1250-TRUE16-NEXT: v_and_b16 v5.h, 0x80, v2.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, 0, v4.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v5.l, v11.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v12.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.l, v3.l, v4.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v4.l, v9.l, v4.h
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.l, v2.l, v5.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.l, v6.l, v7.l bitop3:0xe0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 3, v1.h
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, 0, s1
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 7, v3.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v1.l, v8.l, v5.h bitop3:0xe0
-; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v8, 0, 1, s2
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.h, 0, 8, s1
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 6, v4.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v2.l, v2.l, 6
; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
-; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v4.h, v2.l, v3.h bitop3:0xfe
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v4.h, v4.l, v5.l bitop3:0xfe
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v5.l, v6.l, v8.l
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v7.l, v1.l
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 31, v0
-; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 15, v1.h
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v2.l, vcc_lo
-; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.h, v5.l, 6
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s1
+; GFX1250-TRUE16-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.h, 0, 8, s1
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 3, v2.l
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.l, v10.l, v1.l
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s1, 6, v1.h
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v3.h, v3.h, v6.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.l, v5.h, v3.l, v4.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v4.h, v5.h, v1.h, v5.l bitop3:0xfe
; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 7, v1.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 31, v0
+; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v3.h, 6
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s2
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.h, 0, 8, s0
; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.l, 7, v6.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v6.l, 3, v1.h
+; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 15, v2.l
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.h, v3.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v5.l, v1.l, v3.h bitop3:0xfe
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v5.l, v4.l, v6.l bitop3:0xfe
; GFX1250-TRUE16-NEXT: s_and_b32 s3, s3, s1
-; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v5.h, 3, v0.h
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s0
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v4.l, 0, 8, s0
-; GFX1250-TRUE16-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 6, v3.l
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v3.h, v5.l, v3.l, v5.h bitop3:0xfe
-; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 15, v0.h
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.l, v5.l, v1.l, v4.l bitop3:0xfe
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 15, v0.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x7e
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s0, 6, v4.l
+; GFX1250-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 15, v1.h
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e64 s2, 15, v1.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x7e
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, v1.l, vcc_lo
+; GFX1250-TRUE16-NEXT: v_or_b16 v1.h, 0x7e, v5.l
; GFX1250-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.l, vcc_lo
-; GFX1250-TRUE16-NEXT: v_or_b16 v1.l, 0x7e, v5.l
-; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 15, v1.h
+; GFX1250-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 15, v2.l
; GFX1250-TRUE16-NEXT: s_or_b32 s0, s2, s0
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v1.h, v2.h, v3.l, 0x80 bitop3:0xec
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, s0
-; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v2.l, v2.h, v4.l, 0x80 bitop3:0xec
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v1.h, s0
+; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
; GFX1250-TRUE16-NEXT: s_or_b32 s1, vcc_lo, s3
; GFX1250-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.h, s1
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v2.l, s1
; GFX1250-TRUE16-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, s0
-; GFX1250-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX1250-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 0x204
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, vcc_lo
-; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v12.l, v12.l
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.l, s0
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, v5.h, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v1.h, s0
; GFX1250-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, v1.h, s1
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v2.l, s1
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, vcc_lo
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v1.l, s0
-; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v0.h
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0xff bitop3:0xec
-; GFX1250-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v0.h
+; GFX1250-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.h, s0
+; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
+; GFX1250-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 0xff bitop3:0xec
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_v2f16_saturate:
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
index 2df2dd63497058..cc038e9cb65ea7 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
@@ -1615,71 +1615,69 @@ define i8 @to_fp8_bf16(bfloat %x) {
; GFX1200-NEXT: v_cndmask_b32_e32 v7, v3, v4, vcc_lo
; GFX1200-NEXT: v_sub_nc_u16 v1.h, v1.l, 1 clamp
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 16, v7
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, v1.h, 1
+; GFX1200-NEXT: v_and_b16 v2.l, 0x7f, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, v1.h, 1
+; GFX1200-NEXT: v_and_b16 v3.l, v7.h, 7
; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v2.h, 0x7f, v3.l
-; GFX1200-NEXT: v_and_b16 v3.l, v3.l, 7
-; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, -1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v3.h, 0x80, v2.h
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, 4, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v3.h, 0x80, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v2.l, 4, v2.l
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b16 v2.l, v3.h, v2.l
-; GFX1200-NEXT: v_and_b16 v3.l, v2.h, 1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
+; GFX1200-NEXT: v_and_b16 v2.h, v3.h, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b16 v3.l, v2.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
; GFX1200-NEXT: v_lshrrev_b16 v4.h, v1.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v1.h, v1.h, v3.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v3.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_and_b16 v3.l, v4.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
-; GFX1200-NEXT: v_and_b16 v2.l, v7.l, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b16 v2.h, v7.l, v2.h
; GFX1200-NEXT: v_mov_b16_e32 v4.l, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.h, v2.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, v2.h
; GFX1200-NEXT: v_or_b16 v3.l, v4.l, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_and_b16 v1.l, v1.h, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
; GFX1200-NEXT: v_cmp_eq_f32_e64 s0, 0, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v1.l, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u16 v0.h, v4.h, v1.l
; GFX1200-NEXT: v_add_nc_u16 v1.l, v6.l, v3.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_add_nc_u16 v1.l, v1.l, 6
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_lshlrev_b16 v2.h, 3, v1.l
; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, 0, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b16 v1.h, v0.l, v1.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v2.h, v0.l, v2.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_or_b16 v0.h, v1.h, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_or_b16 v1.l, v2.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.l, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v5, v5
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v0.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, vcc_lo
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
index 3aec6c15ee0c8c..4ae07ec61a46d3 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
@@ -608,388 +608,386 @@ define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
-; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v2
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.l, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v3.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.l
+; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v4.h, 1 clamp
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
-; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v11.l, v6.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
-; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
-; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
-; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
-; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
-; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.l
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v4.h, v10.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v7.h
+; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v8.h, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 6, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.l, v7.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v11.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v5.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_and_b16 v10.l, v7.l, v10.h
+; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 1
+; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v10.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_and_b16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
-; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v14.l
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v11.h, v4.h
+; GFX1200-NEXT: v_and_b16 v4.l, v4.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 31, v1
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v4.l
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.h
+; GFX1200-NEXT: v_or_b16 v8.l, v6.h, v8.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s1
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v7.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
-; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v6.l, v7.l
+; GFX1200-NEXT: v_min_u16 v7.l, v9.h, 15
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v2.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.l, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v4.h
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.h, s1
+; GFX1200-NEXT: v_or_b16 v8.l, v5.l, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v9.h, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v2.h, v10.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v7.l, v10.l
+; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v8.h
+; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v3.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v6.l, 63
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
-; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
-; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.l, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.l, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.h
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.h, v10.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v1.l
+; GFX1200-NEXT: v_and_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
+; GFX1200-NEXT: v_and_b16 v3.h, v4.l, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v8.l
+; GFX1200-NEXT: v_or_b16 v5.l, v9.l, v7.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
-; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
+; GFX1200-NEXT: v_min_u16 v2.h, v4.l, 15
+; GFX1200-NEXT: v_and_b16 v4.l, v6.l, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v4.h, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v2.h, 1 clamp
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
+; GFX1200-NEXT: v_and_b16 v8.h, v5.l, 63
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, v6.l, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v2.h, v7.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v9.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v4.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, 7, v11.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v7.l, v10.h, v7.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v6.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.h, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v7.h
+; GFX1200-NEXT: v_or_b16 v4.h, v10.h, v6.h
+; GFX1200-NEXT: v_or_b16 v3.h, v7.l, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v0.h
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_or_b16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
-; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.l, v3.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
-; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
-; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
-; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v10.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v8.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.h, v1.h
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
-; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.l
+; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_and_b16 v4.l, v10.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v5.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v8.h, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_min_u16 v2.h, v4.h, 15
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, 63
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
-; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v0.l
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v2.h, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.h
; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
+; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v2.h, v9.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v2.h
; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v4.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.l, v5.l, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.l, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v10.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v1.h, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
-; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s3
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v4.h, s2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v0.l
+; GFX1200-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
-; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v5.h
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v7.h
+; GFX1200-NEXT: v_or_b16 v1.l, v6.l, v1.l
+; GFX1200-NEXT: v_or_b16 v8.l, v7.l, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v8.h, v7.l, v8.h
+; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s2
; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v3.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v1.l, vcc_lo
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
-; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, s0
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.h
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
+; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -1389,389 +1387,387 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
-; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v2
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.l, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v3.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v5.l
+; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 63
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v4.h, 1 clamp
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
-; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v11.l, v6.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
-; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
-; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
-; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
-; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
-; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.l
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v8.l, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v4.h, v10.l
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v7.h
+; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v8.h, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 6, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.l, v7.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v11.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v5.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_and_b16 v10.l, v7.l, v10.h
+; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 1
+; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v10.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_and_b16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
-; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v14.l
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v11.h, v4.h
+; GFX1200-NEXT: v_and_b16 v4.l, v4.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 31, v1
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v4.l
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.h
+; GFX1200-NEXT: v_or_b16 v8.l, v6.h, v8.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s1
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v7.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
-; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v6.l, v7.l
+; GFX1200-NEXT: v_min_u16 v7.l, v9.h, 15
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v7.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.h, v2.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.l, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v4.h
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.h, s1
+; GFX1200-NEXT: v_or_b16 v8.l, v5.l, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v9.h, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v2.h, v10.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v7.l, v10.l
+; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v8.h
+; GFX1200-NEXT: v_or_b16 v4.l, v9.h, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v3.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v6.l, 63
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
-; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
-; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.l, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.l, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.h
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.h, v10.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v1.l
+; GFX1200-NEXT: v_and_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, s0
+; GFX1200-NEXT: v_and_b16 v3.h, v4.l, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v8.l
+; GFX1200-NEXT: v_or_b16 v5.l, v9.l, v7.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
-; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
+; GFX1200-NEXT: v_min_u16 v2.h, v4.l, 15
+; GFX1200-NEXT: v_and_b16 v4.l, v6.l, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v4.h, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v2.h, 1 clamp
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
+; GFX1200-NEXT: v_and_b16 v8.h, v5.l, 63
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, v6.l, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v4.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, v2.h, v7.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v9.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v4.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, 7, v11.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v7.l, v10.h, v7.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v0.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v6.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.h, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v7.h
+; GFX1200-NEXT: v_or_b16 v4.h, v10.h, v6.h
+; GFX1200-NEXT: v_or_b16 v3.h, v7.l, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v0.h
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_or_b16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
-; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.l, v3.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.h, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
-; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
-; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, vcc_lo
+; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
-; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v10.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v8.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.h, v1.h
+; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 3, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v5.l, v9.h
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
-; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.l
+; GFX1200-NEXT: v_or_b16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_and_b16 v4.l, v10.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v5.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
-; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v8.h, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_min_u16 v2.h, v4.h, 15
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v0.l
+; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v2.h, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.h
; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
+; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_and_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_and_b16 v9.l, v4.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v2.h, v9.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v2.h
; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v4.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.l, v5.l, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.l, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v10.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v1.h, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
-; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s3
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v4.h, s2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v0.l
+; GFX1200-NEXT: v_or_b16 v6.l, v6.h, v6.l
; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
-; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s2
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v5.h
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v7.h
+; GFX1200-NEXT: v_or_b16 v1.l, v6.l, v1.l
+; GFX1200-NEXT: v_or_b16 v8.l, v7.l, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v8.h, v7.l, v8.h
+; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s2
; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v2.h, v7.l, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v3.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v1.l, vcc_lo
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
-; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, s0
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_lshrrev_b64 v[7:8], 24, v[5:6]
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v7.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -2281,514 +2277,496 @@ define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v3.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v3.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 31, v3
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v3.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v3.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v3.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v3
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v3.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v3.l
; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v4.l
-; GFX1200-NEXT: v_and_b16 v6.l, v4.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v13.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.l, v13.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_min_u16 v3.h, v5.h, 15
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, v4.h, 63
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v6.l
+; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
+; GFX1200-NEXT: v_and_b16 v10.l, v5.l, 63
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, v5.h, 1 clamp
; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.h, v8.l
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, v9.l, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v7.l
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.h, v7.l, 63
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, v3.h, 1
-; GFX1200-NEXT: v_and_b16 v8.h, v8.l, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v7.l
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.h, v10.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, v9.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
+; GFX1200-NEXT: v_and_b16 v10.l, v7.l, 1
+; GFX1200-NEXT: v_sub_nc_u16 v12.h, v9.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v11.l, v11.l, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, v12.l, v10.l
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, v12.h, 1
+; GFX1200-NEXT: v_and_b16 v11.l, v10.h, v11.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v10.l, v10.l, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v11.l
+; GFX1200-NEXT: v_and_b16 v5.h, v11.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v11.l, v9.l, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.h, v10.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v11.l, -1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v3.h, v3.h, v8.h
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v10.l
-; GFX1200-NEXT: v_and_b16 v6.h, v8.h, v6.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v9.h, v8.l, v10.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_and_b16 v13.l, v8.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s3
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v9.l, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v3.l, v3.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v9.h, v11.l, 1
+; GFX1200-NEXT: v_or_b16 v5.h, v12.l, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v2.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v13.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.l
; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v10.l
-; GFX1200-NEXT: v_and_b16 v6.h, v5.h, 1
-; GFX1200-NEXT: v_and_b16 v9.l, v8.l, 1
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v12.h, v8.l
+; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v8.h, v5.l
; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s2
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v4.l
-; GFX1200-NEXT: v_or_b16 v6.h, v11.l, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v4.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
-; GFX1200-NEXT: v_or_b16 v9.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v6.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, s3
-; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v4.h, s1
-; GFX1200-NEXT: v_min_u16 v4.h, v6.l, 15
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v6.h
; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.h
-; GFX1200-NEXT: v_and_b16 v9.h, v6.h, 63
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v4.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, vcc_lo
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v4.h, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.l
+; GFX1200-NEXT: v_min_u16 v4.l, v9.l, 15
+; GFX1200-NEXT: v_or_b16 v8.h, v7.h, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
-; GFX1200-NEXT: v_lshlrev_b16 v5.l, 7, v14.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s1
; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_or_b16 v7.h, v5.l, v8.l
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
-; GFX1200-NEXT: v_or_b16 v3.h, v7.h, v3.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v8.h
-; GFX1200-NEXT: v_and_b16 v4.l, 0xff, v4.l
-; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v10.l, 1
+; GFX1200-NEXT: v_sub_nc_u16 v9.l, v4.l, 1 clamp
+; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.h, v2.h
+; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v11.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v10.l
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_and_b16 v10.l, 0x3ff, v8.h
+; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 8, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_or_b16 v11.h, 0x400, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s0
+; GFX1200-NEXT: v_and_b16 v8.l, 0x80, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, 3, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v5.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.h, v11.h, v10.h
+; GFX1200-NEXT: v_cndmask_b16 v7.l, v7.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v9.h, v8.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s2
+; GFX1200-NEXT: v_or_b16 v11.l, v8.l, v11.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
+; GFX1200-NEXT: v_or_b16 v7.l, v9.h, v7.l
+; GFX1200-NEXT: v_and_b16 v5.h, v8.h, 63
+; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v5.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v4.l, v11.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v3.l, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
-; GFX1200-NEXT: v_and_b16 v9.h, v7.h, 1
-; GFX1200-NEXT: v_or_b16 v5.h, v8.h, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v7.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v7.l, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v3.h, v3.h
+; GFX1200-NEXT: v_or_b16 v5.h, v11.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v9.l, v11.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
-; GFX1200-NEXT: v_or_b16 v7.l, v11.l, v9.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v14.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v8.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v2.l
+; GFX1200-NEXT: v_and_b16 v3.h, v7.h, 1
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v10.l
+; GFX1200-NEXT: v_and_b16 v5.h, v7.l, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v4.h, s0
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v8.h
+; GFX1200-NEXT: v_or_b16 v3.h, v9.l, v3.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v5.h, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v9.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v7.l
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, vcc_lo
-; GFX1200-NEXT: v_min_u16 v4.h, v5.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v6.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v7.h, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v14.l
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v13.l, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.l, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0x7f, v5.l, s1
+; GFX1200-NEXT: v_and_b16 v3.h, v7.l, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.l, v5.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v4.h, 1 clamp
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.h, v3.h
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_and_b16 v10.h, v6.l, 63
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v4.h, v8.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_and_b16 v8.l, v8.h, v8.l
; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v4.h, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_and_b16 v11.h, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
+; GFX1200-NEXT: v_and_b16 v10.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
+; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.h, 3, v6.h
+; GFX1200-NEXT: v_or_b16 v9.h, v10.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v10.h, v12.l, v10.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
+; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v11.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.h, v1.h
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
-; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v1.l
-; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.h
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v10.l
-; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v7.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v11.l
-; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v5.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.l
-; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v6.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v6.l
+; GFX1200-NEXT: v_or_b16 v5.h, v9.h, v5.h
+; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v8.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.h, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v9.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v7.l, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, v6.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v2
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v9.l, v7.l
-; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 6
-; GFX1200-NEXT: v_and_b16 v8.h, v9.l, v8.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v2.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v2.h
-; GFX1200-NEXT: v_and_b16 v2.h, v6.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s0
+; GFX1200-NEXT: v_min_u16 v5.h, v6.l, 15
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.l, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v5.h, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, 8, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v10.l, s0
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
+; GFX1200-NEXT: v_and_b16 v9.l, 0x80, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v7.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, 3, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s0
+; GFX1200-NEXT: v_and_b16 v8.l, v10.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s1
+; GFX1200-NEXT: v_or_b16 v9.h, v9.l, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, v10.h, 1
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v4.h
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, 63
+; GFX1200-NEXT: v_or_b16 v6.l, v9.h, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v2.l, v7.l, v5.h
-; GFX1200-NEXT: v_and_b16 v5.h, v10.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v11.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0x7f, v5.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v10.l
+; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v8.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v1.l
+; GFX1200-NEXT: v_and_b16 v7.h, v4.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
-; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v5.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v13.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.l
-; GFX1200-NEXT: v_and_b16 v3.l, v8.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v13.l
-; GFX1200-NEXT: v_or_b16 v3.l, v9.l, v3.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s1
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v6.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_and_b16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.l
; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
-; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 63
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.l, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v1.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s0
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 31, v1
+; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v11.h, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_and_b16 v9.l, v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v6.l
-; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, v9.l
-; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v9.l, s0
+; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v10.h, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0xff, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v6.l
+; GFX1200-NEXT: v_and_b16 v2.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.l, v7.l, 1
+; GFX1200-NEXT: v_and_b16 v9.h, v6.h, 63
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.l
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v2.l, 7, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v7.h
+; GFX1200-NEXT: v_and_b16 v6.l, v7.h, v6.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s0
+; GFX1200-NEXT: v_and_b16 v9.h, v10.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.h, v10.l
+; GFX1200-NEXT: v_and_b16 v8.h, v2.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.h, 7, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_or_b16 v7.h, v11.h, v9.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v0.h
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, 6
-; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v10.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v7.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v9.l
-; GFX1200-NEXT: v_or_b16 v6.h, v12.l, v11.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v5.h, v9.h, v5.h
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, v6.h
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, 2, v9.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_or_b16 v5.h, v11.h, v8.h
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.h
+; GFX1200-NEXT: v_min_u16 v6.h, v6.h, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.l
+; GFX1200-NEXT: v_or_b16 v4.l, v5.h, v4.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v6.h, 1 clamp
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v6.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v0.l
-; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v3.l, v2.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_min_u16 v5.h, v8.l, 15
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v4.h, s1
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v5.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v12.l
+; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.h, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v9.h, s0
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v14.l, v14.l
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v10.l, 0, 8, s2
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.l, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v8.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
+; GFX1200-NEXT: v_or_b16 v10.l, v9.h, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v11.h, s1
+; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v4.h, 3, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v11.l, v6.h, v10.h
+; GFX1200-NEXT: v_and_b16 v8.l, v10.h, v8.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.h, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_or_b16 v4.h, v9.h, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, 3, v7.l
-; GFX1200-NEXT: v_and_b16 v3.l, v10.h, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v5.h, v10.h
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.l
-; GFX1200-NEXT: v_and_b16 v9.h, v8.l, 1
-; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v11.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
-; GFX1200-NEXT: v_and_b16 v4.h, v9.l, 1
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.l, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
-; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, s1
+; GFX1200-NEXT: v_or_b16 v2.l, v4.h, v2.l
+; GFX1200-NEXT: v_and_b16 v4.h, v11.l, 1
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v6.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v4.l, 8, v4.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v8.l
+; GFX1200-NEXT: v_or_b16 v4.h, v6.l, v4.h
; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.h, v10.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v10.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v1.h, v4.h, 15
-; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
-; GFX1200-NEXT: v_and_b16 v4.h, v7.h, 63
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.l, v9.h, s0
+; GFX1200-NEXT: v_min_u16 v2.l, v5.h, 15
+; GFX1200-NEXT: v_and_b16 v5.h, v7.h, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v0.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v2.l, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v5.h
+; GFX1200-NEXT: v_and_b16 v9.h, v7.l, 1
; GFX1200-NEXT: v_lshrrev_b16 v7.h, 6, v7.h
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v1.h, 1 clamp
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v4.h
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
+; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v5.h
; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v1.h, v10.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v9.h, v12.l, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v11.h, v2.l, v10.h
; GFX1200-NEXT: v_and_b16 v8.h, v10.h, v8.h
-; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
+; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 1
; GFX1200-NEXT: v_and_b16 v7.h, v7.h, v9.h
; GFX1200-NEXT: v_and_b16 v9.h, v11.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v14.l
; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v1.h
-; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v3.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v7.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v13.l, v13.l
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s4
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, v7.h, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s2
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v10.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s2
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v10.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v1.l, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, v4.h, s0
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.l, v7.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v1.l, v11.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v1.h, s2
+; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v4.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v1.l
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v7.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 7, v4.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v0
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.h, s3
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, s4
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v11.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, 0, s4
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, s3
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s5
+; GFX1200-NEXT: v_mov_b16_e32 v2.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v0
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v8.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v9.l, v2.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 8, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, 6
+; GFX1200-NEXT: v_and_b16 v8.l, 0x80, v8.l
+; GFX1200-NEXT: v_or_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v9.l, 0, 8, s3
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s3
; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s5
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v7.l, 6
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v6.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s3
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v6.h
-; GFX1200-NEXT: v_or_b16 v7.l, v5.h, v7.l
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.l
-; GFX1200-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v6.h
-; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v7.h
-; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v5.l
-; GFX1200-NEXT: v_or_b16 v1.h, v8.l, v1.h
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v2.h
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.l, v0.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v3.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.h, v1.h, s3
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.h, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v8.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v2.l, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_or_b16 v9.l, v8.l, v9.l
+; GFX1200-NEXT: v_or_b16 v9.h, v8.l, v9.h
+; GFX1200-NEXT: v_or_b16 v8.h, v7.h, v8.h
+; GFX1200-NEXT: v_or_b16 v1.l, v6.h, v1.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v2.l
+; GFX1200-NEXT: v_or_b16 v2.l, v9.l, v5.h
+; GFX1200-NEXT: v_or_b16 v4.h, v9.h, v4.h
+; GFX1200-NEXT: v_or_b16 v6.l, v8.h, v6.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v7.l
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v6.l, v1.l, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v0.h
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.h, v2.l, s3
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v7.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.h, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v2.l, v8.l, s1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v0.l, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v2.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v4.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.h, 8, v3.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s0
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, s1
+; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v4.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v6.l, v1.l, v1.h
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v6.l, v0.l, v1.h
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
; GFX1200-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX1200-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX1200-NEXT: s_setpc_b64 s[30:31]
@@ -3251,447 +3229,440 @@ define <5 x i8> @to_bf8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v2
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v2
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.l, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v2.l
; GFX1200-NEXT: v_sub_nc_u16 v4.h, -5, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v3.h
-; GFX1200-NEXT: v_and_b16 v5.h, 0x7f, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v12.l
-; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x7f, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, -5, v5.l
; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, -5, v6.h
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v4.h, 1 clamp
-; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 8, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v4.h, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_and_b16 v11.l, v6.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_min_u16 v8.l, v8.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, v8.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v4.h, v9.h
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v10.l, v10.l, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, v8.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_and_b16 v10.l, v9.h, v10.l
+; GFX1200-NEXT: v_and_b16 v11.l, v9.l, 1
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v11.h, v4.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 8, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v8.h, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v8.l, v10.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.h, v5.l, 1
-; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
-; GFX1200-NEXT: v_and_b16 v9.h, 0x7f, v6.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.h
-; GFX1200-NEXT: v_and_b16 v8.l, v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v4.h
-; GFX1200-NEXT: v_and_b16 v4.h, v10.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v9.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.h
+; GFX1200-NEXT: v_and_b16 v6.l, v7.h, 1
; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v9.l, v10.h
-; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
-; GFX1200-NEXT: v_and_b16 v9.h, v5.l, 1
-; GFX1200-NEXT: v_cmp_class_f16_e64 s6, v2.l, 0x204
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v4.h, v10.h
+; GFX1200-NEXT: v_or_b16 v9.h, v12.l, v11.l
+; GFX1200-NEXT: v_add_nc_u16 v11.l, v11.h, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_and_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_or_b16 v4.h, v8.l, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v7.h, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v11.l
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
-; GFX1200-NEXT: v_and_b16 v4.h, v7.l, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v8.l, -1
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_and_b16 v8.h, v8.h, v9.h
+; GFX1200-NEXT: v_and_b16 v9.h, v10.h, v11.l
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v14.l
+; GFX1200-NEXT: v_or_b16 v6.l, v12.l, v6.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, v8.h, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_and_b16 v4.l, v4.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, v10.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v9.l, v8.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 14
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
-; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
-; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
-; GFX1200-NEXT: v_or_b16 v8.l, v8.l, v9.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v3.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 30, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v10.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 2, v3.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.h, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.l, v9.h
-; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v4.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x7c, v6.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v8.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 2, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v4.l
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s4
-; GFX1200-NEXT: v_and_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v7.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v2
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v5.l, v3.l
-; GFX1200-NEXT: s_and_b32 s0, s3, s2
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.h, v7.l
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s5, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, -5, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 14
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v4.l, 7, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, vcc_lo
+; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 30, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 4, s0
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 2, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s6
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
-; GFX1200-NEXT: v_or_b16 v5.h, v4.l, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
-; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v2.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7e, v3.h, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
-; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v6.l
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v7.l, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v6.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v2.h
-; GFX1200-NEXT: v_or_b16 v2.h, 0x400, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, -1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v3.l, 0x7f, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v6.l, v2.h, v6.l
-; GFX1200-NEXT: s_and_b32 s0, s1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s2
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v6.l
+; GFX1200-NEXT: v_or_b16 v6.l, v6.h, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v7.h, v8.l, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.l, v6.h, v8.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s1
+; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v3.l
+; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v7.h
+; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v10.l, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.l, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v5.h
+; GFX1200-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v3.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s2, s0
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
-; GFX1200-NEXT: v_and_b16 v6.l, v5.h, 1
-; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: s_or_b32 s0, s3, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v2.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v1.l
-; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.l, v8.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v4.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v13.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v8.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v3.l, -5, v6.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
-; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7e, v2.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v7.h, v2.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
-; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v7.l, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.h
; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 14
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 2, v4.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 4, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v9.h, v7.l, v9.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
-; GFX1200-NEXT: v_and_b16 v7.h, v5.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v3.l, v8.h
-; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v6.h, s0
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 2, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v1.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v6.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v7.h, v5.l, v7.h
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
+; GFX1200-NEXT: v_and_b16 v9.l, 0x3ff, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, v8.h, 1
; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v7.h
+; GFX1200-NEXT: v_or_b16 v3.l, v7.h, v3.l
+; GFX1200-NEXT: v_or_b16 v6.h, v6.h, v4.l
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v9.h, v9.h, -1
+; GFX1200-NEXT: v_and_b16 v10.l, 0x7f, v8.l
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v2.h, 0x204
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v6.h, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 30, v4.h
+; GFX1200-NEXT: v_and_b16 v6.h, v7.h, v9.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v10.h, v9.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v7.l, s0
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v6.l, v7.h
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s0, 30, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v8.h, v7.h
+; GFX1200-NEXT: v_or_b16 v7.h, 0x7c, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v8.l, v2.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v7.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
-; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v10.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v6.h, v9.h
-; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v7.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 3, v4.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v5.l, s0
-; GFX1200-NEXT: s_and_b32 s0, s1, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3
+; GFX1200-NEXT: v_and_b16 v4.l, v9.l, 1
+; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v4.l, v11.l, v4.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s2, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: s_or_b32 s1, s1, s0
+; GFX1200-NEXT: v_and_b16 v6.h, v8.l, v6.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.h, v2.h
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s3
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v7.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v3.l, v7.h, s1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v1.l
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v6.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s2, v1.l, 0x204
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, 14
-; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, 4, s0
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7e, v3.h, s0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0, v4.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s1
+; GFX1200-NEXT: v_min_u16 v5.l, v6.l, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v9.l, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v10.h, 0x7f, v6.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v7.l
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, s2
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, v6.l, 1 clamp
-; GFX1200-NEXT: v_or_b16 v5.l, v6.h, v5.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
-; GFX1200-NEXT: v_or_b16 v7.l, v6.h, v7.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.l, 1
-; GFX1200-NEXT: v_or_b16 v3.l, v5.l, v3.l
-; GFX1200-NEXT: s_and_b32 s1, s1, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s3, v13.l, 0x204
-; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v4.l
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 4, s0
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 8, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 14
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.h
+; GFX1200-NEXT: v_and_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 2, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, 1
+; GFX1200-NEXT: v_or_b16 v9.h, v9.l, v9.h
+; GFX1200-NEXT: v_or_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_and_b16 v7.l, v10.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v9.h, v9.h, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v7.l, v12.l, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v10.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
+; GFX1200-NEXT: v_cmp_class_f16_e64 s1, v2.l, 0x204
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.l, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v9.h, v4.l, vcc_lo
+; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v8.l, v6.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s2, 30, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 30, v5.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v5.l, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 30, v2.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, v6.l, v7.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
-; GFX1200-NEXT: v_or_b16 v4.l, 0x7c, v6.h
-; GFX1200-NEXT: v_and_b16 v4.h, v2.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0, v4.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v7.h, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v4.h
+; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v10.h, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, -5, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7e, v2.h, s0
+; GFX1200-NEXT: s_and_b32 s1, s2, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 8, v1.l
+; GFX1200-NEXT: v_min_u16 v6.h, v6.h, 15
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s1
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v1.l
+; GFX1200-NEXT: s_or_b32 s1, s3, s1
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 4, s0
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 14
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v3.l, v4.l, s0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v12.l
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v13.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v1.h
+; GFX1200-NEXT: v_and_b16 v6.l, 0x80, v6.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v0.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 2, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v6.h, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v9.l, s1
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v7.l, v6.l, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v7.h, v6.l, v7.h
+; GFX1200-NEXT: v_and_b16 v9.l, 0x3ff, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, v8.h, 1
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v1.h, 0x204
+; GFX1200-NEXT: v_or_b16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v5.l
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v9.h, v9.h, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v3.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s0, 30, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 30, v3.l
+; GFX1200-NEXT: v_and_b16 v4.h, v7.h, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, v6.h, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v7.l, v4.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v5.l
+; GFX1200-NEXT: v_and_b16 v9.h, 0x7f, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v4.h
+; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v6.l
+; GFX1200-NEXT: v_and_b16 v5.l, v3.l, 1
+; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v1.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s2
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: s_or_b32 s0, s1, s0
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v4.h, s0
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v1.l
+; GFX1200-NEXT: v_cmp_class_f16_e64 s3, v1.l, 0x204
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7e, v1.h, vcc_lo
-; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.l, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, -5, v3.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.h, v12.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7e, v2.l, vcc_lo
+; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v8.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 8, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, -5, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
-; GFX1200-NEXT: v_min_u16 v5.l, v8.l, 15
-; GFX1200-NEXT: v_and_b16 v6.l, v7.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, v5.l, 1 clamp
-; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, v9.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
-; GFX1200-NEXT: v_and_b16 v4.h, v7.h, v6.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x7f, v8.h
-; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v5.l, v7.l, v5.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.h, 1
+; GFX1200-NEXT: v_min_u16 v6.h, v8.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.h, v0.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v6.l, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s0
+; GFX1200-NEXT: v_or_b16 v7.l, v9.l, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, v6.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v9.l, 0x3ff, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, s3
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v5.l
+; GFX1200-NEXT: v_and_b16 v5.l, v8.l, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v10.l, v9.h, 1
+; GFX1200-NEXT: v_and_b16 v8.l, 0x7f, v8.h
+; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v9.l
; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_and_b16 v6.h, v6.l, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
-; GFX1200-NEXT: v_and_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v7.h, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v10.l, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 8, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v6.h, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
+; GFX1200-NEXT: v_and_b16 v7.l, v6.l, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v6.h
-; GFX1200-NEXT: v_and_b16 v6.h, v7.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v9.l, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v5.l
+; GFX1200-NEXT: v_and_b16 v9.l, v7.h, 1
+; GFX1200-NEXT: v_and_b16 v10.h, v8.l, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v9.h, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v11.l
-; GFX1200-NEXT: v_and_b16 v5.h, v8.h, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v0.l
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v5.h
-; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 14
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v4.h
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s1
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v11.l
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v7.l
+; GFX1200-NEXT: v_and_b16 v5.h, v8.h, v9.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v0
+; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v10.h
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 14
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.h, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v9.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v4.h
; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v6.h
-; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 2, v4.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s5, 30, v4.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s5, 30, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v4.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, v6.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v0
-; GFX1200-NEXT: v_or_b16 v6.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s6, 30, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v8.h
+; GFX1200-NEXT: v_or_b16 v7.l, v6.h, v7.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: v_or_b16 v1.l, v7.h, v3.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v4.l, v9.l
+; GFX1200-NEXT: v_or_b16 v4.l, v7.l, v5.l
; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v6.l
-; GFX1200-NEXT: v_lshlrev_b16 v4.h, 7, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v0.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s6, 30, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 14
; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
-; GFX1200-NEXT: v_add_nc_u16 v0.h, v3.l, 14
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, 4, s1
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v6.l, 0, s1
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, 4, s1
+; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v6.l, 0, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 2, v3.l
; GFX1200-NEXT: s_and_b32 s1, s5, s4
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v0.h
-; GFX1200-NEXT: v_or_b16 v3.l, v4.h, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s3
+; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v5.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-NEXT: s_or_b32 s5, s6, s1
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v0.h
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v0.h
-; GFX1200-NEXT: v_or_b16 v6.l, v4.h, v7.l
-; GFX1200-NEXT: v_or_b16 v3.l, v3.l, v4.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v13.l, v13.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 30, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v4.l, v6.l, v5.h
-; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v5.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7e, v1.l, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v4.l, v3.l, s1
+; GFX1200-NEXT: v_or_b16 v6.l, v7.l, v7.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
+; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.h
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v3.l
+; GFX1200-NEXT: v_or_b16 v4.h, v6.l, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 30, v3.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x7c, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7e, v1.h, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v0.h, 0x204
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v4.h, v4.l, s1
+; GFX1200-NEXT: v_or_b16 v4.l, 0x7c, v7.l
; GFX1200-NEXT: s_and_b32 s1, s3, s2
-; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.h
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.h, s5
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s5
; GFX1200-NEXT: s_or_b32 s2, s4, s1
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.l
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.h
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s2
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s2, 0, v12.l
-; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s2
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s2, 0, v0.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s1
-; GFX1200-NEXT: v_cmp_class_f16_e64 s1, v12.l, 0x204
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v4.h, s2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v2.h, v5.h, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v1.l
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, s1
+; GFX1200-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s2
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v0.l, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v3.l, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.l, v4.l, s1
+; GFX1200-NEXT: v_or_b16 v4.l, v2.h, v3.h
+; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7e, v4.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7e, v1.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7e, v0.h, s0
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_or_b32_e32 v6, 0x7e7e0000, v1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7e, v0.l, s0
-; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index aa6f54af57d162..365c938d8f6e64 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -614,12 +614,11 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
; GFX11-SDAG-TRUE16-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v1, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v1, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -693,13 +692,12 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v1, v0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v1, v1, v0
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1.h
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index cb64b3de060ff9..c80e3aaccabe6d 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -2467,24 +2467,23 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v1.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.l, s2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
@@ -2494,14 +2493,13 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v8
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v8
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
@@ -2511,14 +2509,14 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s2, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
@@ -2528,10 +2526,10 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v5.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v2.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.h, v1.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -2652,25 +2650,24 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v4.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.l, s2
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
@@ -2681,33 +2678,32 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v8
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v8
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s1
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
@@ -2718,11 +2714,11 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v5.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v2.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.h, v1.l, s1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
index 0785510b255099..10aa33b055a8a1 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
@@ -135,13 +135,11 @@ define <2 x half> @test_fmax_legacy_ugt_v2f16(<2 x half> %a, <2 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v2f16:
@@ -259,16 +257,13 @@ define <3 x half> @test_fmax_legacy_ugt_v3f16(<3 x half> %a, <3 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v3f16:
@@ -415,20 +410,16 @@ define <4 x half> @test_fmax_legacy_ugt_v4f16(<4 x half> %a, <4 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmax_legacy_ugt_v4f16:
@@ -647,28 +638,20 @@ define <8 x half> @test_fmax_legacy_ugt_v8f16(<8 x half> %a, <8 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmax_legacy_ugt_v8f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v9.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v11.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v13.l, v12.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, v0.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v15.l, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s4, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s1, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, v3.h, v7.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s3, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s4, v1.h, v5.h
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s5, v2.l, v6.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s6, v3.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v14.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
index 7638f32cc61ac3..5492ea5111fe99 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
@@ -197,35 +197,34 @@ define <2 x bfloat> @v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum(<2 x bfloat
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e64 s0, v2, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v3.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v0.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, s0
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 2.0, v3
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 4.0, v3
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4080, v1.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4080, v0.l, s0
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
%max = call <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %a, <2 x bfloat> splat (bfloat 2.0))
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index da7f46a2a06137..2e9c5a848a8ad5 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -2472,24 +2472,23 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v4.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v1.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.l, s2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
@@ -2499,14 +2498,13 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v8
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v8
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
@@ -2516,14 +2514,14 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s2, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-SDAG-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
@@ -2533,10 +2531,10 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v5.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v2.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.h, v1.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -2657,25 +2655,24 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v4.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v1.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.l, s2
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
@@ -2686,33 +2683,32 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v8
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v8
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX12-SDAG-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s1
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v4.l, v3.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
@@ -2723,11 +2719,11 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v5.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v2.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.h, v1.l, s1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
index c8f4d72abc2949..c88c3bcae96cb3 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
@@ -136,13 +136,11 @@ define <2 x half> @test_fmin_legacy_ule_v2f16(<2 x half> %a, <2 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v2f16:
@@ -260,16 +258,13 @@ define <3 x half> @test_fmin_legacy_ule_v3f16(<3 x half> %a, <3 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v3f16:
@@ -416,20 +411,16 @@ define <4 x half> @test_fmin_legacy_ule_v4f16(<4 x half> %a, <4 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_fmin_legacy_ule_v4f16:
@@ -648,28 +639,20 @@ define <8 x half> @test_fmin_legacy_ule_v8f16(<8 x half> %a, <8 x half> %b) #0 {
; GFX11-TRUE16-LABEL: test_fmin_legacy_ule_v8f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v9.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v11.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v13.l, v12.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s3, v0.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v15.l, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s4, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v3.h, v7.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s3, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s4, v1.h, v5.h
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s5, v2.l, v6.l
; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e64 s6, v3.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v12.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v14.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
index 1a3bd8b68f9644..8410cd5d0e362e 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
@@ -245,15 +245,12 @@ define <2 x i16> @fneg_xor_select_v2i16(<2 x i1> %cond, <2 x i16> %arg0, <2 x i1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -766,28 +763,24 @@ define <2 x half> @select_fneg_select_v2f16(<2 x i1> %cond0, <2 x i1> %cond1, <2
; GFX11-TRUE16-LABEL: select_fneg_select_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_select_v2f16:
@@ -877,28 +870,24 @@ define <2 x i16> @select_fneg_xor_select_v2i16(<2 x i1> %cond0, <2 x i1> %cond1,
; GFX11-TRUE16-LABEL: select_fneg_xor_select_v2i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80008000, v4
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v3.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v5.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_xor_select_v2i16:
@@ -1057,9 +1046,8 @@ define float @cospiD_pattern0_half(i16 %arg, float %arg1, float %arg2) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.h
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, v1, v2, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x8000, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v2.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_xor_b16 v0.h, v0.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: cospiD_pattern0_half:
diff --git a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
index 0507e926ec6fe6..c32ff26c1c8962 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -214,27 +214,24 @@ define <8 x half> @fmul_pow2_8xhalf(<8 x i16> %i) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v3, v3, 1 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, v2, 1 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, v1, 1 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v5.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v0, 1 op_sel_hi:[1,0]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.h, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v5.h, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v2.l, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v3.l, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, 0x7000, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v1, 0x7000, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v2, 0x7000, v5 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v3, 0x7000, v4 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v2, 0x7000, v2 op_sel_hi:[0,1]
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v3, 0x7000, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fmul_pow2_8xhalf:
@@ -316,20 +313,14 @@ define <8 x half> @fmul_pow2_ldexp_8xhalf(<8 x i16> %i) {
; GFX11-TRUE16-LABEL: fmul_pow2_ldexp_8xhalf:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v4.l, 0x7000, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.l, 0x7000, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v4.h, 0x7000, v5.l
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, 0x7000, v1.l
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.h, 0x7000, v2.l
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.h, 0x7000, v3.h
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v2.h, 0x7000, v2.h
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, 0x7000, v1.h
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, 0x7000, v0.h
; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, 0x7000, v0.l
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, 0x7000, v6.l
-; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, 0x7000, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, 0x7000, v1.l
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v2.l, 0x7000, v2.l
+; GFX11-TRUE16-NEXT: v_ldexp_f16_e32 v3.l, 0x7000, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: fmul_pow2_ldexp_8xhalf:
@@ -1091,10 +1082,9 @@ define <2 x half> @fmul_pow_shl_cnt_vec_fail_to_large(<2 x i16> %cnt) nounwind {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, v0, 2 op_sel_hi:[1,0]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, 0x4b80, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fpow.ll b/llvm/test/CodeGen/AMDGPU/fpow.ll
index b12bd73c8287a5..0de8e7db0f3743 100644
--- a/llvm/test/CodeGen/AMDGPU/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpow.ll
@@ -316,20 +316,17 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-LABEL: v_pow_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -464,20 +461,17 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -613,20 +607,17 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_rhs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v1.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
@@ -763,20 +754,17 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) {
; GFX11-TRUE16-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v1.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v2.l
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, -v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_log_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v2, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v1, v2
; GFX11-TRUE16-NEXT: v_exp_f32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index d86969155ad957..f1ae8af89ca765 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2560,15 +2560,13 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v0.h, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2598,15 +2596,13 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v0.h, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2738,25 +2734,23 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xff80
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xff80
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v2.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v2.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v0.h, v2.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v2.l, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v2.l, v1.h, 0x7f
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
@@ -2801,25 +2795,23 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xff80
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0xff80
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v2.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v2.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v0.h, v2.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v2.l, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v3.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v2.l, v1.h, 0x7f
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
@@ -2931,12 +2923,10 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v4f16_v4i16:
@@ -2963,12 +2953,10 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v4f16_v4i16:
@@ -3049,16 +3037,14 @@ define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i32_duplicate:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v4
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v4f16_v4i32_duplicate:
@@ -3087,16 +3073,14 @@ define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v4
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v2
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v3
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v4f16_v4i32_duplicate:
@@ -3197,19 +3181,17 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v4f16_v4i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v1
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3243,19 +3225,17 @@ define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v2
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v3
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v1
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4180,26 +4160,22 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.h, -1, 0
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v4.l, v4.l, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i16 v6.l, v0.h, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v4.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i16 v4.l, v0.h, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i16 v5.l, v2.h, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i16 v6.l, v4.h, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i16 v7.l, v3.h, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4240,26 +4216,22 @@ define <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v1.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.h, -1, 0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v8.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v4.l, v4.l, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i16 v6.l, v0.h, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, -1, 0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v4.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v0.h, -1, 0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v4.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v1.h, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i16 v4.l, v0.h, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i16 v5.l, v2.h, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i16 v6.l, v4.h, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i16 v7.l, v3.h, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4481,45 +4453,41 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0xff80
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v5.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v3.h, v3.h, v4.l, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v1.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v2.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v7.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v3.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v1.h
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v2.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v5.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v2.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v0.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v4.l, 0x7f
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v0.h, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v1.h, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
@@ -4588,45 +4556,41 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0xff80
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v5.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v2.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v3.h, v3.h, v4.l, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v1.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v2.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v7.l
-; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v3.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v1.h
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v2.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v5.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.l, v0.h
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX12-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_or_b16 v6.h, v3.l, v3.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v2.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v0.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v4.l, 0x7f
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
-; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v6.l, v0.h, v1.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
+; GFX12-TRUE16-NEXT: v_or_b16 v6.l, v1.h, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
@@ -4805,15 +4769,11 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v7.l
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
@@ -4851,15 +4811,11 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, v7.l
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
@@ -4993,28 +4949,23 @@ define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i32_duplicate:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v4
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v6
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v5
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v7
; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v9
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v5, v2
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v7, v9
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v8f16_v8i32_duplicate:
@@ -5055,28 +5006,23 @@ define <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v4
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v9, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v6
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v7, v7
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v1
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v5
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v7
; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v4
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v8
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v9
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v5, v2
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v6
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v7, v9
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v8f16_v8i32_duplicate:
@@ -5246,35 +5192,31 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_signed_v8f16_v8i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v17, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v6
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v16, 31, v17
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v7
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v2
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v3
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v17 :: v_dual_mov_b32 v3, v16
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_v8f16_v8i64:
@@ -5322,35 +5264,31 @@ define <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v16, v4
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v5
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v8
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v17, 31, v16
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v4
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v2
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v3
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
-; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v8, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v17, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v4
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v6
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v16, 31, v17
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v6, v7
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v8, v8
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v10, v2
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v12, v9
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v14, v3
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v13, 31, v12
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v16 :: v_dual_mov_b32 v3, v17
+; GFX12-TRUE16-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v17 :: v_dual_mov_b32 v3, v16
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_v8f16_v8i64:
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 830e14ec13ad15..2260c4146bd010 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2366,15 +2366,13 @@ define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
; GFX11-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
-; GFX11-TRUE16-NEXT: v_min_u16 v2.l, v0.h, 1
-; GFX11-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 1
+; GFX11-TRUE16-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX11-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX11-TRUE16-NEXT: v_min_u16 v3.l, v1.h, 1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2404,15 +2402,13 @@ define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
; GFX12-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
-; GFX12-TRUE16-NEXT: v_min_u16 v2.l, v0.h, 1
-; GFX12-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 1
+; GFX12-TRUE16-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX12-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX12-TRUE16-NEXT: v_min_u16 v3.l, v1.h, 1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2530,22 +2526,20 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
@@ -2586,22 +2580,20 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
@@ -2706,12 +2698,10 @@ define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v4f16_v4i16:
@@ -2738,12 +2728,10 @@ define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v4f16_v4i16:
@@ -2824,16 +2812,14 @@ define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i32_duplicate:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v4
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v4f16_v4i32_duplicate:
@@ -2862,16 +2848,14 @@ define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v1
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v4
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v3
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v5
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v4f16_v4i32_duplicate:
@@ -2972,18 +2956,16 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v4f16_v4i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -3018,18 +3000,16 @@ define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v3
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -3893,26 +3873,22 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, v2.l, 1
-; GFX11-TRUE16-NEXT: v_min_u16 v2.l, v2.h, 1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v8.l
-; GFX11-TRUE16-NEXT: v_min_u16 v4.l, v4.l, 1
-; GFX11-TRUE16-NEXT: v_min_u16 v6.l, v0.h, 1
-; GFX11-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v4.h
+; GFX11-TRUE16-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
+; GFX11-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX11-TRUE16-NEXT: v_min_u16 v3.l, v1.h, 1
+; GFX11-TRUE16-NEXT: v_min_u16 v4.l, v0.h, 1
; GFX11-TRUE16-NEXT: v_min_u16 v5.l, v2.h, 1
+; GFX11-TRUE16-NEXT: v_min_u16 v6.l, v4.h, 1
; GFX11-TRUE16-NEXT: v_min_u16 v7.l, v3.h, 1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3953,26 +3929,22 @@ define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v1.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX12-TRUE16-NEXT: v_min_u16 v0.l, v2.l, 1
-; GFX12-TRUE16-NEXT: v_min_u16 v2.l, v2.h, 1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v8.l
-; GFX12-TRUE16-NEXT: v_min_u16 v4.l, v4.l, 1
-; GFX12-TRUE16-NEXT: v_min_u16 v6.l, v0.h, 1
-; GFX12-TRUE16-NEXT: v_min_u16 v1.l, v1.l, 1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v4.h
+; GFX12-TRUE16-NEXT: v_min_u16 v1.l, v0.h, 1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v4.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.h, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX12-TRUE16-NEXT: v_min_u16 v0.l, v0.l, 1
+; GFX12-TRUE16-NEXT: v_min_u16 v2.l, v2.l, 1
; GFX12-TRUE16-NEXT: v_min_u16 v3.l, v1.h, 1
+; GFX12-TRUE16-NEXT: v_min_u16 v4.l, v0.h, 1
; GFX12-TRUE16-NEXT: v_min_u16 v5.l, v2.h, 1
+; GFX12-TRUE16-NEXT: v_min_u16 v6.l, v4.h, 1
; GFX12-TRUE16-NEXT: v_min_u16 v7.l, v3.h, 1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4173,41 +4145,37 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v6.l
-; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v2.h
; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v4.l
-; GFX11-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_min_u16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_min_u16 v3.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v2.l
-; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX11-TRUE16-NEXT: v_min_u16 v4.l, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT: v_min_u16 v4.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v4.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v3.l, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v4.h, v1.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v6
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l
@@ -4269,41 +4237,37 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v2.l
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v6.l
-; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v2.h
; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_min_u16 v3.h, 0xff, v3.h
+; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
; GFX12-TRUE16-NEXT: v_min_u16 v3.l, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v8.h, v1.h, v0.h
-; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v2.l
-; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v3.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX12-TRUE16-NEXT: v_min_u16 v4.l, 0xff, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
+; GFX12-TRUE16-NEXT: v_min_u16 v4.h, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v8.h, v3.l, v3.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v4.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v8.l, v3.l, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_or_b16 v8.l, v4.h, v1.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[7:8]
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v6
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l
@@ -4472,15 +4436,11 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v7.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v2.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v3.l
@@ -4518,15 +4478,11 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v7.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v2.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v3.l
@@ -4660,28 +4616,23 @@ define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i32_duplicate:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v4
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v6
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v5
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v7
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v9
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v8f16_v8i32_duplicate:
@@ -4722,28 +4673,23 @@ define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v6.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v4
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v9, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v6
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v5
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v7
; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v8
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v7, v9
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v8f16_v8i32_duplicate:
@@ -4909,27 +4855,23 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v7.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.h
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v6
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v3
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v5
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, 0
@@ -4983,27 +4925,23 @@ define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v0.h
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v6
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v7.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v6, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v7, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v5, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v3
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v6
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.h
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v9, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.h
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v4
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v6
; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v7
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v5
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v8, v7
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v10, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v12, v9
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v14, v3
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, v5
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0
diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll
index c56f682c9b6ac0..210e7cc8c7a1ce 100644
--- a/llvm/test/CodeGen/AMDGPU/fract-match.ll
+++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll
@@ -66,6 +66,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -81,6 +82,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -92,6 +94,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -102,6 +105,7 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) writeonly captures(
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -248,7 +252,6 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; GFX6-IR-NEXT: [[COND6:%.*]] = select <3 x i1> [[CMPINF]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[COND]]
; GFX6-IR-NEXT: store <3 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; GFX6-IR-NEXT: ret <3 x float> [[COND6]]
-;
; IR-FRACT-LABEL: define <3 x float> @safe_math_fract_v3f32(
; IR-FRACT-SAME: <3 x float> [[X:%.*]], ptr addrspace(1) writeonly captures(none) [[IP:%.*]]) {
; IR-FRACT-NEXT: [[FLOOR:%.*]] = tail call <3 x float> @llvm.floor.v3f32(<3 x float> [[X]])
@@ -266,7 +269,6 @@ define <3 x float> @safe_math_fract_v3f32(<3 x float> %x, ptr addrspace(1) write
; IR-FRACT-NEXT: [[COND6:%.*]] = select <3 x i1> [[CMPINF]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[COND]]
; IR-FRACT-NEXT: store <3 x float> [[FLOOR]], ptr addrspace(1) [[IP]], align 4
; IR-FRACT-NEXT: ret <3 x float> [[COND6]]
-;
%floor = tail call <3 x float> @llvm.floor.v3f32(<3 x float> %x)
%sub = fsub <3 x float> %x, %floor
%min = tail call <3 x float> @llvm.minnum.v3f32(<3 x float> %sub, <3 x float> <float 0x3FEFFFFFE0000000, float poison, float 0x3FEFFFFFE0000000>)
@@ -316,6 +318,7 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_v2f32_const_splat_poison:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -339,6 +342,7 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_v2f32_const_splat_poison:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -358,6 +362,7 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[4:5], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_v2f32_const_splat_poison:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -376,6 +381,7 @@ define <2 x float> @safe_math_fract_v2f32_const_splat_poison(<2 x float> %x, ptr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_v2f32_const_splat_poison:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -458,6 +464,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swap:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -473,6 +480,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swap:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -484,6 +492,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swap:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -494,6 +503,7 @@ define float @safe_math_fract_f32_swap(float %x, ptr addrspace(1) writeonly capt
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swap:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -557,6 +567,7 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_noinf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -569,6 +580,7 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_noinf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -577,6 +589,7 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_noinf_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -584,6 +597,7 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) writeon
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: global_store_b32 v[1:2], v3, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_noinf_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -635,6 +649,7 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: no_nan_check_math_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -651,6 +666,7 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: no_nan_check_math_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -663,6 +679,7 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: no_nan_check_math_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -674,6 +691,7 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) writeonly c
; GFX11-NEXT: v_min_f32_e32 v4, 0x3f7fffff, v4
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: no_nan_check_math_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -723,21 +741,25 @@ define float @basic_fract_f32_nonans(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_nonans:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_nonans:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_nonans:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_nonans:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -770,6 +792,7 @@ define float @basic_fract_f32_flags_minnum(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_flags_minnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -777,6 +800,7 @@ define float @basic_fract_f32_flags_minnum(float %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_flags_minnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -784,6 +808,7 @@ define float @basic_fract_f32_flags_minnum(float %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_flags_minnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -792,6 +817,7 @@ define float @basic_fract_f32_flags_minnum(float %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_flags_minnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -833,21 +859,25 @@ define float @basic_fract_f32_flags_fsub(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_flags_fsub:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_flags_fsub:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_flags_fsub:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_flags_fsub:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -894,24 +924,28 @@ define <2 x float> @basic_fract_v2f32_nonans(<2 x float> nofpclass(nan) %x) {
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: v_min_f32_e32 v1, 0x3f7fffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_v2f32_nonans:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: v_fract_f32_e32 v1, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_v2f32_nonans:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: v_fract_f32_e32 v1, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_v2f32_nonans:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: v_fract_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_v2f32_nonans:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -961,6 +995,7 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_multi_use_fsub_nonans:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -974,6 +1009,7 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_multi_use_fsub_nonans:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -983,6 +1019,7 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_multi_use_fsub_nonans:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -992,6 +1029,7 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: global_store_b32 v[1:2], v3, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_multi_use_fsub_nonans:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1035,21 +1073,25 @@ define float @nnan_minnum_fract_f32(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_minnum_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_minnum_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_minnum_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_minnum_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1084,6 +1126,7 @@ define float @nnan_fsub_fract_f32(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_fsub_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1091,6 +1134,7 @@ define float @nnan_fsub_fract_f32(float %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_fsub_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1098,6 +1142,7 @@ define float @nnan_fsub_fract_f32(float %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_fsub_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1106,6 +1151,7 @@ define float @nnan_fsub_fract_f32(float %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_fsub_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1141,6 +1187,7 @@ define float @nnan_floor_fract_f32(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_floor_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1148,6 +1195,7 @@ define float @nnan_floor_fract_f32(float %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_floor_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1155,6 +1203,7 @@ define float @nnan_floor_fract_f32(float %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_floor_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1163,6 +1212,7 @@ define float @nnan_floor_fract_f32(float %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_floor_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1204,21 +1254,25 @@ define float @nnan_src_fract_f32(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_src_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_src_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_src_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_src_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1252,6 +1306,7 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7ffffe, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: not_fract_f32_wrong_const:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1259,6 +1314,7 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7ffffe, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: not_fract_f32_wrong_const:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1266,6 +1322,7 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7ffffe, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: not_fract_f32_wrong_const:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1274,6 +1331,7 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7ffffe, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: not_fract_f32_wrong_const:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1310,6 +1368,7 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: not_fract_f32_swapped_fsub:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1317,6 +1376,7 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: not_fract_f32_swapped_fsub:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1324,6 +1384,7 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: not_fract_f32_swapped_fsub:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1332,6 +1393,7 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v1, v0
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: not_fract_f32_swapped_fsub:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1368,6 +1430,7 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: not_fract_f32_not_floor:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1375,6 +1438,7 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: not_fract_f32_not_floor:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1382,6 +1446,7 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: not_fract_f32_not_floor:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1390,6 +1455,7 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: not_fract_f32_not_floor:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1426,6 +1492,7 @@ define float @not_fract_f32_different_floor(float %x, float %y) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: not_fract_f32_different_floor:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1433,6 +1500,7 @@ define float @not_fract_f32_different_floor(float %x, float %y) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: not_fract_f32_different_floor:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1440,6 +1508,7 @@ define float @not_fract_f32_different_floor(float %x, float %y) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: not_fract_f32_different_floor:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1448,6 +1517,7 @@ define float @not_fract_f32_different_floor(float %x, float %y) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: not_fract_f32_different_floor:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1484,6 +1554,7 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_max_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: not_fract_f32_maxnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1491,6 +1562,7 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_max_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: not_fract_f32_maxnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1498,6 +1570,7 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_max_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: not_fract_f32_maxnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1506,6 +1579,7 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_max_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: not_fract_f32_maxnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1540,6 +1614,7 @@ define float @fcmp_uno_check_is_nan_f32(float %x) {
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: fcmp_uno_check_is_nan_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1584,21 +1659,25 @@ define float @select_nan_fract_f32(float %x) {
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: select_nan_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: select_nan_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: select_nan_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: select_nan_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1643,21 +1722,25 @@ define float @commuted_select_nan_fract_f32(float %x) {
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: commuted_select_nan_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: commuted_select_nan_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: commuted_select_nan_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: commuted_select_nan_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1696,6 +1779,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: wrong_commuted_nan_select_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1705,6 +1789,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; GFX7-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: wrong_commuted_nan_select_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1714,6 +1799,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: wrong_commuted_nan_select_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1725,6 +1811,7 @@ define float @wrong_commuted_nan_select_f32(float %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: wrong_commuted_nan_select_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1786,6 +1873,7 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fe000, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f16_nonan:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1799,21 +1887,25 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fe000, v0
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f16_nonan:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f16_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-TRUE16-LABEL: basic_fract_f16_nonan:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-FAKE16-LABEL: basic_fract_f16_nonan:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_fract_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-TRUE16-LABEL: basic_fract_f16_nonan:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1823,6 +1915,7 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) {
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-FAKE16-LABEL: basic_fract_f16_nonan:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1892,6 +1985,7 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_v2f16_nonan:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1917,6 +2011,7 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_v2f16_nonan:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1924,14 +2019,14 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX8-NEXT: v_fract_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-TRUE16-LABEL: basic_fract_v2f16_nonan:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-FAKE16-LABEL: basic_fract_v2f16_nonan:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1941,6 +2036,7 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX11-FAKE16-NEXT: v_fract_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-TRUE16-LABEL: basic_fract_v2f16_nonan:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -1948,11 +2044,10 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.h, v0.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-FAKE16-LABEL: basic_fract_v2f16_nonan:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2004,21 +2099,25 @@ define double @basic_fract_f64_nanans(double nofpclass(nan) %x) {
; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
; GFX6-NEXT: v_min_f64 v[0:1], v[0:1], s[4:5]
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f64_nanans:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f64_e32 v[0:1], v[0:1]
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f64_nanans:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f64_e32 v[0:1], v[0:1]
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f64_nanans:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f64_e32 v[0:1], v[0:1]
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f64_nanans:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2087,6 +2186,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX6-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f16_noinf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2108,6 +2208,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f16_noinf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2116,6 +2217,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX8-NEXT: global_store_short v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-TRUE16-LABEL: safe_math_fract_f16_noinf_check:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2123,6 +2225,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: global_store_d16_hi_b16 v[1:2], v0, off
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-FAKE16-LABEL: safe_math_fract_f16_noinf_check:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2130,6 +2233,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX11-FAKE16-NEXT: v_fract_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: global_store_b16 v[1:2], v3, off
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-TRUE16-LABEL: safe_math_fract_f16_noinf_check:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2141,6 +2245,7 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) writeonly
; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: global_store_d16_hi_b16 v[1:2], v0, off
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-FAKE16-LABEL: safe_math_fract_f16_noinf_check:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2207,6 +2312,7 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) write
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f64_noinf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2219,6 +2325,7 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) write
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f64_noinf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2227,6 +2334,7 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) write
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[4:5], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f64_noinf_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2234,6 +2342,7 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) write
; GFX11-NEXT: v_fract_f64_e32 v[0:1], v[0:1]
; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f64_noinf_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2281,21 +2390,25 @@ define float @select_nan_fract_f32_flags_select(float %x) {
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: select_nan_fract_f32_flags_select:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: select_nan_fract_f32_flags_select:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: select_nan_fract_f32_flags_select:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: select_nan_fract_f32_flags_select:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2340,21 +2453,25 @@ define float @select_nan_fract_f32_flags_minnum(float %x) {
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: select_nan_fract_f32_flags_minnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: select_nan_fract_f32_flags_minnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: select_nan_fract_f32_flags_minnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: select_nan_fract_f32_flags_minnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2429,6 +2546,7 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_v2f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2448,6 +2566,7 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_v2f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2463,6 +2582,7 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[4:5], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_v2f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2477,6 +2597,7 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) write
; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_v2f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2565,6 +2686,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX6-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f64:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2582,6 +2704,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX7-NEXT: buffer_store_dwordx2 v[6:7], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f64:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2595,6 +2718,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[6:7], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f64:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2605,6 +2729,7 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5
; GFX11-NEXT: global_store_b64 v[2:3], v[6:7], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f64:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2698,6 +2823,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f16:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2723,6 +2849,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f16:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2734,6 +2861,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX8-NEXT: global_store_short v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-TRUE16-LABEL: safe_math_fract_f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2744,6 +2872,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0, v0.h, s0
; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v3, off
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-FAKE16-LABEL: safe_math_fract_f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2754,6 +2883,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-FAKE16-NEXT: global_store_b16 v[1:2], v4, off
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-TRUE16-LABEL: safe_math_fract_f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2769,6 +2899,7 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) writeonly captures(no
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, 0, v0.h, s0
; GFX12-TRUE16-NEXT: global_store_b16 v[1:2], v3, off
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-FAKE16-LABEL: safe_math_fract_f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2887,6 +3018,7 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_v2f16:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2932,6 +3064,7 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX7-NEXT: v_or_b32_e32 v0, v4, v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_v2f16:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2949,21 +3082,22 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-TRUE16-LABEL: safe_math_fract_v2f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_fract_f16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: v_fract_f16_e32 v3.h, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 0x204
; GFX11-TRUE16-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
-; GFX11-TRUE16-NEXT: v_floor_f16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_fract_f16_e32 v0.h, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v4.l, 0x204
-; GFX11-TRUE16-NEXT: v_floor_f16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: v_floor_f16_e32 v4.h, v0.h
+; GFX11-TRUE16-NEXT: v_floor_f16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, 0, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, 0, s0
-; GFX11-TRUE16-NEXT: global_store_b32 v[1:2], v5, off
+; GFX11-TRUE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-FAKE16-LABEL: safe_math_fract_v2f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2982,6 +3116,7 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX11-FAKE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v3
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-TRUE16-LABEL: safe_math_fract_v2f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -2989,19 +3124,18 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) writeon
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-TRUE16-NEXT: v_fract_f16_e32 v3.l, v0.l
+; GFX12-TRUE16-NEXT: v_fract_f16_e32 v3.h, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v0.h, 0x204
; GFX12-TRUE16-NEXT: v_cmp_class_f16_e64 s1, v0.l, 0x204
-; GFX12-TRUE16-NEXT: v_floor_f16_e32 v5.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_fract_f16_e32 v0.h, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_class_f16_e64 s0, v4.l, 0x204
-; GFX12-TRUE16-NEXT: v_floor_f16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_floor_f16_e32 v4.h, v0.h
+; GFX12-TRUE16-NEXT: v_floor_f16_e32 v4.l, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, 0, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, 0, s0
-; GFX12-TRUE16-NEXT: global_store_b32 v[1:2], v5, off
+; GFX12-TRUE16-NEXT: global_store_b32 v[1:2], v4, off
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-FAKE16-LABEL: safe_math_fract_v2f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3113,6 +3247,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX6-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_v2f64:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3134,6 +3269,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX7-NEXT: buffer_store_dwordx4 v[6:9], v[4:5], s[8:11], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_v2f64:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3151,6 +3287,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX8-NEXT: global_store_dwordx4 v[4:5], v[6:9], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_v2f64:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3166,6 +3303,7 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) wri
; GFX11-NEXT: v_cndmask_b32_e64 v3, v13, 0, s1
; GFX11-NEXT: global_store_b128 v[4:5], v[6:9], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_v2f64:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3246,6 +3384,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_minimum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3261,6 +3400,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_minimum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3272,6 +3412,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_minimum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3282,6 +3423,7 @@ define float @safe_math_fract_f32_minimum(float %x, ptr addrspace(1) writeonly c
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_minimum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3357,6 +3499,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_minimum_swap:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3372,6 +3515,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_minimum_swap:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3383,6 +3527,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_minimum_swap:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3393,6 +3538,7 @@ define float @safe_math_fract_f32_minimum_swap(float %x, ptr addrspace(1) writeo
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_minimum_swap:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3465,6 +3611,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_minimumnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3480,6 +3627,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_minimumnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3491,6 +3639,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_minimumnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3501,6 +3650,7 @@ define float @safe_math_fract_f32_minimumnum(float %x, ptr addrspace(1) writeonl
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_minimumnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3573,6 +3723,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX6-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_minimumnum_swap:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3588,6 +3739,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX7-NEXT: buffer_store_dword v3, v[1:2], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_minimumnum_swap:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3599,6 +3751,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX8-NEXT: global_store_dword v[1:2], v3, off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_minimumnum_swap:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3609,6 +3762,7 @@ define float @safe_math_fract_f32_minimumnum_swap(float %x, ptr addrspace(1) wri
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo
; GFX11-NEXT: global_store_b32 v[1:2], v4, off
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_minimumnum_swap:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3659,21 +3813,25 @@ define float @basic_fract_f32_nonans_minimumnum(float nofpclass(nan) %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_nonans_minimumnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_nonans_minimumnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_nonans_minimumnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_nonans_minimumnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3715,21 +3873,25 @@ define float @basic_fract_f32_nonans_minimum(float nofpclass(nan) %x) {
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_nonans_minimum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_nonans_minimum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_nonans_minimum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_nonans_minimum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3768,21 +3930,25 @@ define float @nnan_minimum_fract_f32(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_minimum_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_minimum_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_minimum_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_minimum_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3821,21 +3987,25 @@ define float @nnan_minimumnum_fract_f32(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: nnan_minimumnum_fract_f32:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: nnan_minimumnum_fract_f32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: nnan_minimumnum_fract_f32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: nnan_minimumnum_fract_f32:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3868,6 +4038,7 @@ define float @basic_fract_f32_flags_minimumnum(float %x) {
; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_flags_minimumnum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3875,6 +4046,7 @@ define float @basic_fract_f32_flags_minimumnum(float %x) {
; GFX7-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX7-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_flags_minimumnum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3882,6 +4054,7 @@ define float @basic_fract_f32_flags_minimumnum(float %x) {
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_flags_minimumnum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -3890,6 +4063,7 @@ define float @basic_fract_f32_flags_minimumnum(float %x) {
; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_flags_minimumnum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -3934,21 +4108,25 @@ define float @basic_fract_f32_flags_minimum(float %x) {
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_flags_minimum:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_flags_minimum:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_flags_minimum:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_flags_minimum:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4044,7 +4222,6 @@ define double @fract_match_f64_assume_not_nan(double %x) #0 {
; GFX6-IR-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], +inf
; GFX6-IR-NEXT: [[RESULT:%.*]] = select i1 [[IS_INF]], double 0.000000e+00, double [[MIN]]
; GFX6-IR-NEXT: ret double [[RESULT]]
-;
; IR-FRACT-LABEL: define double @fract_match_f64_assume_not_nan(
; IR-FRACT-SAME: double [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -4055,7 +4232,6 @@ define double @fract_match_f64_assume_not_nan(double %x) #0 {
; IR-FRACT-NEXT: [[IS_INF:%.*]] = fcmp oeq double [[X_ABS]], +inf
; IR-FRACT-NEXT: [[RESULT:%.*]] = select i1 [[IS_INF]], double 0.000000e+00, double [[MIN]]
; IR-FRACT-NEXT: ret double [[RESULT]]
-;
entry:
%is.ord = fcmp ord double %x, 0.000000e+00
tail call void @llvm.assume(i1 %is.ord)
@@ -4104,6 +4280,7 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4112,6 +4289,7 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; GFX7-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swapped_edge_case:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4120,6 +4298,7 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; GFX8-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swapped_edge_case:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4128,6 +4307,7 @@ define float @safe_math_fract_f32_swapped_edge_case(float %x) #0 {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swapped_edge_case:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4235,7 +4415,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select(float
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
; GFX6-IR-NEXT: ret float [[COND8]]
-;
; IR-FRACT-LABEL: define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
@@ -4244,7 +4423,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select(float
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: store float [[COND8]], ptr addrspace(1) [[PTR]], align 4
; IR-FRACT-NEXT: ret float [[COND8]]
-;
%floor = call float @llvm.floor.f32(float %x)
%sub = fsub float %x, %floor
%min = call float @llvm.minnum.f32(float %sub, float 0x3FEFFFFFE0000000)
@@ -4344,7 +4522,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
; GFX6-IR-NEXT: ret float [[COND8]]
-;
; IR-FRACT-LABEL: define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
@@ -4353,7 +4530,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_inner_select_fcmp(
; IR-FRACT-NEXT: store i1 [[NOT_INF]], ptr addrspace(1) [[PTR]], align 1
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
-;
%floor = call float @llvm.floor.f32(float %x)
%sub = fsub float %x, %floor
%min = call float @llvm.minnum.f32(float %sub, float 0x3FEFFFFFE0000000)
@@ -4453,7 +4629,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_fabs(float %x, ptr
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
; GFX6-IR-NEXT: ret float [[COND8]]
-;
; IR-FRACT-LABEL: define float @safe_math_fract_f32_swapped_edge_case_multi_use_fabs(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[COND:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
@@ -4462,7 +4637,6 @@ define float @safe_math_fract_f32_swapped_edge_case_multi_use_fabs(float %x, ptr
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
-;
%floor = call float @llvm.floor.f32(float %x) #3
%sub = fsub float %x, %floor
%min = call float @llvm.minnum.f32(float %sub, float 0x3FEFFFFFE0000000)
@@ -4501,6 +4675,7 @@ define float @safe_math_fract_f32_swapped_edge_case_wrong_compared(float %x, flo
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case_wrong_compared:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4513,6 +4688,7 @@ define float @safe_math_fract_f32_swapped_edge_case_wrong_compared(float %x, flo
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swapped_edge_case_wrong_compared:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4525,6 +4701,7 @@ define float @safe_math_fract_f32_swapped_edge_case_wrong_compared(float %x, flo
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swapped_edge_case_wrong_compared:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4538,6 +4715,7 @@ define float @safe_math_fract_f32_swapped_edge_case_wrong_compared(float %x, flo
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swapped_edge_case_wrong_compared:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4595,6 +4773,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_inf_check(float %x)
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case_commute_inf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4607,6 +4786,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_inf_check(float %x)
; GFX7-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swapped_edge_case_commute_inf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4619,6 +4799,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_inf_check(float %x)
; GFX8-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swapped_edge_case_commute_inf_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4632,6 +4813,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_inf_check(float %x)
; GFX11-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swapped_edge_case_commute_inf_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4689,6 +4871,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_nan_check(float %x)
; GFX6-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case_commute_nan_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4701,6 +4884,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_nan_check(float %x)
; GFX7-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swapped_edge_case_commute_nan_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4713,6 +4897,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_nan_check(float %x)
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swapped_edge_case_commute_nan_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4726,6 +4911,7 @@ define float @safe_math_fract_f32_swapped_edge_case_commute_nan_check(float %x)
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swapped_edge_case_commute_nan_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4781,21 +4967,25 @@ define float @safe_math_fract_f32_swapped_edge_case_cmp_neg_inf(float %x) #0 {
; GFX6-NEXT: v_cmp_o_f32_e32 vcc, v0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: safe_math_fract_f32_swapped_edge_case_cmp_neg_inf:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_fract_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: safe_math_fract_f32_swapped_edge_case_cmp_neg_inf:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_fract_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: safe_math_fract_f32_swapped_edge_case_cmp_neg_inf:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fract_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: safe_math_fract_f32_swapped_edge_case_cmp_neg_inf:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4839,6 +5029,7 @@ define float @basic_fract_f32_with_inf_check(float %x) {
; GFX6-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_with_inf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4849,6 +5040,7 @@ define float @basic_fract_f32_with_inf_check(float %x) {
; GFX7-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_with_inf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4859,6 +5051,7 @@ define float @basic_fract_f32_with_inf_check(float %x) {
; GFX8-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_with_inf_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4870,6 +5063,7 @@ define float @basic_fract_f32_with_inf_check(float %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_with_inf_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -4927,6 +5121,7 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; GFX6-NEXT: v_cmp_lg_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
; GFX7-LABEL: basic_fract_f32_nonans_with_inf_check:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4935,6 +5130,7 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; GFX7-NEXT: v_cmp_lg_f32_e64 vcc, |v0|, s4
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
; GFX8-LABEL: basic_fract_f32_nonans_with_inf_check:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4943,6 +5139,7 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; GFX8-NEXT: v_cmp_lg_f32_e64 vcc, |v0|, s4
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX11-LABEL: basic_fract_f32_nonans_with_inf_check:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -4951,6 +5148,7 @@ define float @basic_fract_f32_nonans_with_inf_check(float nofpclass(nan) %x) {
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
; GFX12-LABEL: basic_fract_f32_nonans_with_inf_check:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
@@ -5053,7 +5251,6 @@ define float @safe_math_fract_f32_swapped_edge_case_x_is_const() #0 {
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float bitcast (i32 ptrtoint (ptr @gv to i32) to float), 0.000000e+00
; GFX6-IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float bitcast (i32 ptrtoint (ptr @gv to i32) to float)
; GFX6-IR-NEXT: ret float [[COND8]]
-;
; IR-FRACT-LABEL: define float @safe_math_fract_f32_swapped_edge_case_x_is_const(
; IR-FRACT-SAME: ) #[[ATTR0]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -5062,7 +5259,6 @@ define float @safe_math_fract_f32_swapped_edge_case_x_is_const() #0 {
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[X_FABS]], +inf
; IR-FRACT-NEXT: [[COND8:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND8]]
-;
entry:
%floor = call float @llvm.floor.f32(float bitcast (i32 ptrtoint (ptr @gv to i32) to float))
%sub = fsub float bitcast (i32 ptrtoint (ptr @gv to i32) to float), %floor
@@ -5236,7 +5432,6 @@ define float @safe_math_fract_f32_swapped_edge_case_split_block(float %x, i1 %co
; GFX6-IR-NEXT: ret float [[COND8]]
; GFX6-IR: [[RET]]:
; GFX6-IR-NEXT: ret float [[MIN]]
-;
; IR-FRACT-LABEL: define float @safe_math_fract_f32_swapped_edge_case_split_block(
; IR-FRACT-SAME: float [[X:%.*]], i1 [[COND:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[FLOOR:%.*]] = call float @llvm.floor.f32(float [[X]])
@@ -5251,7 +5446,6 @@ define float @safe_math_fract_f32_swapped_edge_case_split_block(float %x, i1 %co
; IR-FRACT-NEXT: ret float [[COND8]]
; IR-FRACT: [[RET]]:
; IR-FRACT-NEXT: ret float [[MIN]]
-;
%floor = call float @llvm.floor.f32(float %x)
%sub = fsub float %x, %floor
%min = call float @llvm.minnum.f32(float %sub, float 0x3FEFFFFFE0000000)
@@ -5358,7 +5552,6 @@ define <3 x float> @safe_math_fract_f32_swapped_edge_case_vector(<3 x float> %x)
; GFX6-IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord <3 x float> [[X]], <float 0.000000e+00, float poison, float 0.000000e+00>
; GFX6-IR-NEXT: [[COND8:%.*]] = select <3 x i1> [[NOT_NAN]], <3 x float> [[COND]], <3 x float> [[X]]
; GFX6-IR-NEXT: ret <3 x float> [[COND8]]
-;
; IR-FRACT-LABEL: define <3 x float> @safe_math_fract_f32_swapped_edge_case_vector(
; IR-FRACT-SAME: <3 x float> [[X:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -5375,7 +5568,6 @@ define <3 x float> @safe_math_fract_f32_swapped_edge_case_vector(<3 x float> %x)
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une <3 x float> [[X_FABS]], <float +inf, float poison, float +inf>
; IR-FRACT-NEXT: [[COND8:%.*]] = select <3 x i1> [[NOT_INF]], <3 x float> [[COND]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>
; IR-FRACT-NEXT: ret <3 x float> [[COND8]]
-;
entry:
%floor = call <3 x float> @llvm.floor.v3f32(<3 x float> %x)
%sub = fsub <3 x float> %x, %floor
@@ -5438,7 +5630,6 @@ define float @safe_math_fract_f32_swapped_edge_case_inf_check_wrong_compare(floa
; IR-NEXT: [[NOT_NAN:%.*]] = fcmp ord float [[X]], 0.000000e+00
; IR-NEXT: [[COND8:%.*]] = select i1 [[NOT_NAN]], float [[COND]], float [[X]]
; IR-NEXT: ret float [[COND8]]
-;
entry:
%floor = call float @llvm.floor.f32(float %x)
%sub = fsub float %x, %floor
@@ -5537,7 +5728,6 @@ define float @fract_pat_fcmp_oge_select(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
-;
; IR-FRACT-LABEL: define float @fract_pat_fcmp_oge_select(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[IPTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -5548,7 +5738,6 @@ define float @fract_pat_fcmp_oge_select(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
-;
entry:
%call = call float @llvm.floor.f32(float %x)
store float %call, ptr addrspace(1) %iptr, align 4
@@ -5645,7 +5834,6 @@ define float @fract_pat_fcmp_ogt_select(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
-;
; IR-FRACT-LABEL: define float @fract_pat_fcmp_ogt_select(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[IPTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -5656,7 +5844,6 @@ define float @fract_pat_fcmp_ogt_select(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
-;
entry:
%call = call float @llvm.floor.f32(float %x)
store float %call, ptr addrspace(1) %iptr, align 4
@@ -5758,7 +5945,6 @@ define float @negative_fract_pat_fcmp_olt(float %x, ptr addrspace(1) %iptr) #0 {
; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-NEXT: ret float [[COND6]]
-;
entry:
%call = call float @llvm.floor.f32(float noundef %x)
store float %call, ptr addrspace(1) %iptr, align 4
@@ -5859,7 +6045,6 @@ define float @fract_pat_fcmp_olt_not_nan_src(float nofpclass(nan) %x, ptr addrsp
; IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[COND]], float 0.000000e+00
; IR-NEXT: ret float [[COND6]]
-;
entry:
%call = call float @llvm.floor.f32(float noundef %x)
store float %call, ptr addrspace(1) %iptr, align 4
@@ -5959,7 +6144,6 @@ define float @fract_pat_minimum(float %x, ptr addrspace(1) %iptr) #0 {
; GFX6-IR-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; GFX6-IR-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; GFX6-IR-NEXT: ret float [[COND6]]
-;
; IR-FRACT-LABEL: define float @fract_pat_minimum(
; IR-FRACT-SAME: float [[X:%.*]], ptr addrspace(1) [[IPTR:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[ENTRY:.*:]]
@@ -5970,7 +6154,6 @@ define float @fract_pat_minimum(float %x, ptr addrspace(1) %iptr) #0 {
; IR-FRACT-NEXT: [[NOT_INF:%.*]] = fcmp une float [[FABS_X]], +inf
; IR-FRACT-NEXT: [[COND6:%.*]] = select i1 [[NOT_INF]], float [[MIN]], float 0.000000e+00
; IR-FRACT-NEXT: ret float [[COND6]]
-;
entry:
%call = call float @llvm.floor.f32(float %x)
store float %call, ptr addrspace(1) %iptr, align 4
@@ -6025,12 +6208,10 @@ define float @core_fract_pat_fcmp_oge_select(float %x) #0 {
; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge float [[SUB_FLOOR]], f0x3F7FFFFF
; GFX6-IR-NEXT: [[SELECT:%.*]] = select i1 [[OGE_MIN_CONST]], float f0x3F7FFFFF, float [[SUB_FLOOR]]
; GFX6-IR-NEXT: ret float [[SELECT]]
-;
; IR-FRACT-LABEL: define float @core_fract_pat_fcmp_oge_select(
; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[SELECT:%.*]] = call float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: ret float [[SELECT]]
-;
%floor = call float @llvm.floor.f32(float %x)
%sub.floor = fsub float %x, %floor
%oge.min.const = fcmp oge float %sub.floor, 0x3FEFFFFFE0000000
@@ -6083,12 +6264,10 @@ define float @core_fract_pat_minimum(float %x) #0 {
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub float [[X]], [[FLOOR]]
; GFX6-IR-NEXT: [[MIN:%.*]] = call float @llvm.minimum.f32(float [[SUB_FLOOR]], float f0x3F7FFFFF)
; GFX6-IR-NEXT: ret float [[MIN]]
-;
; IR-FRACT-LABEL: define float @core_fract_pat_minimum(
; IR-FRACT-SAME: float [[X:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[MIN:%.*]] = call nnan float @llvm.amdgcn.fract.f32(float [[X]])
; IR-FRACT-NEXT: ret float [[MIN]]
-;
%floor = call float @llvm.floor.f32(float %x)
%sub.floor = fsub float %x, %floor
%min = call float @llvm.minimum.f32(float %sub.floor, float 0x3FEFFFFFE0000000)
@@ -6144,7 +6323,6 @@ define <2 x float> @core_fract_pat_fcmp_oge_select_v2f32(<2 x float> %x) #0 {
; GFX6-IR-NEXT: [[OGE_MIN_CONST:%.*]] = fcmp oge <2 x float> [[SUB_FLOOR]], <float f0x3F7FFFFF, float poison>
; GFX6-IR-NEXT: [[SELECT:%.*]] = select <2 x i1> [[OGE_MIN_CONST]], <2 x float> <float f0x3F7FFFFF, float poison>, <2 x float> [[SUB_FLOOR]]
; GFX6-IR-NEXT: ret <2 x float> [[SELECT]]
-;
; IR-FRACT-LABEL: define <2 x float> @core_fract_pat_fcmp_oge_select_v2f32(
; IR-FRACT-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 0
@@ -6154,7 +6332,6 @@ define <2 x float> @core_fract_pat_fcmp_oge_select_v2f32(<2 x float> %x) #0 {
; IR-FRACT-NEXT: [[TMP5:%.*]] = insertelement <2 x float> poison, float [[TMP3]], i64 0
; IR-FRACT-NEXT: [[SELECT:%.*]] = insertelement <2 x float> [[TMP5]], float [[TMP4]], i64 1
; IR-FRACT-NEXT: ret <2 x float> [[SELECT]]
-;
%floor = call <2 x float> @llvm.floor.v2f32(<2 x float> %x)
%sub.floor = fsub <2 x float> %x, %floor
%oge.min.const = fcmp oge <2 x float> %sub.floor, <float 0x3FEFFFFFE0000000, float poison>
@@ -6212,7 +6389,6 @@ define <2 x float> @core_fract_pat_minimum_v2f32(<2 x float> %x) #0 {
; GFX6-IR-NEXT: [[SUB_FLOOR:%.*]] = fsub <2 x float> [[X]], [[FLOOR]]
; GFX6-IR-NEXT: [[MIN:%.*]] = call <2 x float> @llvm.minimum.v2f32(<2 x float> [[SUB_FLOOR]], <2 x float> <float f0x3F7FFFFF, float poison>)
; GFX6-IR-NEXT: ret <2 x float> [[MIN]]
-;
; IR-FRACT-LABEL: define <2 x float> @core_fract_pat_minimum_v2f32(
; IR-FRACT-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; IR-FRACT-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[X]], i64 0
@@ -6222,7 +6398,6 @@ define <2 x float> @core_fract_pat_minimum_v2f32(<2 x float> %x) #0 {
; IR-FRACT-NEXT: [[TMP5:%.*]] = insertelement <2 x float> poison, float [[TMP3]], i64 0
; IR-FRACT-NEXT: [[MIN:%.*]] = insertelement <2 x float> [[TMP5]], float [[TMP4]], i64 1
; IR-FRACT-NEXT: ret <2 x float> [[MIN]]
-;
%floor = call <2 x float> @llvm.floor.v2f32(<2 x float> %x)
%sub.floor = fsub <2 x float> %x, %floor
%min = call <2 x float> @llvm.minimum.v2f32(<2 x float> %sub.floor, <2 x float> <float 0x3FEFFFFFE0000000, float poison>)
diff --git a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
index 2f1542743f8e5d..4534a4e0b426d1 100644
--- a/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
@@ -494,10 +494,8 @@ define <2 x i16> @frexp_nan_clamp_exp_v2f16(<2 x half> %x) {
; GFX11-LABEL: frexp_nan_clamp_exp_v2f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v0.h
; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0.h, v1.l
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX950-LABEL: frexp_nan_clamp_exp_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 29d40dabdf4682..c18dbaa94921c3 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -1813,26 +1813,23 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; GFX11-TRUE16-LABEL: v_fshr_v3i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v2.h, v5.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v6.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v1.h, v7.l, -1
+; GFX11-TRUE16-NEXT: v_xor_b16 v1.h, v5.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
+; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v4.h, -1
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v4.l, -1
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.h, v7.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v2.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v5.l, v3.l
+; GFX11-TRUE16-NEXT: v_xor_b16 v5.h, v4.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v3.h, v0.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v5.h, v0.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.h, v5.l, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fshr_v3i16:
@@ -1869,26 +1866,23 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v2.h, v5.l, -1
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v6.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v1.h, v7.l, -1
+; GFX12-TRUE16-NEXT: v_xor_b16 v1.h, v5.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
+; GFX12-TRUE16-NEXT: v_xor_b16 v3.h, v4.h, -1
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v3.h, v4.l, -1
-; GFX12-TRUE16-NEXT: v_lshrrev_b16 v4.h, v7.l, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v2.h, v1.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, v1.h, v0.h
-; GFX12-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v3.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.l, v5.l, v3.l
+; GFX12-TRUE16-NEXT: v_xor_b16 v5.h, v4.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v1.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v1.h, v4.h, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, v3.h, v0.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v5.h, v0.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.h, v5.l, v3.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v4.h
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v2.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_fshr_v3i16:
@@ -2053,30 +2047,24 @@ define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2
; GFX11-TRUE16-LABEL: v_fshr_v4i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v1.h
+; GFX11-TRUE16-NEXT: v_xor_b16 v6.l, v5.h, -1
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.h, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v8.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v3.h, v7.l, -1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v9.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v4.h, v10.l, -1
-; GFX11-TRUE16-NEXT: v_xor_b16 v5.h, v5.l, -1
+; GFX11-TRUE16-NEXT: v_xor_b16 v6.h, v5.l, -1
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: v_xor_b16 v6.l, v4.l, -1
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, v3.h, v1.h
-; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.h, v10.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, v4.h, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v5.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v6.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, v6.l, v1.h
+; GFX11-TRUE16-NEXT: v_xor_b16 v6.l, v4.h, -1
+; GFX11-TRUE16-NEXT: v_xor_b16 v7.l, v4.l, -1
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.h, v5.h, v3.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v6.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.h, v4.h, v2.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, v6.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v7.l, v0.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v3.l, v5.l, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v3.h
+; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v2.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v3.l
@@ -2124,30 +2112,24 @@ define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v1.h
+; GFX12-TRUE16-NEXT: v_xor_b16 v6.l, v5.h, -1
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 1, v1.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.h, v7.l, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 1, v8.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v3.h, v7.l, -1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.h, 1, v9.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v4.h, v10.l, -1
-; GFX12-TRUE16-NEXT: v_xor_b16 v5.h, v5.l, -1
+; GFX12-TRUE16-NEXT: v_xor_b16 v6.h, v5.l, -1
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 1, v0.h
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: v_xor_b16 v6.l, v4.l, -1
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, v3.h, v1.h
-; GFX12-TRUE16-NEXT: v_lshrrev_b16 v3.h, v10.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.h, v4.h, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v5.h, v1.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v6.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, v6.l, v1.h
+; GFX12-TRUE16-NEXT: v_xor_b16 v6.l, v4.h, -1
+; GFX12-TRUE16-NEXT: v_xor_b16 v7.l, v4.l, -1
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v3.h, v5.h, v3.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, v6.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.h, v4.h, v2.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, v6.l, v0.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, v7.l, v0.l
; GFX12-TRUE16-NEXT: v_lshrrev_b16 v2.l, v4.l, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b16 v3.l, v5.l, v3.l
-; GFX12-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v0.h
-; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v3.h
+; GFX12-TRUE16-NEXT: v_or_b16 v1.h, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_or_b16 v0.h, v0.h, v2.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
; GFX12-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v3.l
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index c1089c70368be9..1430ef6ad9aae2 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -21468,19 +21468,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB78_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -21491,12 +21490,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -21508,7 +21504,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB78_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -21870,19 +21865,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB79_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -21893,12 +21887,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -21910,7 +21901,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB79_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -22274,19 +22264,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB80_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -22297,12 +22286,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -22314,7 +22300,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB80_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -22686,16 +22671,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB81_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -22704,15 +22688,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -22725,7 +22706,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB81_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23072,16 +23052,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB82_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -23090,15 +23069,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -23111,7 +23087,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB82_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23461,16 +23436,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB83_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -23479,15 +23453,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -23500,7 +23471,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB83_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -23859,19 +23829,18 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB84_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -23882,12 +23851,9 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -23899,7 +23865,6 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB84_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -24267,16 +24232,15 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB85_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -24285,15 +24249,12 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -24306,7 +24267,6 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB85_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -24659,19 +24619,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB86_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -24682,12 +24641,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -24699,7 +24655,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB86_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -25061,16 +25016,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB87_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -25079,15 +25033,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -25100,7 +25051,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB87_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -25447,19 +25397,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB88_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -25470,12 +25419,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -25487,7 +25433,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB88_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -25849,16 +25794,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB89_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -25867,15 +25811,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -25888,7 +25829,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB89_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -26235,19 +26175,18 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB90_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -26258,12 +26197,9 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -26275,7 +26211,6 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB90_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -26637,16 +26572,15 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB91_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -26655,15 +26589,12 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -26676,7 +26607,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB91_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 2b5feeb6867313..f352dd9c53f46d 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -14915,12 +14915,12 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -14932,13 +14932,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15055,19 +15052,18 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15078,12 +15074,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15095,7 +15088,6 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15430,12 +15422,12 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15447,13 +15439,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15570,19 +15559,18 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15593,12 +15581,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15610,7 +15595,6 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15947,12 +15931,12 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15964,13 +15948,10 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16087,19 +16068,18 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -16110,12 +16090,9 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16127,7 +16104,6 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16470,11 +16446,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16484,15 +16460,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16607,16 +16580,15 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16625,15 +16597,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16646,7 +16615,6 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16964,11 +16932,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16978,15 +16946,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17101,16 +17066,15 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17119,15 +17083,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17140,7 +17101,6 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17461,11 +17421,11 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17475,15 +17435,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17598,16 +17555,15 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17616,15 +17572,12 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17637,7 +17590,6 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17968,12 +17920,12 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -17985,13 +17937,10 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18110,19 +18059,18 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB60_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18133,12 +18081,9 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -18150,7 +18095,6 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18488,11 +18432,11 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18502,15 +18446,12 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18627,16 +18568,15 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18645,15 +18585,12 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -18666,7 +18603,6 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index 1510e0efeeee23..410af2929e8c6b 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -14915,12 +14915,12 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -14932,13 +14932,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15055,19 +15052,18 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15078,12 +15074,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15095,7 +15088,6 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15430,12 +15422,12 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15447,13 +15439,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15570,19 +15559,18 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15593,12 +15581,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15610,7 +15595,6 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15947,12 +15931,12 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15964,13 +15948,10 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16087,19 +16068,18 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -16110,12 +16090,9 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16127,7 +16104,6 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16470,11 +16446,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16484,15 +16460,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16607,16 +16580,15 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16625,15 +16597,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16646,7 +16615,6 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -16964,11 +16932,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16978,15 +16946,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17101,16 +17066,15 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17119,15 +17083,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17140,7 +17101,6 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB58_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17461,11 +17421,11 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17475,15 +17435,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17598,16 +17555,15 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17616,15 +17572,12 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17637,7 +17590,6 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB59_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17968,12 +17920,12 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -17985,13 +17937,10 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18110,19 +18059,18 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB60_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18133,12 +18081,9 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -18150,7 +18095,6 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB60_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18488,11 +18432,11 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18502,15 +18446,12 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18627,16 +18568,15 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18645,15 +18585,12 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -18666,7 +18603,6 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB61_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index ef314c8f68b1fe..42a8596598bce2 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -15273,12 +15273,12 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15290,13 +15290,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15413,19 +15410,18 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15436,12 +15432,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15453,7 +15446,6 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -15788,12 +15780,12 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -15805,13 +15797,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -15928,19 +15917,18 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB51_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -15951,12 +15939,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -15968,7 +15953,6 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB51_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16305,12 +16289,12 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -16322,13 +16306,10 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16445,19 +16426,18 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -16468,12 +16448,9 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -16485,7 +16462,6 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB52_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -16828,11 +16804,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16842,15 +16818,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -16965,16 +16938,15 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB53_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -16983,15 +16955,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17004,7 +16973,6 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB53_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17322,11 +17290,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17336,15 +17304,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17459,16 +17424,15 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17477,15 +17441,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17498,7 +17459,6 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB54_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -17819,11 +17779,11 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17833,15 +17793,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
@@ -17956,16 +17913,15 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -17974,15 +17930,12 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:-2048 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -17995,7 +17948,6 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace(
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB55_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -18326,12 +18278,12 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
@@ -18343,13 +18295,10 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18468,19 +18417,18 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v3, v3, v2
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
@@ -18491,12 +18439,9 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v3, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[5:6], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -18508,7 +18453,6 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB56_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -18846,11 +18790,11 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -18860,15 +18804,12 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX12-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX12-TRUE16-NEXT: global_wb scope:SCOPE_SYS
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
@@ -18985,16 +18926,15 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB57_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v5
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
@@ -19003,15 +18943,12 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v6, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v10, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2044 glc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
@@ -19024,7 +18961,6 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB57_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
index ec16890ba93fbe..8ac3bdd90231e2 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
@@ -75,28 +75,28 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
}
define i16 @test_v7i16_load_store(ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr2) {
-; GCN-SDAG-LABEL: test_v7i16_load_store:
-; GCN-SDAG: ; %bb.0:
-; GCN-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-SDAG-NEXT: s_wait_kmcnt 0x0
-; GCN-SDAG-NEXT: global_load_b128 v[4:7], v[0:1], off
-; GCN-SDAG-NEXT: global_load_b128 v[8:11], v[2:3], off
-; GCN-SDAG-NEXT: v_mov_b64_e32 v[12:13], 0
-; GCN-SDAG-NEXT: s_wait_loadcnt 0x0
-; GCN-SDAG-NEXT: s_wait_xcnt 0x1
-; GCN-SDAG-NEXT: v_pk_add_u16 v1, v6, v10
-; GCN-SDAG-NEXT: s_wait_xcnt 0x0
-; GCN-SDAG-NEXT: v_pk_add_u16 v3, v5, v9
-; GCN-SDAG-NEXT: v_pk_add_u16 v5, v7, v11
-; GCN-SDAG-NEXT: v_mov_b64_e32 v[6:7], 12
-; GCN-SDAG-NEXT: v_mov_b64_e32 v[10:11], 8
-; GCN-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GCN-SDAG-NEXT: v_pk_add_u16 v2, v4, v8
-; GCN-SDAG-NEXT: s_clause 0x2
-; GCN-SDAG-NEXT: global_store_b16 v[6:7], v5, off
-; GCN-SDAG-NEXT: global_store_b32 v[10:11], v1, off
-; GCN-SDAG-NEXT: global_store_b64 v[12:13], v[2:3], off
-; GCN-SDAG-NEXT: s_set_pc_i64 s[30:31]
+; GCN-SDAG-FAKE16-LABEL: test_v7i16_load_store:
+; GCN-SDAG-FAKE16: ; %bb.0:
+; GCN-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GCN-SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GCN-SDAG-FAKE16-NEXT: global_load_b128 v[4:7], v[0:1], off
+; GCN-SDAG-FAKE16-NEXT: global_load_b128 v[8:11], v[2:3], off
+; GCN-SDAG-FAKE16-NEXT: v_mov_b64_e32 v[12:13], 0
+; GCN-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GCN-SDAG-FAKE16-NEXT: s_wait_xcnt 0x1
+; GCN-SDAG-FAKE16-NEXT: v_pk_add_u16 v1, v6, v10
+; GCN-SDAG-FAKE16-NEXT: s_wait_xcnt 0x0
+; GCN-SDAG-FAKE16-NEXT: v_pk_add_u16 v3, v5, v9
+; GCN-SDAG-FAKE16-NEXT: v_pk_add_u16 v5, v7, v11
+; GCN-SDAG-FAKE16-NEXT: v_mov_b64_e32 v[6:7], 12
+; GCN-SDAG-FAKE16-NEXT: v_mov_b64_e32 v[10:11], 8
+; GCN-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GCN-SDAG-FAKE16-NEXT: v_pk_add_u16 v2, v4, v8
+; GCN-SDAG-FAKE16-NEXT: s_clause 0x2
+; GCN-SDAG-FAKE16-NEXT: global_store_b16 v[6:7], v5, off
+; GCN-SDAG-FAKE16-NEXT: global_store_b32 v[10:11], v1, off
+; GCN-SDAG-FAKE16-NEXT: global_store_b64 v[12:13], v[2:3], off
+; GCN-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
; GCN-GISEL-FAKE16-LABEL: test_v7i16_load_store:
; GCN-GISEL-FAKE16: ; %bb.0:
@@ -128,6 +128,29 @@ define i16 @test_v7i16_load_store(ptr addrspace(1) %ptr1, ptr addrspace(1) %ptr2
; GCN-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GCN-GISEL-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
+; GCN-SDAG-REAL16-LABEL: test_v7i16_load_store:
+; GCN-SDAG-REAL16: ; %bb.0:
+; GCN-SDAG-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GCN-SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
+; GCN-SDAG-REAL16-NEXT: global_load_b128 v[4:7], v[0:1], off
+; GCN-SDAG-REAL16-NEXT: global_load_b128 v[8:11], v[2:3], off
+; GCN-SDAG-REAL16-NEXT: s_wait_xcnt 0x0
+; GCN-SDAG-REAL16-NEXT: v_mov_b64_e32 v[2:3], 12
+; GCN-SDAG-REAL16-NEXT: v_mov_b64_e32 v[12:13], 8
+; GCN-SDAG-REAL16-NEXT: v_mov_b64_e32 v[14:15], 0
+; GCN-SDAG-REAL16-NEXT: s_wait_loadcnt 0x0
+; GCN-SDAG-REAL16-NEXT: v_pk_add_u16 v1, v7, v11
+; GCN-SDAG-REAL16-NEXT: v_pk_add_u16 v0, v6, v10
+; GCN-SDAG-REAL16-NEXT: v_pk_add_u16 v5, v5, v9
+; GCN-SDAG-REAL16-NEXT: v_pk_add_u16 v4, v4, v8
+; GCN-SDAG-REAL16-NEXT: s_clause 0x2
+; GCN-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v1, off
+; GCN-SDAG-REAL16-NEXT: global_store_b32 v[12:13], v0, off
+; GCN-SDAG-REAL16-NEXT: global_store_b64 v[14:15], v[4:5], off
+; GCN-SDAG-REAL16-NEXT: s_wait_xcnt 0x1
+; GCN-SDAG-REAL16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GCN-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
+;
; GCN-GISEL-REAL16-LABEL: test_v7i16_load_store:
; GCN-GISEL-REAL16: ; %bb.0:
; GCN-GISEL-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index c3807581d13e17..a8b37029649409 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -33,45 +33,85 @@ define bfloat @v_uitofp_i1_to_bf16(i1 %num) {
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_uitofp_i1_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_uitofp_i1_to_bf16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_uitofp_i1_to_bf16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
-; GFX12-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX12-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: v_uitofp_i1_to_bf16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_uitofp_i1_to_bf16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_uitofp_i1_to_bf16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
+; GFX12-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%op = uitofp i1 %num to bfloat
ret bfloat %op
}
@@ -191,12 +231,12 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-LABEL: v_uitofp_v2i1_to_v2bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
@@ -211,11 +251,8 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_uitofp_v2i1_to_v2bf16:
@@ -251,13 +288,13 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -274,11 +311,8 @@ define <2 x bfloat> @v_uitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_uitofp_v2i1_to_v2bf16:
@@ -495,40 +529,37 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-LABEL: v_uitofp_v3i1_to_v3bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v6, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_uitofp_v3i1_to_v3bf16:
@@ -575,45 +606,42 @@ define <3 x bfloat> @v_uitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v6, v0, 0x7fff
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_uitofp_v3i1_to_v3bf16:
@@ -898,49 +926,44 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_uitofp_v4i1_to_v4bf16:
@@ -998,56 +1021,51 @@ define <4 x bfloat> @v_uitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
-; GFX12-TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
-; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.h
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_uitofp_v4i1_to_v4bf16:
@@ -1339,45 +1357,85 @@ define bfloat @v_sitofp_i1_to_bf16(i1 %num) {
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-LABEL: v_sitofp_i1_to_bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
-; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_setpc_b64 s[30:31]
+; GFX11-TRUE16-LABEL: v_sitofp_i1_to_bf16:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_sitofp_i1_to_bf16:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
-; GFX12-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX12-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX11-FAKE16-LABEL: v_sitofp_i1_to_bf16:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: v_sitofp_i1_to_bf16:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_sitofp_i1_to_bf16:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
+; GFX12-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%op = sitofp i1 %num to bfloat
ret bfloat %op
}
@@ -1497,12 +1555,12 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-LABEL: v_sitofp_v2i1_to_v2bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
@@ -1517,11 +1575,8 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_sitofp_v2i1_to_v2bf16:
@@ -1557,13 +1612,13 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
@@ -1580,11 +1635,8 @@ define <2 x bfloat> @v_sitofp_v2i1_to_v2bf16(<2 x i1> %num) {
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_sitofp_v2i1_to_v2bf16:
@@ -1803,40 +1855,37 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX11-TRUE16-LABEL: v_sitofp_v3i1_to_v3bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v5, v6, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_sitofp_v3i1_to_v3bf16:
@@ -1883,45 +1932,42 @@ define <3 x bfloat> @v_sitofp_v3i1_to_v3bf16(<3 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
; GFX12-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
+; GFX12-TRUE16-NEXT: v_add3_u32 v3, v3, v2, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 16, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
-; GFX12-TRUE16-NEXT: v_add3_u32 v5, v6, v0, 0x7fff
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_sitofp_v3i1_to_v3bf16:
@@ -2209,49 +2255,44 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.h
-; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
+; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_sitofp_v4i1_to_v4bf16:
@@ -2309,56 +2350,51 @@ define <4 x bfloat> @v_sitofp_v4i1_to_v4bf16(<4 x i1> %num) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v3.l
-; GFX12-TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l
-; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l
+; GFX12-TRUE16-NEXT: v_and_b16 v2.l, 1, v2.l
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.h
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, -1.0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v1.l
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v2.l
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l
-; GFX12-TRUE16-NEXT: v_add3_u32 v6, v6, v3, 0x7fff
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
+; GFX12-TRUE16-NEXT: v_add3_u32 v5, v5, v2, 0x7fff
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
; GFX12-TRUE16-NEXT: v_add3_u32 v5, v9, v0, 0x7fff
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_sitofp_v4i1_to_v4bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll
index 31622c37e0d847..c2037dc42affaf 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll
@@ -1151,31 +1151,28 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v1.h, 8, v1.l
-; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v2.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v4.h, 8, v1.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v7.h, 8, v2.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v1.h, 8, v1.h
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v2.h
+; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v4, v4, v7
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.l
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v7, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v4, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v4.h, 8, v7.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v1, v2
-; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v4.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v1.l, v0.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v2, v4
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v4.l, v0.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v1, v2
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v4.h
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.h
; GFX11-DL-TRUE16-NEXT: global_store_b16 v3, v0, s[4:5]
; GFX11-DL-TRUE16-NEXT: s_endpgm
;
@@ -3375,29 +3372,30 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 8, v3
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v3, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v3, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.h
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v0, 0, 8
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v4.l
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v4
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v4.h
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v4
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v1.l
-; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v7.l
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v0.h, v0.l
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v3.l, v0.l
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v4.l, v0.l
; GFX11-DL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-DL-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5]
; GFX11-DL-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 5e6c34c085aa41..3f2c70790fd56a 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -1949,25 +1949,24 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v4
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v7, v4, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v4, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h
; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v6, 0, 8
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l
-; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v8.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v1.h, v0.l
-; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8
+; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.h
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v1.h, v0.l
+; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v0.h, v0.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v3.l, v1.l, v0.l
; GFX11-DL-TRUE16-NEXT: global_store_b16 v5, v0, s[4:5]
@@ -2428,26 +2427,22 @@ define amdgpu_kernel void @udot4_acc16_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b16 v5.h, 8, v2.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v1.l
; GFX11-DL-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v2.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 24, v2
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 24, v1
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
+; GFX11-DL-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.h
; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v4, v4, v5
-; GFX11-DL-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v6.l
-; GFX11-DL-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v7.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
-; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
+; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.h, v7.l
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v4.l, v0.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v2, v5, v6
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v4.l, v0.l
+; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v1, v2
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v4.h
; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.h
; GFX11-DL-TRUE16-NEXT: global_store_b16 v3, v0, s[4:5]
; GFX11-DL-TRUE16-NEXT: s_endpgm
;
@@ -2705,30 +2700,28 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-TRUE16-NEXT: global_load_b32 v4, v0, s[2:3]
; GFX11-DL-TRUE16-NEXT: global_load_d16_u8 v0, v5, s[4:5]
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 24, v3
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v4
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v4
; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-DL-TRUE16-NEXT: v_lshrrev_b16 v0.h, 8, v3.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v4.l
+; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v1.l, v3.h, v4.h
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b16 v1.h, 8, v4.l
; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v1.h, v2.l, v7.l
-; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v2.l, v6.l, v8.l
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.h, v0.h, v1.l
-; GFX11-DL-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v1.h
-; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
-; GFX11-DL-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
+; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v2.l, v2.l, v6.l
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.h, v0.h, v1.h
+; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-DL-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX11-DL-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v0.h
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v7.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-DL-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v2.l
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v6
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v7
-; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v6.l, v8.l, v0.l
+; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
+; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v3.h, v4.h, v0.l
; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
; GFX11-DL-TRUE16-NEXT: global_store_b8 v5, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
index 1526d59749a1f3..325110e2e8cbd6 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
@@ -254,14 +254,11 @@ define amdgpu_kernel void @v_insertelement_v2bf16_0(ptr addrspace(1) %out, ptr a
; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-REAL16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v2.l, 0x40a0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX1250-REAL16-NEXT: global_store_b32 v0, v2, s[0:1] scale_offset
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, 0x40a0
+; GFX1250-REAL16-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64
@@ -360,14 +357,11 @@ define amdgpu_kernel void @v_insertelement_v2bf16_0_inlineimm(ptr addrspace(1) %
; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-REAL16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v2.l, 53
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX1250-REAL16-NEXT: global_store_b32 v0, v2, s[0:1] scale_offset
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, 53
+; GFX1250-REAL16-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64
@@ -816,10 +810,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_0(ptr addrspace(1) %out, ptr a
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b64 v[0:1], v2, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, s4
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX1250-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -1051,10 +1042,7 @@ define amdgpu_kernel void @v_insertelement_v4bf16_2(ptr addrspace(1) %out, ptr a
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b64 v[0:1], v2, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX1250-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
@@ -1686,40 +1674,38 @@ define amdgpu_kernel void @v_insertelement_v8bf16_dynamic(ptr addrspace(1) %out,
; GFX1250-REAL16-NEXT: v_nop
; GFX1250-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-REAL16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
-; GFX1250-REAL16-NEXT: v_and_b32_e32 v6, 0x3ff, v0
+; GFX1250-REAL16-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-REAL16-NEXT: s_wait_xcnt 0x0
; GFX1250-REAL16-NEXT: s_load_b64 s[4:5], s[4:5], 0x10 nv
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: global_load_b128 v[0:3], v6, s[2:3] scale_offset
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 6
+; GFX1250-REAL16-NEXT: global_load_b128 v[0:3], v4, s[2:3] scale_offset
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 7
; GFX1250-REAL16-NEXT: s_wait_xcnt 0x0
; GFX1250-REAL16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 7
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 6
; GFX1250-REAL16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 4
-; GFX1250-REAL16-NEXT: s_cselect_b32 s6, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 5
+; GFX1250-REAL16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 4
; GFX1250-REAL16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 2
-; GFX1250-REAL16-NEXT: s_cselect_b32 s8, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 3
+; GFX1250-REAL16-NEXT: s_cselect_b32 s8, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 2
; GFX1250-REAL16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 0
-; GFX1250-REAL16-NEXT: s_cselect_b32 s10, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 1
+; GFX1250-REAL16-NEXT: s_cselect_b32 s10, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 0
; GFX1250-REAL16-NEXT: s_cselect_b32 s5, -1, 0
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v5.l, v3.l, s4, s2
-; GFX1250-REAL16-NEXT: v_dual_lshrrev_b32 v7, 16, v3 :: v_dual_lshrrev_b32 v8, 16, v2
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.l, v1.l, s4, s8
-; GFX1250-REAL16-NEXT: v_dual_lshrrev_b32 v1, 16, v1 :: v_dual_lshrrev_b32 v9, 16, v0
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v4.l, v2.l, s4, s6
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.l, v0.l, s4, s10
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v5.h, v7.l, s4, s3
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v4.h, v8.l, s4, s7
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.h, v1.l, s4, s9
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.h, v9.l, s4, s5
-; GFX1250-REAL16-NEXT: global_store_b128 v6, v[2:5], s[0:1] scale_offset
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.h, v3.h, s4, s2
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.l, v3.l, s4, s3
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.h, v2.h, s4, s6
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.l, v2.l, s4, s7
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.h, v1.h, s4, s8
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.l, v1.l, s4, s9
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.h, v0.h, s4, s10
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.l, v0.l, s4, s5
+; GFX1250-REAL16-NEXT: global_store_b128 v4, v[0:3], s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64
@@ -2335,71 +2321,65 @@ define amdgpu_kernel void @v_insertelement_v16bf16_dynamic(ptr addrspace(1) %out
; GFX1250-REAL16-NEXT: s_wait_xcnt 0x0
; GFX1250-REAL16-NEXT: s_load_b64 s[4:5], s[4:5], 0x10 nv
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v12, 5, v0
+; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v8, 5, v0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: s_clause 0x1
-; GFX1250-REAL16-NEXT: global_load_b128 v[0:3], v12, s[2:3]
-; GFX1250-REAL16-NEXT: global_load_b128 v[4:7], v12, s[2:3] offset:16
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 6
+; GFX1250-REAL16-NEXT: global_load_b128 v[0:3], v8, s[2:3]
+; GFX1250-REAL16-NEXT: global_load_b128 v[4:7], v8, s[2:3] offset:16
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 7
; GFX1250-REAL16-NEXT: s_wait_xcnt 0x0
; GFX1250-REAL16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 7
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 6
; GFX1250-REAL16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 4
-; GFX1250-REAL16-NEXT: s_cselect_b32 s6, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 5
+; GFX1250-REAL16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 4
; GFX1250-REAL16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 2
-; GFX1250-REAL16-NEXT: s_cselect_b32 s8, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 3
+; GFX1250-REAL16-NEXT: s_cselect_b32 s8, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 2
; GFX1250-REAL16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 0
-; GFX1250-REAL16-NEXT: s_cselect_b32 s10, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 1
+; GFX1250-REAL16-NEXT: s_cselect_b32 s10, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 0
; GFX1250-REAL16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 14
-; GFX1250-REAL16-NEXT: s_cselect_b32 s12, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 15
+; GFX1250-REAL16-NEXT: s_cselect_b32 s12, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 14
; GFX1250-REAL16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 12
-; GFX1250-REAL16-NEXT: s_cselect_b32 s14, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 13
+; GFX1250-REAL16-NEXT: s_cselect_b32 s14, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 12
; GFX1250-REAL16-NEXT: s_cselect_b32 s15, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 10
-; GFX1250-REAL16-NEXT: s_cselect_b32 s16, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 11
+; GFX1250-REAL16-NEXT: s_cselect_b32 s16, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 10
; GFX1250-REAL16-NEXT: s_cselect_b32 s17, -1, 0
-; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 8
-; GFX1250-REAL16-NEXT: s_cselect_b32 s18, -1, 0
; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 9
+; GFX1250-REAL16-NEXT: s_cselect_b32 s18, -1, 0
+; GFX1250-REAL16-NEXT: s_cmp_eq_u32 s5, 8
; GFX1250-REAL16-NEXT: s_cselect_b32 s5, -1, 0
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x1
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v11.l, v3.l, s4, s2
-; GFX1250-REAL16-NEXT: v_dual_lshrrev_b32 v13, 16, v3 :: v_dual_lshrrev_b32 v14, 16, v2
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v10.l, v2.l, s4, s6
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v9.l, v1.l, s4, s8
-; GFX1250-REAL16-NEXT: v_dual_lshrrev_b32 v15, 16, v1 :: v_dual_lshrrev_b32 v16, 16, v0
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v8.l, v0.l, s4, s10
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.h, v3.h, s4, s2
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.l, v7.l, s4, s12
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.l, v6.l, s4, s14
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.l, v5.l, s4, s16
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.l, v4.l, s4, s18
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.h, v7.l, s4, s13
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.h, v6.l, s4, s15
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.h, v5.l, s4, s17
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v11.h, v13.l, s4, s3
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.h, v4.l, s4, s5
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v10.h, v14.l, s4, s7
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v9.h, v15.l, s4, s9
-; GFX1250-REAL16-NEXT: v_cndmask_b16 v8.h, v16.l, s4, s11
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v7.h, v7.h, s4, s12
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v7.l, v7.l, s4, s13
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v6.h, v6.h, s4, s14
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v6.l, v6.l, s4, s15
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v5.h, v5.h, s4, s16
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v5.l, v5.l, s4, s17
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v4.h, v4.h, s4, s18
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v4.l, v4.l, s4, s5
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v3.l, v3.l, s4, s3
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.h, v2.h, s4, s6
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v2.l, v2.l, s4, s7
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.h, v1.h, s4, s8
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v1.l, v1.l, s4, s9
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.h, v0.h, s4, s10
+; GFX1250-REAL16-NEXT: v_cndmask_b16 v0.l, v0.l, s4, s11
; GFX1250-REAL16-NEXT: s_clause 0x1
-; GFX1250-REAL16-NEXT: global_store_b128 v12, v[0:3], s[0:1] offset:16
-; GFX1250-REAL16-NEXT: global_store_b128 v12, v[8:11], s[0:1]
+; GFX1250-REAL16-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX1250-REAL16-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tid.ext = sext i32 %tid to i64
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
index 7bccc761fc5bbd..42fe4831c8c381 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -753,15 +753,13 @@ define amdgpu_kernel void @v_insertelement_v2i16_0(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3e7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3e7
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v2i16_0:
@@ -850,17 +848,14 @@ define amdgpu_kernel void @v_insertelement_v2i16_0_reghi(ptr addrspace(1) %out,
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: s_load_b32 s4, s[4:5], 0x10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v2i16_0_reghi:
@@ -947,15 +942,13 @@ define amdgpu_kernel void @v_insertelement_v2i16_0_inlineimm(ptr addrspace(1) %o
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 53
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 53
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v2i16_0_inlineimm:
@@ -1223,15 +1216,13 @@ define amdgpu_kernel void @v_insertelement_v2f16_0(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x4500
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x4500
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v2f16_0:
@@ -1316,15 +1307,13 @@ define amdgpu_kernel void @v_insertelement_v2f16_0_inlineimm(ptr addrspace(1) %o
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 53
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
-; GFX11-TRUE16-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 53
+; GFX11-TRUE16-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v2f16_0_inlineimm:
@@ -1890,10 +1879,7 @@ define amdgpu_kernel void @v_insertelement_v4f16_0(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2090,10 +2076,7 @@ define amdgpu_kernel void @v_insertelement_v4f16_2(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2290,10 +2273,7 @@ define amdgpu_kernel void @v_insertelement_v4i16_2(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2712,10 +2692,7 @@ define amdgpu_kernel void @v_insertelement_v8i16_6(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
; GFX11-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2912,39 +2889,35 @@ define amdgpu_kernel void @v_insertelement_v8f16_dynamic(ptr addrspace(1) %out,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 4, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v5, s[2:3]
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 6
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v4, s[2:3]
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 7
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 6
; GFX11-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 4
-; GFX11-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 5
+; GFX11-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 4
; GFX11-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 2
-; GFX11-TRUE16-NEXT: s_cselect_b32 s8, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 3
+; GFX11-TRUE16-NEXT: s_cselect_b32 s8, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 2
; GFX11-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s10, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 1
+; GFX11-TRUE16-NEXT: s_cselect_b32 s10, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.l, s4, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v2.l, s4, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, s4, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, s4, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v6.l, s4, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.l, s4, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v8.l, s4, s9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.l, s4, s5
-; GFX11-TRUE16-NEXT: global_store_b128 v5, v[1:4], s[0:1]
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, s4, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, s4, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, s4, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, s4, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, s4, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, s4, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, s4, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, s4, s5
+; GFX11-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v8f16_dynamic:
@@ -3215,17 +3188,13 @@ define amdgpu_kernel void @v_insertelement_v16i16_6(ptr addrspace(1) %out, ptr a
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 5, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v8, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v8, s[2:3] offset:16
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
+; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v8, s[2:3] offset:16
+; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v8, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, s4
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
-; GFX11-TRUE16-NEXT: global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
+; GFX11-TRUE16-NEXT: global_store_b128 v8, v[4:7], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v16i16_6:
@@ -3553,72 +3522,64 @@ define amdgpu_kernel void @v_insertelement_v16f16_dynamic(ptr addrspace(1) %out,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 5, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 5, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v12, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v12, s[2:3] offset:16
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 6
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v8, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v8, s[2:3] offset:16
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 7
+; GFX11-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 6
; GFX11-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 4
-; GFX11-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 5
+; GFX11-TRUE16-NEXT: s_cselect_b32 s6, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 4
; GFX11-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 2
-; GFX11-TRUE16-NEXT: s_cselect_b32 s8, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 3
+; GFX11-TRUE16-NEXT: s_cselect_b32 s8, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 2
; GFX11-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s10, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 1
+; GFX11-TRUE16-NEXT: s_cselect_b32 s10, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 0
; GFX11-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 14
-; GFX11-TRUE16-NEXT: s_cselect_b32 s12, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 15
+; GFX11-TRUE16-NEXT: s_cselect_b32 s12, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 14
; GFX11-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 12
-; GFX11-TRUE16-NEXT: s_cselect_b32 s14, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 13
+; GFX11-TRUE16-NEXT: s_cselect_b32 s14, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 12
; GFX11-TRUE16-NEXT: s_cselect_b32 s15, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 10
-; GFX11-TRUE16-NEXT: s_cselect_b32 s16, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 11
+; GFX11-TRUE16-NEXT: s_cselect_b32 s16, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 10
; GFX11-TRUE16-NEXT: s_cselect_b32 s17, -1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 8
-; GFX11-TRUE16-NEXT: s_cselect_b32 s18, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 9
+; GFX11-TRUE16-NEXT: s_cselect_b32 s18, -1, 0
+; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s5, 8
; GFX11-TRUE16-NEXT: s_cselect_b32 s5, -1, 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v3.l, s4, s2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.l, s4, s6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v1.l, s4, s8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v0.l, s4, s10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.h, s4, s2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, s4, s12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, s4, s14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, s4, s16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, s4, s18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.l, s4, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.l, s4, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, s4, s17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v13.l, s4, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, s4, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v14.l, s4, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v15.l, s4, s9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v16.l, s4, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.h, s4, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, s4, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.h, s4, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, s4, s15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.h, s4, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, s4, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.h, s4, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, s4, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, s4, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.h, s4, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, s4, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, s4, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, s4, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, s4, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, s4, s11
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_store_b128 v12, v[0:3], s[0:1] offset:16
-; GFX11-TRUE16-NEXT: global_store_b128 v12, v[8:11], s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX11-TRUE16-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_insertelement_v16f16_dynamic:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
index c8e0c273bde2ef..81d915ec6212d2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
@@ -722,9 +722,7 @@ define amdgpu_ps float @test_cvt_pk_f16_fp8_v_hi(<2 x i16> %a) {
; GFX1250-SDAG-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SDAG-REAL16-NEXT: v_nop
; GFX1250-SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SDAG-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.l
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_f16_fp8 v0, v0.h
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_f16_fp8_v_hi:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
index 9ac0bf4647b76a..0e998656de5679 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
@@ -647,10 +647,8 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX1250-SDAG-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SDAG-REAL16-NEXT: v_nop
; GFX1250-SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
-; GFX1250-SDAG-REAL16-NEXT: v_mov_b32_e32 v4, v3
-; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1
+; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
@@ -691,13 +689,11 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
;
-; GFX13-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
-; GFX13-SDAG-REAL16: ; %bb.0:
-; GFX13-SDAG-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX13-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX13-SDAG-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.l, v1
-; GFX13-SDAG-REAL16-NEXT: global_store_b32 v[3:4], v2, off
-; GFX13-SDAG-REAL16-NEXT: s_endpgm
+; GFX13-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
+; GFX13-REAL16: ; %bb.0:
+; GFX13-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.h, v1
+; GFX13-REAL16-NEXT: global_store_b32 v[3:4], v2, off
+; GFX13-REAL16-NEXT: s_endpgm
;
; GFX13-FAKE16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
; GFX13-FAKE16: ; %bb.0:
@@ -706,12 +702,6 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX13-FAKE16-NEXT: v_cvt_sr_bf8_f16 v2, v0, v1
; GFX13-FAKE16-NEXT: global_store_b32 v[3:4], v2, off
; GFX13-FAKE16-NEXT: s_endpgm
-;
-; GFX13-GISEL-REAL16-LABEL: test_cvt_sr_bf8_f16_hi_byte0:
-; GFX13-GISEL-REAL16: ; %bb.0:
-; GFX13-GISEL-REAL16-NEXT: v_cvt_sr_bf8_f16 v2, v0.h, v1
-; GFX13-GISEL-REAL16-NEXT: global_store_b32 v[3:4], v2, off
-; GFX13-GISEL-REAL16-NEXT: s_endpgm
%a.1 = extractelement <2 x half> %a, i32 1
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a.1, i32 %sr, i32 %old, i32 0)
store i32 %cvt, ptr addrspace(1) %out
@@ -1002,10 +992,8 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX1250-SDAG-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SDAG-REAL16-NEXT: v_nop
; GFX1250-SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_lshrrev_b32 v0, 16, v0
-; GFX1250-SDAG-REAL16-NEXT: v_mov_b32_e32 v4, v3
-; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1
+; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.h, v1
; GFX1250-SDAG-REAL16-NEXT: global_store_b32 v[4:5], v2, off
; GFX1250-SDAG-REAL16-NEXT: s_endpgm
;
@@ -1046,13 +1034,11 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX1250-GISEL-FAKE16-NEXT: global_store_b32 v[6:7], v2, off
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
;
-; GFX13-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
-; GFX13-SDAG-REAL16: ; %bb.0:
-; GFX13-SDAG-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX13-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX13-SDAG-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.l, v1
-; GFX13-SDAG-REAL16-NEXT: global_store_b32 v[3:4], v2, off
-; GFX13-SDAG-REAL16-NEXT: s_endpgm
+; GFX13-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
+; GFX13-REAL16: ; %bb.0:
+; GFX13-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.h, v1
+; GFX13-REAL16-NEXT: global_store_b32 v[3:4], v2, off
+; GFX13-REAL16-NEXT: s_endpgm
;
; GFX13-FAKE16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
; GFX13-FAKE16: ; %bb.0:
@@ -1061,14 +1047,11 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
; GFX13-FAKE16-NEXT: v_cvt_sr_fp8_f16 v2, v0, v1
; GFX13-FAKE16-NEXT: global_store_b32 v[3:4], v2, off
; GFX13-FAKE16-NEXT: s_endpgm
-;
-; GFX13-GISEL-REAL16-LABEL: test_cvt_sr_fp8_f16_hi_byte0:
-; GFX13-GISEL-REAL16: ; %bb.0:
-; GFX13-GISEL-REAL16-NEXT: v_cvt_sr_fp8_f16 v2, v0.h, v1
-; GFX13-GISEL-REAL16-NEXT: global_store_b32 v[3:4], v2, off
-; GFX13-GISEL-REAL16-NEXT: s_endpgm
%a.1 = extractelement <2 x half> %a, i32 1
%cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a.1, i32 %sr, i32 %old, i32 0)
store i32 %cvt, ptr addrspace(1) %out
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX13-GISEL-REAL16: {{.*}}
+; GFX13-SDAG-REAL16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index e0201c807ca706..e1992331061aa5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -50,9 +50,7 @@ define float @v_fdot2_f32_bf16_neg_a_lo(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_lo:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-SDAG: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SDAG: v_mov_b16_e32 v0.h, v3.l
; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_lo:
@@ -64,9 +62,7 @@ define float @v_fdot2_f32_bf16_neg_a_lo(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_lo:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-SDAG: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX12-SDAG: v_mov_b16_e32 v0.h, v3.l
; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_lo:
@@ -105,8 +101,7 @@ define float @v_fdot2_f32_bf16_neg_a_hi(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_hi:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG: v_xor_b16 v0.h, 0x8000, v3.l
+; GFX11-SDAG: v_xor_b16 v0.h, 0x8000, v0.h
; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_hi:
@@ -119,8 +114,7 @@ define float @v_fdot2_f32_bf16_neg_a_hi(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_hi:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-SDAG: v_xor_b16 v0.h, 0x8000, v3.l
+; GFX12-SDAG: v_xor_b16 v0.h, 0x8000, v0.h
; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_hi:
@@ -166,9 +160,7 @@ define float @v_fdot2_f32_bf16_neg_b_lo(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_lo:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-SDAG: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX11-SDAG: v_mov_b16_e32 v1.h, v3.l
; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_lo:
@@ -180,9 +172,7 @@ define float @v_fdot2_f32_bf16_neg_b_lo(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_lo:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v3, 16, v1
; GFX12-SDAG: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX12-SDAG: v_mov_b16_e32 v1.h, v3.l
; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_lo:
@@ -221,8 +211,7 @@ define float @v_fdot2_f32_bf16_neg_b_hi(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_hi:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-SDAG: v_xor_b16 v1.h, 0x8000, v3.l
+; GFX11-SDAG: v_xor_b16 v1.h, 0x8000, v1.h
; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_hi:
@@ -235,8 +224,7 @@ define float @v_fdot2_f32_bf16_neg_b_hi(<2 x bfloat> %a, <2 x bfloat> %b, float
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_hi:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-SDAG: v_xor_b16 v1.h, 0x8000, v3.l
+; GFX12-SDAG: v_xor_b16 v1.h, 0x8000, v1.h
; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_hi:
@@ -279,27 +267,10 @@ define float @v_fdot2_f32_bf16_opsel_lo_a(<2 x bfloat> %a, <2 x bfloat> %b, floa
; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
; GFX950: v_mov_b32_e32 v0, v2
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX11-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX12-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v0.l, v0.h
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2
%shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 false)
ret float %r
@@ -337,27 +308,10 @@ define float @v_fdot2_f32_bf16_opsel_lo_b(<2 x bfloat> %a, <2 x bfloat> %b, floa
; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
; GFX950: v_mov_b32_e32 v0, v2
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX11-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX12-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v1.l, v1.h
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2
%shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 false)
ret float %r
@@ -478,27 +432,10 @@ define float @v_fdot2_f32_bf16_opsel_lo_a_clamp(<2 x bfloat> %a, <2 x bfloat> %b
; GFX950: v_perm_b32 v0, v0, v0, s0
; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX11-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX12-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v0.l, v0.h
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
%shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 true)
ret float %r
@@ -533,27 +470,10 @@ define float @v_fdot2_f32_bf16_opsel_lo_b_clamp(<2 x bfloat> %a, <2 x bfloat> %b
; GFX950: v_perm_b32 v1, v1, v1, s0
; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX11-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX11-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX12-SDAG: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX12-GISEL: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v1.l, v1.h
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
%shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 true)
ret float %r
@@ -791,11 +711,8 @@ define float @v_fdot2_f32_bf16_neg_a_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_lo_dual:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-SDAG: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_mov_b16_e32 v0.h, v6.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_lo_dual:
@@ -809,11 +726,8 @@ define float @v_fdot2_f32_bf16_neg_a_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_lo_dual:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v6, 16, v0
; GFX12-SDAG: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_mov_b16_e32 v0.h, v6.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX12-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_lo_dual:
@@ -858,10 +772,8 @@ define float @v_fdot2_f32_bf16_neg_a_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_hi_dual:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_xor_b16 v0.h, 0x8000, v6.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11-SDAG: v_xor_b16 v0.h, 0x8000, v0.h
+; GFX11-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_hi_dual:
@@ -876,10 +788,8 @@ define float @v_fdot2_f32_bf16_neg_a_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_a_hi_dual:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_xor_b16 v0.h, 0x8000, v6.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX12-SDAG: v_xor_b16 v0.h, 0x8000, v0.h
+; GFX12-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_a_hi_dual:
@@ -941,11 +851,8 @@ define float @v_fdot2_f32_bf16_neg_b_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_lo_dual:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-SDAG: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_mov_b16_e32 v1.h, v6.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_lo_dual:
@@ -959,11 +866,8 @@ define float @v_fdot2_f32_bf16_neg_b_lo_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_lo_dual:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v6, 16, v1
; GFX12-SDAG: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_mov_b16_e32 v1.h, v6.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX12-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_lo_dual:
@@ -1008,10 +912,8 @@ define float @v_fdot2_f32_bf16_neg_b_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_hi_dual:
; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_xor_b16 v1.h, 0x8000, v6.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX11-SDAG: v_xor_b16 v1.h, 0x8000, v1.h
+; GFX11-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_hi_dual:
@@ -1026,10 +928,8 @@ define float @v_fdot2_f32_bf16_neg_b_hi_dual(<2 x bfloat> %a, <2 x bfloat> %b, f
;
; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_neg_b_hi_dual:
; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_xor_b16 v1.h, 0x8000, v6.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
+; GFX12-SDAG: v_xor_b16 v1.h, 0x8000, v1.h
+; GFX12-SDAG: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
;
; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_neg_b_hi_dual:
@@ -1097,33 +997,11 @@ define float @v_fdot2_f32_bf16_opsel_lo_a_dual(<2 x bfloat> %a, <2 x bfloat> %b,
; GFX950: v_dot2c_f32_bf16_e32 v5, v3, v4
; GFX950: v_add_f32_e32 v0, v2, v5
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a_dual:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
-; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a_dual:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX11-GISEL: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
-; GFX11-GISEL: v_add_f32_e32 v0, v2, v5
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_a_dual:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v0, 16, v0
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_mov_b16_e32 v0.h, v0.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
-; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_a_dual:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v0.l, v0.h
-; GFX12-GISEL: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
-; GFX12-GISEL: v_add_f32_e32 v0, v2, v5
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_a_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v0.l, v0.h
+; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
%shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 false)
%r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
@@ -1169,33 +1047,11 @@ define float @v_fdot2_f32_bf16_opsel_lo_b_dual(<2 x bfloat> %a, <2 x bfloat> %b,
; GFX950: v_dot2c_f32_bf16_e32 v5, v3, v4
; GFX950: v_add_f32_e32 v0, v2, v5
;
-; GFX11-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b_dual:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX11-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX11-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
-; GFX11-SDAG: v_add_f32_e32 v0, v2, v5
-;
-; GFX11-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b_dual:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX11-GISEL: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
-; GFX11-GISEL: v_add_f32_e32 v0, v2, v5
-;
-; GFX12-SDAG-LABEL: v_fdot2_f32_bf16_opsel_lo_b_dual:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG: v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-SDAG: v_dot2_f32_bf16 v5, v3, v4, v5
-; GFX12-SDAG: v_mov_b16_e32 v1.h, v1.l
-; GFX12-SDAG: v_dot2_f32_bf16 v2, v0, v1, v2
-; GFX12-SDAG: v_add_f32_e32 v0, v2, v5
-;
-; GFX12-GISEL-LABEL: v_fdot2_f32_bf16_opsel_lo_b_dual:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL: v_mov_b16_e32 v1.l, v1.h
-; GFX12-GISEL: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
-; GFX12-GISEL: v_add_f32_e32 v0, v2, v5
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_opsel_lo_b_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v1.l, v1.h
+; GFX11PLUS: v_dual_dot2acc_f32_bf16 v5, v3, v4 :: v_dual_dot2acc_f32_bf16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
%shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
%r0 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 false)
%r1 = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %d, <2 x bfloat> %e, float %f, i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
index e6e03afad3db6f..086101cd610d20 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
@@ -63,19 +63,20 @@ define float @v_fdot2_neg_a_lo(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_neg_a_lo:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v3, 16, v0
; GFX11: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11: v_mov_b16_e32 v0.h, v3.l
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_neg_a_lo:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_xor_b16 v0.l, 0x8000, v0.l
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_neg_a_lo:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v3, 16, v0
; GFX1170: v_xor_b16 v0.l, 0x8000, v0.l
; GFX1170: v_mov_b16_e32 v0.h, v3.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_neg_a_lo:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v3, 16, v0
@@ -109,17 +110,19 @@ define float @v_fdot2_neg_a_hi(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_neg_a_hi:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11: v_xor_b16 v0.h, 0x8000, v3.l
+; GFX11: v_xor_b16 v0.h, 0x8000, v0.h
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_neg_a_hi:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_xor_b16 v0.h, 0x8000, v0.h
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_neg_a_hi:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v3, 16, v0
; GFX1170: v_xor_b16 v0.h, 0x8000, v3.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_neg_a_hi:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v3, 16, v0
@@ -160,19 +163,20 @@ define float @v_fdot2_neg_b_lo(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_neg_b_lo:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v3, 16, v1
; GFX11: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX11: v_mov_b16_e32 v1.h, v3.l
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_neg_b_lo:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_xor_b16 v1.l, 0x8000, v1.l
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_neg_b_lo:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v3, 16, v1
; GFX1170: v_xor_b16 v1.l, 0x8000, v1.l
; GFX1170: v_mov_b16_e32 v1.h, v3.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_neg_b_lo:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v3, 16, v1
@@ -206,17 +210,19 @@ define float @v_fdot2_neg_b_hi(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_neg_b_hi:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11: v_xor_b16 v1.h, 0x8000, v3.l
+; GFX11: v_xor_b16 v1.h, 0x8000, v1.h
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_neg_b_hi:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_xor_b16 v1.h, 0x8000, v1.h
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_neg_b_hi:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v3, 16, v1
; GFX1170: v_xor_b16 v1.h, 0x8000, v3.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_neg_b_hi:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v3, 16, v1
@@ -265,17 +271,19 @@ define float @v_fdot2_opsel_lo_a(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_opsel_lo_a:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11: v_mov_b16_e32 v0.h, v0.l
+; GFX11: v_mov_b16_e32 v0.l, v0.h
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_opsel_lo_a:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_mov_b16_e32 v0.l, v0.h
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_opsel_lo_a:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v0, 16, v0
; GFX1170: v_mov_b16_e32 v0.h, v0.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_opsel_lo_a:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v0, 16, v0
@@ -335,17 +343,19 @@ define float @v_fdot2_opsel_lo_b(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11-LABEL: v_fdot2_opsel_lo_b:
; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11: v_mov_b16_e32 v1.h, v1.l
+; GFX11: v_mov_b16_e32 v1.l, v1.h
; GFX11: v_dot2acc_f32_f16 v2, v0, v1
; GFX11: v_mov_b32_e32 v0, v2
;
+; GFX1170-GFX12-LABEL: v_fdot2_opsel_lo_b:
+; GFX1170-GFX12: ; %bb.0:
+; GFX1170-GFX12: v_mov_b16_e32 v1.l, v1.h
+; GFX1170-GFX12: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170-LABEL: v_fdot2_opsel_lo_b:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v1, 16, v1
; GFX1170: v_mov_b16_e32 v1.h, v1.l
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
-;
; GFX12-LABEL: v_fdot2_opsel_lo_b:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v1, 16, v1
@@ -532,8 +542,7 @@ define float @v_fdot2_opsel_lo_a_clamp(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11PLUS-LABEL: v_fdot2_opsel_lo_a_clamp:
; GFX11PLUS: ; %bb.0:
-; GFX11PLUS: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11PLUS: v_mov_b16_e32 v0.h, v0.l
+; GFX11PLUS: v_mov_b16_e32 v0.l, v0.h
; GFX11PLUS: v_dot2_f32_f16 v0, v0, v1, v2 clamp
%shuf = shufflevector <2 x half> %a, <2 x half> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2(<2 x half> %shuf, <2 x half> %b, float %c, i1 true)
@@ -581,8 +590,7 @@ define float @v_fdot2_opsel_lo_b_clamp(<2 x half> %a, <2 x half> %b, float %c) {
;
; GFX11PLUS-LABEL: v_fdot2_opsel_lo_b_clamp:
; GFX11PLUS: ; %bb.0:
-; GFX11PLUS: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11PLUS: v_mov_b16_e32 v1.h, v1.l
+; GFX11PLUS: v_mov_b16_e32 v1.l, v1.h
; GFX11PLUS: v_dot2_f32_f16 v0, v0, v1, v2 clamp
%shuf = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> <i32 1, i32 1>
%r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %shuf, float %c, i1 true)
@@ -955,15 +963,11 @@ define float @v_fdot2_neg_a_lo_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_neg_a_lo_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_mov_b16_e32 v0.h, v6.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_neg_a_lo_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_xor_b16 v0.l, 0x8000, v0.l
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_neg_a_lo_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v6, 16, v0
@@ -972,7 +976,6 @@ define float @v_fdot2_neg_a_lo_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_neg_a_lo_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v6, 16, v0
@@ -1013,14 +1016,11 @@ define float @v_fdot2_neg_a_hi_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_neg_a_hi_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_xor_b16 v0.h, 0x8000, v6.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_neg_a_hi_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_xor_b16 v0.h, 0x8000, v0.h
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_neg_a_hi_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v6, 16, v0
@@ -1028,7 +1028,6 @@ define float @v_fdot2_neg_a_hi_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_neg_a_hi_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v6, 16, v0
@@ -1104,15 +1103,11 @@ define float @v_fdot2_neg_b_lo_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_neg_b_lo_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_mov_b16_e32 v1.h, v6.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_neg_b_lo_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_xor_b16 v1.l, 0x8000, v1.l
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_neg_b_lo_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v6, 16, v1
@@ -1121,7 +1116,6 @@ define float @v_fdot2_neg_b_lo_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_neg_b_lo_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v6, 16, v1
@@ -1162,14 +1156,11 @@ define float @v_fdot2_neg_b_hi_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_neg_b_hi_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_xor_b16 v1.h, 0x8000, v6.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_neg_b_hi_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_xor_b16 v1.h, 0x8000, v1.h
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_neg_b_hi_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v6, 16, v1
@@ -1177,7 +1168,6 @@ define float @v_fdot2_neg_b_hi_dual(<2 x half> %a, <2 x half> %b, float %c, <2 x
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_neg_b_hi_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v6, 16, v1
@@ -1289,14 +1279,11 @@ define float @v_fdot2_opsel_lo_a_dual(<2 x half> %a, <2 x half> %b, float %c, <2
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_opsel_lo_a_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_mov_b16_e32 v0.h, v0.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_opsel_lo_a_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v0.l, v0.h
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_opsel_lo_a_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v0, 16, v0
@@ -1304,7 +1291,6 @@ define float @v_fdot2_opsel_lo_a_dual(<2 x half> %a, <2 x half> %b, float %c, <2
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_opsel_lo_a_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v0, 16, v0
@@ -1373,14 +1359,11 @@ define float @v_fdot2_opsel_lo_b_dual(<2 x half> %a, <2 x half> %b, float %c, <2
; GFX10: v_dot2c_f32_f16 v5, v3, v4
; GFX10: v_add_f32_e32 v0, v2, v5
;
-; GFX11-LABEL: v_fdot2_opsel_lo_b_dual:
-; GFX11: ; %bb.0:
-; GFX11: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11: v_dot2acc_f32_f16 v5, v3, v4
-; GFX11: v_mov_b16_e32 v1.h, v1.l
-; GFX11: v_dot2acc_f32_f16 v2, v0, v1
-; GFX11: v_add_f32_e32 v0, v2, v5
-;
+; GFX11PLUS-LABEL: v_fdot2_opsel_lo_b_dual:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_mov_b16_e32 v1.l, v1.h
+; GFX11PLUS: v_dual_dot2acc_f32_f16 v5, v3, v4 :: v_dual_dot2acc_f32_f16 v2, v0, v1
+; GFX11PLUS: v_add_f32_e32 v0, v2, v5
; GFX1170-LABEL: v_fdot2_opsel_lo_b_dual:
; GFX1170: ; %bb.0:
; GFX1170: v_lshrrev_b32_e32 v1, 16, v1
@@ -1388,7 +1371,6 @@ define float @v_fdot2_opsel_lo_b_dual(<2 x half> %a, <2 x half> %b, float %c, <2
; GFX1170: v_dot2_f32_f16 v0, v0, v1, v2
; GFX1170: v_dot2_f32_f16 v1, v3, v4, v5
; GFX1170: v_add_f32_e32 v0, v0, v1
-;
; GFX12-LABEL: v_fdot2_opsel_lo_b_dual:
; GFX12: ; %bb.0:
; GFX12: v_lshrrev_b32_e32 v1, 16, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
index 448f56fbbd5892..bb5cf676d6a8d9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
@@ -34,7 +34,7 @@ define bfloat @v_exp2_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_bf16:
@@ -166,7 +166,7 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fabs_bf16:
@@ -305,7 +305,7 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_fabs_bf16:
@@ -445,7 +445,7 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_bf16:
@@ -582,7 +582,7 @@ define bfloat @v_exp2_bf16_fast(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_bf16_fast:
@@ -686,8 +686,8 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -721,10 +721,7 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_v2bf16:
@@ -868,10 +865,8 @@ define <2 x bfloat> @v_exp2_v2bf16(<2 x bfloat> %in) {
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.h, v0.h
; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.l, v0.l
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.h, v1.l
; GFX1250-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: v_exp2_v2bf16:
@@ -920,49 +915,45 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v0.h
; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fabs_v2bf16:
@@ -1115,10 +1106,8 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, |v0.h|
; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.l, |v0.l|
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, |v1.l|
; GFX1250-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: v_exp2_fabs_v2bf16:
@@ -1171,49 +1160,45 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v0.h
; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_fabs_v2bf16:
@@ -1365,10 +1350,8 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, -|v0.h|
; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.l, -|v0.l|
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, -|v1.l|
; GFX1250-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: v_exp2_fneg_fabs_v2bf16:
@@ -1422,49 +1405,45 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v1.l
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v4
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_fneg_v2bf16:
@@ -1616,10 +1595,8 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, -v0.h
; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.l, -v0.l
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e64 v0.h, -v1.l
; GFX1250-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: v_exp2_fneg_v2bf16:
@@ -1672,8 +1649,8 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
@@ -1707,10 +1684,7 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1200-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX1200-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1200-SDAG-FAKE16-LABEL: v_exp2_v2bf16_fast:
@@ -1838,10 +1812,8 @@ define <2 x bfloat> @v_exp2_v2bf16_fast(<2 x bfloat> %in) {
; GFX1250-SDAG-TRUE16: ; %bb.0:
; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.h, v0.h
; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.l, v0.l
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDAG-TRUE16-NEXT: v_exp_bf16_e32 v0.h, v1.l
; GFX1250-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-SDAG-FAKE16-LABEL: v_exp2_v2bf16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index 6ab411182a651a..92219c51d5e159 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -432,15 +432,13 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32:
@@ -465,15 +463,13 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h
+; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32:
@@ -650,10 +646,8 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
@@ -673,10 +667,8 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
@@ -815,12 +807,10 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -843,12 +833,10 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
+; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
index c68099fd26c1e6..3afa0860e60e01 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
@@ -1036,11 +1036,10 @@ define <2 x i1> @isnan_v2bf16(<2 x bfloat> %x) nounwind {
; GFX11SELDAG-TRUE16-LABEL: isnan_v2bf16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1.l
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1.h
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1120,12 +1119,11 @@ define <3 x i1> @isnan_v3bf16(<3 x bfloat> %x) nounwind {
; GFX11SELDAG-TRUE16-LABEL: isnan_v3bf16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v0
; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v1
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2.l
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2.h
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
@@ -1220,17 +1218,15 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX11SELDAG-TRUE16-LABEL: isnan_v4bf16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
-; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v0
+; GFX11SELDAG-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v1
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2.l
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4.l
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2.h
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3.l
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3.h
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 037384edd09062..e172bf63130315 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1409,10 +1409,10 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX11SELDAG-TRUE16-LABEL: isnan_v2f16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v1.l
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.h, v0.h
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1564,13 +1564,12 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX11SELDAG-TRUE16-LABEL: isnan_v3f16:
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v2.l, v2.l
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.h, v0.h
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v1.l
-; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX11SELDAG-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1754,14 +1753,14 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX11SELDAG-TRUE16: ; %bb.0:
; GFX11SELDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.l
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11SELDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.h, v0.h
+; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.l, v1.l
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v4
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v4.l, v4.l
-; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v3.l, v3.l
+; GFX11SELDAG-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v1.h, v1.h
+; GFX11SELDAG-TRUE16-NEXT: v_mov_b32_e32 v1, v5
; GFX11SELDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11SELDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
index 706c78a0fcdaf2..be4e44726a13e6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
@@ -448,11 +448,11 @@ define <2 x half> @test_ldexp_v2f16_v2i32(<2 x half> %a, <2 x i32> %b) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v3.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -579,11 +579,8 @@ define <2 x half> @test_ldexp_v2f16_v2i16(<2 x half> %a, <2 x i16> %b) {
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_v2f16_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v3.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v2f16_v2i16:
@@ -706,14 +703,13 @@ define <3 x half> @test_ldexp_v3f16_v3i32(<3 x half> %a, <3 x i32> %b) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v5.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -865,12 +861,9 @@ define <3 x half> @test_ldexp_v3f16_v3i16(<3 x half> %a, <3 x i16> %b) {
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_v3f16_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v5.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v3f16_v3i16:
@@ -1020,15 +1013,14 @@ define <4 x half> @test_ldexp_v4f16_v4i32(<4 x half> %a, <4 x i32> %b) {
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v5, v5, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v6.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v1.h, v5.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v7.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v4.l
@@ -1217,15 +1209,10 @@ define <4 x half> @test_ldexp_v4f16_v4i16(<4 x half> %a, <4 x i16> %b) {
; GFX11-SDAG-TRUE16-LABEL: test_ldexp_v4f16_v4i16:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v6.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v7.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v4f16_v4i16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 0b8c2a75d68069..7ef23ae493b365 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -7204,17 +7204,15 @@ define <2 x half> @v_log_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v2f16:
@@ -7376,17 +7374,15 @@ define <2 x half> @v_log_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, |v0.l|
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v1.l|
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_fabs_v2f16:
@@ -7554,17 +7550,15 @@ define <2 x half> @v_log_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -|v0.l|
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v1.l|
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_fabs_v2f16:
@@ -7733,17 +7727,15 @@ define <2 x half> @v_log_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_fneg_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_fneg_v2f16:
@@ -7882,13 +7874,11 @@ define <2 x half> @v_log_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v2f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v2f16_fast:
@@ -8063,21 +8053,19 @@ define <3 x half> @v_log_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v3, v0
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, neg(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v3f16:
@@ -8255,15 +8243,14 @@ define <3 x half> @v_log_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v3f16_fast:
@@ -8483,24 +8470,21 @@ define <4 x half> @v_log_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v4f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3f317218
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v4, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v5, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v1, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v1, v3, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v4, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v5, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v4f16:
@@ -8711,19 +8695,16 @@ define <4 x half> @v_log_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v4f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v2.l, v3.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v0.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v1.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x398c, v1.h
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x398c, v2.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x398c, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x398c, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log_v4f16_fast:
@@ -8946,10 +8927,8 @@ define <2 x half> @v_log_v2f16_fpmath(<2 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v2f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x398c, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -9103,13 +9082,10 @@ define <3 x half> @v_log_v3f16_fpmath(<3 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v3f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x398c, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x398c, v1
@@ -9298,13 +9274,10 @@ define <4 x half> @v_log_v4f16_fpmath(<4 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log_v4f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x398c, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x398c, v1 op_sel_hi:[0,1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 8fcc16c2e6f56f..54dfb6b8454e60 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -7204,17 +7204,15 @@ define <2 x half> @v_log10_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v2f16:
@@ -7376,17 +7374,15 @@ define <2 x half> @v_log10_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, |v0.l|
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v1.l|
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_fabs_v2f16:
@@ -7554,17 +7550,15 @@ define <2 x half> @v_log10_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -|v0.l|
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v1.l|
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_fabs_v2f16:
@@ -7733,17 +7727,15 @@ define <2 x half> @v_log10_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_fneg_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v0
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_fneg_v2f16:
@@ -7882,13 +7874,11 @@ define <2 x half> @v_log10_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v2f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v2f16_fast:
@@ -8063,21 +8053,19 @@ define <3 x half> @v_log10_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v3, v0
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, neg(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v3f16:
@@ -8255,15 +8243,14 @@ define <3 x half> @v_log10_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v3f16_fast:
@@ -8483,24 +8470,21 @@ define <4 x half> @v_log10_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v4f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_mov_b32 s0, 0x3e9a209b
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v3.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v2, v2
; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v4, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f32_e32 v5, v1
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v1, v2, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v0, v2, s0, neg(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixhi_f16 v1, v3, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v0, v4, s0, neg(0)
+; GFX1100-SDAG-TRUE16-NEXT: v_fma_mixlo_f16 v1, v5, s0, neg(0)
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v4f16:
@@ -8711,19 +8695,16 @@ define <4 x half> @v_log10_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v4f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v2.l, v3.l
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v0.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v1.h
; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v0.h
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, 0x34d1, v1.h
-; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, 0x34d1, v2.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x34d1, v0.l
+; GFX1100-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, 0x34d1, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log10_v4f16_fast:
@@ -8946,10 +8927,8 @@ define <2 x half> @v_log10_v2f16_fpmath(<2 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v2f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x34d1, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -9103,13 +9082,10 @@ define <3 x half> @v_log10_v3f16_fpmath(<3 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v3f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x34d1, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x34d1, v1
@@ -9298,13 +9274,10 @@ define <4 x half> @v_log10_v4f16_fpmath(<4 x half> %x) {
; GFX1100-SDAG-TRUE16-LABEL: v_log10_v4f16_fpmath:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, 0x34d1, v0 op_sel_hi:[0,1]
; GFX1100-SDAG-TRUE16-NEXT: v_pk_mul_f16 v1, 0x34d1, v1 op_sel_hi:[0,1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
index 61fc2bcadd1ee5..2eb89ca4fcc070 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
@@ -103,10 +103,8 @@ define <2 x bfloat> @v_log2_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.h, v0.h
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.l, v0.l
-; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.h, v1.l
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_v2bf16:
@@ -149,10 +147,8 @@ define <2 x bfloat> @v_log2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, |v0.h|
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, |v0.l|
-; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, |v1.l|
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_fabs_v2bf16:
@@ -200,10 +196,8 @@ define <2 x bfloat> @v_log2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -|v0.h|
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, -|v0.l|
-; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -|v1.l|
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_fneg_fabs_v2bf16:
@@ -252,10 +246,8 @@ define <2 x bfloat> @v_log2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -v0.h
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.l, -v0.l
-; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e64 v0.h, -v1.l
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_fneg_v2bf16:
@@ -303,10 +295,8 @@ define <2 x bfloat> @v_log2_v2bf16_fast(<2 x bfloat> %in) {
; GFX-SDAG-TRUE16: ; %bb.0:
; GFX-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.h, v0.h
; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.l, v0.l
-; GFX-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX-SDAG-TRUE16-NEXT: v_log_bf16_e32 v0.h, v1.l
; GFX-SDAG-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX-SDAG-FAKE16-LABEL: v_log2_v2bf16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index fc4ac9040e7e03..9253ba8d3a1363 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -4228,10 +4228,8 @@ define <2 x half> @v_log2_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v2f16:
@@ -4347,10 +4345,8 @@ define <2 x half> @v_log2_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, |v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, |v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, |v1.l|
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_fabs_v2f16:
@@ -4471,10 +4467,8 @@ define <2 x half> @v_log2_fneg_fabs_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_fabs_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -|v0.h|
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -|v0.l|
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -|v1.l|
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_fabs_v2f16:
@@ -4596,10 +4590,8 @@ define <2 x half> @v_log2_fneg_v2f16(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_fneg_v2f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.l, -v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e64 v0.h, -v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_fneg_v2f16:
@@ -4716,10 +4708,8 @@ define <2 x half> @v_log2_v2f16_fast(<2 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v2f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v2f16_fast:
@@ -4845,11 +4835,9 @@ define <3 x half> @v_log2_v3f16(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16:
@@ -4980,11 +4968,9 @@ define <3 x half> @v_log2_v3f16_fast(<3 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v3f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v3f16_fast:
@@ -5135,13 +5121,10 @@ define <4 x half> @v_log2_v4f16(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v4f16:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v4f16:
@@ -5297,13 +5280,10 @@ define <4 x half> @v_log2_v4f16_fast(<4 x half> %in) {
; GFX1100-SDAG-TRUE16-LABEL: v_log2_v4f16_fast:
; GFX1100-SDAG-TRUE16: ; %bb.0:
; GFX1100-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX1100-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v1.h
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v0.h
; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
-; GFX1100-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v0.h, v2.l
-; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.h, v3.l
+; GFX1100-SDAG-TRUE16-NEXT: v_log_f16_e32 v1.l, v1.l
; GFX1100-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-FAKE16-LABEL: v_log2_v4f16_fast:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
index 50430cac9ee3ba..aac091681f070c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
@@ -800,16 +800,12 @@ define <2 x half> @v_maximum_v2f16(<2 x half> %src0, <2 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v2f16:
@@ -982,16 +978,12 @@ define <2 x half> @v_maximum_v2f16__nsz(<2 x half> %src0, <2 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v2f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v2f16__nsz:
@@ -1338,19 +1330,16 @@ define <3 x half> @v_maximum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v6, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v3f16:
@@ -1555,19 +1544,16 @@ define <3 x half> @v_maximum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v3f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v6, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v3f16__nsz:
@@ -1796,23 +1782,18 @@ define <4 x half> @v_maximum_v4f16(<4 x half> %src0, <4 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v8, v0, v2
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v5, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v5.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v4f16:
@@ -2056,23 +2037,18 @@ define <4 x half> @v_maximum_v4f16__nsz(<4 x half> %src0, <4 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v4f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v8, v0, v2
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v5, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v5.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v4f16__nsz:
@@ -2401,38 +2377,26 @@ define <8 x half> @v_maximum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v8f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.h, v7.h
; GFX11-TRUE16-NEXT: v_pk_max_f16 v8, v3, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v10, v2, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v9, v2, v6
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v10, v0, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v8.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v9.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v5.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v7, v1, v5
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v2.l, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v10.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v7.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v10.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v7.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v9.l, s4
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v12, v0, v4
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v8.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v0.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v12.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v5.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v8f16:
@@ -2864,70 +2828,46 @@ define <16 x half> @v_maximum_v16f16(<16 x half> %src0, <16 x half> %src1) {
; GFX11-TRUE16-LABEL: v_maximum_v16f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v7
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v18, v7, v15
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.h, v15.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v16, v7, v15
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v6.h, v14.h
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v6.l, v14.l
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v19, v5, v13
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v17.l, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v18
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v16, v6, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, 0x7e00, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, 0x7e00, v15.l, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v16.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v13.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v15.l, v14.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v18.l, v17.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v4.l, v12.l
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v15, v4, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v13.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v16.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v11.l
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v13, v3, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v5.h, v13.h
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v5.l, v13.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, 0x7e00, v16.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.l, v15.l
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v15, v6, v14
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v14, v5, v13
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v13, v4, v12
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v1.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, 0x7e00, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v15.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v15.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v14.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v14.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4.h, v12.h
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.h, v11.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v14, v3, v11
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.h, v10.h
; GFX11-TRUE16-NEXT: v_pk_max_f16 v15, v2, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v13.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v14.l, v11.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v16.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v17, v0, v8
-; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v9
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v13.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v0.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s5, v16.l, v14.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v17.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v13.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4.l, v12.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v14.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v11.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v15.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.h, v9.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v11, v1, v9
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v8.h
+; GFX11-TRUE16-NEXT: v_pk_max_f16 v12, v0, v8
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s5, v2.l, v10.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v11.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v11.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v12.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v12.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v15.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v14.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v13.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximum_v16f16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
index 963d4fc819a2a5..fd7fb5351b7dd3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
@@ -691,16 +691,12 @@ define <2 x half> @v_minimum_v2f16(<2 x half> %src0, <2 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v2f16:
@@ -834,16 +830,12 @@ define <2 x half> @v_minimum_v2f16__nsz(<2 x half> %src0, <2 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v2f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v2f16__nsz:
@@ -1120,19 +1112,16 @@ define <3 x half> @v_minimum_v3f16(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v6, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v3f16:
@@ -1288,19 +1277,16 @@ define <3 x half> @v_minimum_v3f16__nsz(<3 x half> %src0, <3 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v3f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v6, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v5.l, v4.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v3f16__nsz:
@@ -1470,23 +1456,18 @@ define <4 x half> @v_minimum_v4f16(<4 x half> %src0, <4 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v8, v0, v2
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v5, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v5.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v4f16:
@@ -1663,23 +1644,18 @@ define <4 x half> @v_minimum_v4f16__nsz(<4 x half> %src0, <4 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v4f16__nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v8, v0, v2
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v5, v0, v2
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v5.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v4f16__nsz:
@@ -1909,38 +1885,26 @@ define <8 x half> @v_minimum_v8f16(<8 x half> %src0, <8 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v8f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.h, v7.h
; GFX11-TRUE16-NEXT: v_pk_min_f16 v8, v3, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v10, v2, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v9, v2, v6
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v4.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v10, v0, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v8.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v9.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.h, v5.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v7, v1, v5
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v1.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v2.l, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v10.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v7.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v10.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v7.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v9.l, s4
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v12, v0, v4
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v8.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v0.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v12.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v5.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v8f16:
@@ -2238,70 +2202,46 @@ define <16 x half> @v_minimum_v16f16(<16 x half> %src0, <16 x half> %src1) {
; GFX11-TRUE16-LABEL: v_minimum_v16f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v7
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v18, v7, v15
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.h, v15.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v16, v7, v15
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v6.h, v14.h
; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v6.l, v14.l
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v19, v5, v13
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v17.l, v16.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v18
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v16, v6, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, 0x7e00, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, 0x7e00, v15.l, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v16.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v13.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v15.l, v14.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v18.l, v17.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v4.l, v12.l
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v15, v4, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v13.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v16.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v11.l
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v13, v3, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v5.h, v13.h
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v5.l, v13.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, 0x7e00, v16.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v7.l, v15.l
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v15, v6, v14
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v14, v5, v13
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v13, v4, v12
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v1.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, 0x7e00, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v15.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v15.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v14.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v14.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4.h, v12.h
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.h, v11.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v14, v3, v11
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.h, v10.h
; GFX11-TRUE16-NEXT: v_pk_min_f16 v15, v2, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v13.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v14.l, v11.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v16.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v17, v0, v8
-; GFX11-TRUE16-NEXT: v_pk_min_f16 v1, v1, v9
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v13.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s4, v0.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s5, v16.l, v14.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v17.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v13.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v4.l, v12.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v14.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v11.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v15.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.h, v9.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v11, v1, v9
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.h, v8.h
+; GFX11-TRUE16-NEXT: v_pk_min_f16 v12, v0, v8
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v0.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_o_f16_e64 s5, v2.l, v10.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v11.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v11.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v12.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v12.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v15.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v14.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v13.l, vcc_lo
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimum_v16f16:
diff --git a/llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll b/llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
index 96e71dc51eeacd..ce41cfc7b2c249 100644
--- a/llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
@@ -65,41 +65,21 @@ define amdgpu_cs void @atomic_load_f16x2_monotonic_agent(ptr addrspace(0) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: flat_load_b32 v0, v[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(0) %p syncscope("agent") monotonic, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -126,41 +106,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent(ptr addrspace(0) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: flat_load_b32 v0, v[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(0) %p syncscope("agent") monotonic, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -190,55 +150,27 @@ define amdgpu_cs void @atomic_load_f16x4_monotonic_agent(ptr addrspace(0) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: flat_load_b64 v[0:1], v[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(0) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -273,49 +205,25 @@ define amdgpu_cs void @atomic_load_i16x4_monotonic_agent(ptr addrspace(0) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: flat_load_b64 v[0:1], v[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(0) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -441,46 +349,24 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_min(ptr addrspac
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-SDAG-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
-; GFX11-GISEL-NEXT: flat_load_b32 v0, v[0:1] glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-4096 scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc_lo
+; GFX11-NEXT: flat_load_b32 v0, v[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:-4096 scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_min:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b32 v0, v[0:1] offset:-4096 scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(0) %p, i64 -4096
%a = load atomic <2 x i16>, ptr addrspace(0) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -510,41 +396,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:4095 glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:4095 glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:4095 scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: flat_load_b32 v0, v[0:1] offset:4095 glc
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: flat_load_b32 v0, v[0:1] offset:4095 scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: flat_load_b32 v0, v[0:1] offset:4095 scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(0) %p, i64 4095
%a = load atomic <2 x i16>, ptr addrspace(0) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -557,5 +423,9 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
; GCN: {{.*}}
; GFX10-GISEL: {{.*}}
; GFX10-SDAG: {{.*}}
+; GFX11-GISEL: {{.*}}
+; GFX11-SDAG: {{.*}}
+; GFX12-GISEL: {{.*}}
+; GFX12-SDAG: {{.*}}
; GFX9-GISEL: {{.*}}
; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/load-atomic-global.ll b/llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
index 7a1ade7e1748de..6d0f7cb4a6c4e3 100644
--- a/llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
@@ -151,41 +151,21 @@ define amdgpu_cs void @atomic_load_f16x2_monotonic_agent(ptr addrspace(1) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(1) %p syncscope("agent") monotonic, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -214,47 +194,24 @@ define amdgpu_cs void @atomic_load_f16x2_seq_cst_agent(ptr addrspace(1) %p, ptr
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl1_inv
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl1_inv
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: buffer_gl1_inv
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_DEV
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(1) %p syncscope("agent") seq_cst, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -280,41 +237,21 @@ define amdgpu_cs void @atomic_load_f16x2_monotonic_wavefront(ptr addrspace(1) %p
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(1) %p syncscope("wavefront") monotonic, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -341,41 +278,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent(ptr addrspace(1) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(1) %p syncscope("agent") monotonic, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -405,47 +322,24 @@ define amdgpu_cs void @atomic_load_i16x2_seq_cst_agent(ptr addrspace(1) %p, ptr
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl1_inv
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl1_inv
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: buffer_gl1_inv
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_DEV
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(1) %p syncscope("agent") seq_cst, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -472,41 +366,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_wavefront(ptr addrspace(1) %p
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(1) %p syncscope("wavefront") monotonic, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -536,55 +410,27 @@ define amdgpu_cs void @atomic_load_f16x4_monotonic_agent(ptr addrspace(1) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(1) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -621,61 +467,30 @@ define amdgpu_cs void @atomic_load_f16x4_seq_cst_agent(ptr addrspace(1) %p, ptr
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl1_inv
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl1_inv
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: buffer_gl1_inv
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_DEV
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(1) %p syncscope("agent") seq_cst, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -709,55 +524,27 @@ define amdgpu_cs void @atomic_load_f16x4_monotonic_wavefront(ptr addrspace(1) %p
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v1.l, v5.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v1.l, v1.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(1) %p syncscope("wavefront") monotonic, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -792,49 +579,25 @@ define amdgpu_cs void @atomic_load_i16x4_monotonic_agent(ptr addrspace(1) %p, pt
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(1) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -872,55 +635,28 @@ define amdgpu_cs void @atomic_load_i16x4_seq_cst_agent(ptr addrspace(1) %p, ptr
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl1_inv
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl1_inv
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: buffer_gl1_inv
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_DEV
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(1) %p syncscope("agent") seq_cst, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -955,49 +691,25 @@ define amdgpu_cs void @atomic_load_i16x4_monotonic_wavefront(ptr addrspace(1) %p
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v4.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v1.l, v5.l, v0.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b64 v[0:1], v[0:1], off
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v1.l, v1.h, v0.l
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(1) %p syncscope("wavefront") monotonic, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -1122,41 +834,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_1(ptr addrspace(
; GFX10-NEXT: global_store_short v[2:3], v0, off
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off offset:1 glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off offset:1 glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off offset:1 scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:1 glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off offset:1 scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:1 scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(1) %p, i64 1
%a = load atomic <2 x i16>, ptr addrspace(1) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -1197,41 +889,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
; GFX10-GISEL-NEXT: global_store_short v[2:3], v0, off
; GFX10-GISEL-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: global_load_b32 v0, v[0:1], off offset:4095 glc
-; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX11-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: global_load_b32 v0, v[0:1], off offset:4095 glc
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off offset:4095 scope:SCOPE_DEV
-; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4095 glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: global_store_b16 v[2:3], v0, off
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off offset:4095 scope:SCOPE_DEV
-; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: global_store_b16 v[2:3], v0, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:4095 scope:SCOPE_DEV
+; GFX12-NEXT: s_wait_loadcnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: global_store_b16 v[2:3], v0, off
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(1) %p, i64 4095
%a = load atomic <2 x i16>, ptr addrspace(1) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -1242,5 +914,9 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
+; GFX11-GISEL: {{.*}}
+; GFX11-SDAG: {{.*}}
+; GFX12-GISEL: {{.*}}
+; GFX12-SDAG: {{.*}}
; GFX9-GISEL: {{.*}}
; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/load-atomic-local.ll b/llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
index ccd6b16d0d42ef..05bb7ff9de4d3a 100644
--- a/llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
@@ -148,41 +148,21 @@ define amdgpu_cs void @atomic_load_f16x2_monotonic_agent(ptr addrspace(3) %p, pt
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(3) %p syncscope("agent") monotonic, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -209,45 +189,23 @@ define amdgpu_cs void @atomic_load_f16x2_seq_cst_agent(ptr addrspace(3) %p, ptr
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_SE
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_SE
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_SE
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(3) %p syncscope("agent") seq_cst, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -273,41 +231,21 @@ define amdgpu_cs void @atomic_load_f16x2_monotonic_wavefront(ptr addrspace(3) %p
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x2_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x2_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x2_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <2 x half>, ptr addrspace(3) %p syncscope("wavefront") monotonic, align 4
%num1 = extractelement <2 x half> %a0, i32 0
%num2 = extractelement <2 x half> %a0, i32 1
@@ -334,41 +272,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent(ptr addrspace(3) %p, pt
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(3) %p syncscope("agent") monotonic, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -396,45 +314,23 @@ define amdgpu_cs void @atomic_load_i16x2_seq_cst_agent(ptr addrspace(3) %p, ptr
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_SE
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_SE
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_SE
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(3) %p syncscope("agent") seq_cst, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -461,41 +357,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_wavefront(ptr addrspace(3) %p
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a = load atomic <2 x i16>, ptr addrspace(3) %p syncscope("wavefront") monotonic, align 4
%e0 = extractelement <2 x i16> %a, i32 0
%e1 = extractelement <2 x i16> %a, i32 1
@@ -525,55 +401,27 @@ define amdgpu_cs void @atomic_load_f16x4_monotonic_agent(ptr addrspace(3) %p, pt
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(3) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -608,59 +456,29 @@ define amdgpu_cs void @atomic_load_f16x4_seq_cst_agent(ptr addrspace(3) %p, ptr
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_SE
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_SE
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_SE
+; GFX12-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(3) %p syncscope("agent") seq_cst, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -694,55 +512,27 @@ define amdgpu_cs void @atomic_load_f16x4_monotonic_wavefront(ptr addrspace(3) %p
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_f16x4_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX11-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_f16x4_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_f16x4_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_f16_e32 v0.l, v2.l, v2.h
+; GFX12-NEXT: v_mul_f16_e32 v0.h, v3.l, v3.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x half>, ptr addrspace(3) %p syncscope("wavefront") monotonic, align 8
%num1 = extractelement <4 x half> %a0, i32 0
%num2 = extractelement <4 x half> %a0, i32 1
@@ -777,49 +567,25 @@ define amdgpu_cs void @atomic_load_i16x4_monotonic_agent(ptr addrspace(3) %p, pt
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_monotonic_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_monotonic_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(3) %p syncscope("agent") monotonic, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -855,53 +621,27 @@ define amdgpu_cs void @atomic_load_i16x4_seq_cst_agent(ptr addrspace(3) %p, ptr
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: buffer_gl0_inv
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: buffer_gl0_inv
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: global_inv scope:SCOPE_SE
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_seq_cst_agent:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: buffer_gl0_inv
+; GFX11-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_seq_cst_agent:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: global_inv scope:SCOPE_SE
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_seq_cst_agent:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: global_inv scope:SCOPE_SE
+; GFX12-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(3) %p syncscope("agent") seq_cst, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -936,49 +676,25 @@ define amdgpu_cs void @atomic_load_i16x4_monotonic_wavefront(ptr addrspace(3) %p
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX11-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v2.l, v0.l
-; GFX12-SDAG-NEXT: v_mad_u16 v0.l, v3.l, v4.l, v0.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x4_monotonic_wavefront:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b64 v[2:3], v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x4_monotonic_wavefront:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b64 v[2:3], v0
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
-; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-GISEL-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x4_monotonic_wavefront:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b64 v[2:3], v0
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v2.l, v2.h
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_mad_u16 v0.l, v3.l, v3.h, v0.l
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%a0 = load atomic <4 x i16>, ptr addrspace(3) %p syncscope("wavefront") monotonic, align 8
%num1 = extractelement <4 x i16> %a0, i32 0
%num2 = extractelement <4 x i16> %a0, i32 1
@@ -1091,41 +807,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_1(ptr addrspace(
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0 offset:1
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0 offset:1
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0 offset:1
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0 offset:1
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0 offset:1
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_1:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0 offset:1
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(3) %p, i64 1
%a = load atomic <2 x i16>, ptr addrspace(3) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -1153,41 +849,21 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
; GFX10-NEXT: ds_write_b16 v1, v0
; GFX10-NEXT: s_endpgm
;
-; GFX11-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: ds_load_b32 v0, v0 offset:4095
-; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX11-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: ds_load_b32 v0, v0 offset:4095
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX11-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX12-SDAG-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: ds_load_b32 v0, v0 offset:4095
-; GFX12-SDAG-NEXT: s_wait_dscnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: ds_store_b16 v1, v0
-; GFX12-SDAG-NEXT: s_endpgm
+; GFX11-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: ds_load_b32 v0, v0 offset:4095
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX11-NEXT: ds_store_b16 v1, v0
+; GFX11-NEXT: s_endpgm
;
-; GFX12-GISEL-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: ds_load_b32 v0, v0 offset:4095
-; GFX12-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX12-GISEL-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
-; GFX12-GISEL-NEXT: ds_store_b16 v1, v0
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: atomic_load_i16x2_monotonic_agent_offset_max:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: ds_load_b32 v0, v0 offset:4095
+; GFX12-NEXT: s_wait_dscnt 0x0
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
+; GFX12-NEXT: ds_store_b16 v1, v0
+; GFX12-NEXT: s_endpgm
%gep = getelementptr inbounds i8, ptr addrspace(3) %p, i64 4095
%a = load atomic <2 x i16>, ptr addrspace(3) %gep syncscope("agent") monotonic, align 8
%e0 = extractelement <2 x i16> %a, i32 0
@@ -1200,5 +876,9 @@ define amdgpu_cs void @atomic_load_i16x2_monotonic_agent_offset_max(ptr addrspac
; GCN: {{.*}}
; GFX10-GISEL: {{.*}}
; GFX10-SDAG: {{.*}}
+; GFX11-GISEL: {{.*}}
+; GFX11-SDAG: {{.*}}
+; GFX12-GISEL: {{.*}}
+; GFX12-SDAG: {{.*}}
; GFX9-GISEL: {{.*}}
; GFX9-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index ac8526dbce15ca..c92039e315a89c 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -6316,22 +6316,21 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6339,12 +6338,9 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6355,7 +6351,6 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6682,22 +6677,21 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6705,12 +6699,9 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6721,7 +6712,6 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7051,15 +7041,14 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7072,11 +7061,8 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7088,7 +7074,6 @@ define void @local_atomic_fadd_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7400,15 +7385,14 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7421,11 +7405,8 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7437,7 +7418,6 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 369b06bb29697e..6e8da409041f44 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -6099,15 +6099,15 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6116,13 +6116,10 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
@@ -6238,22 +6235,21 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6261,12 +6257,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6277,7 +6270,6 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6593,15 +6585,15 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6610,13 +6602,10 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
@@ -6732,22 +6721,21 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6755,12 +6743,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6771,7 +6756,6 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7088,10 +7072,10 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7106,10 +7090,7 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
@@ -7222,15 +7203,14 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7243,11 +7223,8 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7259,7 +7236,6 @@ define void @local_atomic_fmax_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7558,10 +7534,10 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_max_num_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_max_num_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7576,10 +7552,7 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
@@ -7692,15 +7665,14 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_max_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_max_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_max_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7713,11 +7685,8 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7729,7 +7698,6 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 88e1469580618d..aa5163060fb25d 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -6099,15 +6099,15 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6116,13 +6116,10 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
@@ -6238,22 +6235,21 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6261,12 +6257,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6277,7 +6270,6 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -6593,15 +6585,15 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6610,13 +6602,10 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
@@ -6732,22 +6721,21 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6755,12 +6743,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -6771,7 +6756,6 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7088,10 +7072,10 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7106,10 +7090,7 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
@@ -7222,15 +7203,14 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7243,11 +7223,8 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7259,7 +7236,6 @@ define void @local_atomic_fmin_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7558,10 +7534,10 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_min_num_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_min_num_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7576,10 +7552,7 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
@@ -7692,15 +7665,14 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_min_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_min_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_min_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7713,11 +7685,8 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7729,7 +7698,6 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 515a544b1d0d1b..057982b7c1c4c4 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -6893,15 +6893,15 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -6910,13 +6910,10 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
@@ -7032,22 +7029,21 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB24_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -7055,12 +7051,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7071,7 +7064,6 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16(ptr addrspace(3) %ptr, <2 x bf
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB24_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7387,15 +7379,15 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX12-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -7404,13 +7396,10 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
@@ -7526,22 +7515,21 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB25_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v5, v5, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v2, v2, v1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
@@ -7549,12 +7537,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v2, 0x7fff
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v2, v0, v5, v4 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -7565,7 +7550,6 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB25_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -7882,10 +7866,10 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -7900,10 +7884,7 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
@@ -8016,15 +7997,14 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB26_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -8037,11 +8017,8 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -8053,7 +8030,6 @@ define void @local_atomic_fsub_noret_v2bf16(ptr addrspace(3) %ptr, <2 x bfloat>
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -8352,10 +8328,10 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-TRUE16-NEXT: s_wait_dscnt 0x0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX12-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -8370,10 +8346,7 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_storecnt 0x0
; GFX12-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
@@ -8486,15 +8459,14 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x1
; GFX11-TRUE16-NEXT: .p2align 6
; GFX11-TRUE16-NEXT: .LBB27_1: ; %atomicrmw.start
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v1 :: v_dual_and_b32 v4, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v2
+; GFX11-TRUE16-NEXT: v_dual_sub_f32 v5, v5, v2 :: v_dual_lshlrev_b32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_sub_f32_e32 v4, v4, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v4, 16, 1
@@ -8507,11 +8479,8 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.h
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: ds_cmpstore_rtn_b32 v4, v0, v5, v3 offset:65532
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
@@ -8523,7 +8492,6 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB27_1
; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX11-TRUE16-NEXT: s_set_inst_prefetch_distance 0x2
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
index 49239a259845ad..5013ea2ff2ccd8 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
@@ -478,10 +478,10 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_bf16lo_bf16lo(i32 %src0.arg, bfl
; GFX1250-REAL16: ; %bb.0:
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX1250-REAL16-NEXT: v_xor_b16 v2.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v2|, v1, v0 op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
@@ -909,10 +909,10 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_add_bf16lo(i32 %src0.arg, bfloat
; GFX1250-REAL16: ; %bb.0:
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX1250-REAL16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, 1.0, v0 op_sel:[0,1,0] op_sel_hi:[1,1,1]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
@@ -1271,10 +1271,10 @@ define float @v_mad_mix_f32_precvtnegbf16hi_abs_mul_bf16lo(i32 %src0.arg, bfloat
; GFX1250-REAL16: ; %bb.0:
; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; GFX1250-REAL16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mix_f32_bf16 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0]
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat>
%src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
index 4ac8985ecad7b2..c15cf022b31779 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
@@ -306,11 +306,10 @@ define <2 x bfloat> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x bfloat> %src0, <2 x b
; GFX1250-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_pk_fma_f32 v[0:1], v[4:5], v[6:7], v[0:1]
-; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1250-REAL16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v1, v0, v1
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_pk_max_num_bf16 v0, v1, v1 op_sel_hi:[0,0] clamp
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v1.h
; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext <2 x bfloat> %src0 to <2 x float>
%src1.ext = fpext <2 x bfloat> %src1 to <2 x float>
@@ -357,7 +356,7 @@ define <2 x bfloat> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x bfloat> %src0, <2 x b
; GFX1250-REAL16-NEXT: v_pk_fma_f32 v[0:1], v[4:5], v[6:7], v[0:1]
; GFX1250-REAL16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX1250-REAL16-NEXT: v_pk_max_num_bf16 v1, v1, v1 op_sel_hi:[0,0] clamp
; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v1.l
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
index 5969309df7294a..79702501bf381e 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll
@@ -2165,10 +2165,10 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v2.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v2|, v1, v0 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo:
@@ -3703,10 +3703,10 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %sr
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1]
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, 1.0, v0 op_sel_hi:[1,1,1]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo:
@@ -5183,10 +5183,10 @@ define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %sr
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
; SDAG-GFX1100-TRUE16: ; %bb.0:
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG-GFX1100-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0]
+; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
+; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h
+; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0]
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo:
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index bd2fa2a024fa66..8fe3cea6069b5f 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -554,20 +554,19 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
@@ -654,22 +653,21 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
@@ -887,16 +885,14 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -906,10 +902,10 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16_nnan:
@@ -952,17 +948,15 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -972,11 +966,11 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16_nnan:
@@ -1264,51 +1258,51 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -1322,9 +1316,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1393,56 +1387,54 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -1457,9 +1449,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1711,36 +1703,35 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16_nnan:
@@ -1794,38 +1785,38 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16_nnan:
@@ -2203,82 +2194,78 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16:
@@ -2370,91 +2357,87 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16:
@@ -2776,48 +2759,45 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v10, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v0.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v9
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.h, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:
@@ -2882,53 +2862,49 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v10, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v0.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v9
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s5, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:
@@ -3475,119 +3451,113 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v11, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v18, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v14, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v4.h, v8.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v0.h, v3.h, s5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v3.h, v9.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v9.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v8.l, s7
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v6bf16:
@@ -3716,133 +3686,125 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v11, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v18, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v14, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v4.h, v8.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v0.h, v3.h, s5
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v3.h, v9.l, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v9.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v8.l, s7
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v6bf16:
@@ -4622,164 +4584,150 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v14, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v10.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v5.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v5.h, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v4.h, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.l, v8.l, s8
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v10.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v8bf16:
@@ -4938,185 +4886,172 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v15
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v7.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v16
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v14, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v10.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v5.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v5.h, v8.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v10.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v4.h, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.l, v8.l, s8
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v10.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v8bf16:
@@ -6532,327 +6467,306 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-TRUE16-LABEL: v_maximumnum_v16bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v7.h, v15.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v15.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v16.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v15.h, v16.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v20.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v6.h, v14.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v16.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v18.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v19.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v13.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v13.h, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s0, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v21, v17
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v21, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v4.h, v12.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.h, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v23, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v22
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v20.l, v17.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v16.l, v15.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v11.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.h, v14.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v18.l, v17.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v2.h, v10.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v10.h, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v19, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v1.h, v9.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v9.h, v14.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v16.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v18, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v8.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.h, v13.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v20
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v4, v19
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v16.l, v14.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v16bf16:
@@ -7178,372 +7092,349 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v7.h, v15.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v16.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v15.h, v16.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v6.h, v14.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v20, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v18.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v19.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v20
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v19.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v13.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v20.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v13.h, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s0, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v21, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v29
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v21, v20
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v4.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v24.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.h, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v17.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v20.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s4
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v23, v21
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v22
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v20.l, v17.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v22
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v16.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v16, v16
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v11.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v17.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v4.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.h, v14.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v18.l, v17.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v2.h, v10.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v10.h, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v11.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v19, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v1.h, v9.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v15.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v9.h, v14.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v16.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v18, v18
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v8.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.h, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v15.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v19, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v20
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v14.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v20 :: v_dual_mov_b32 v3, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v16.l, v14.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.l, v13.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v16bf16:
@@ -10369,633 +10260,596 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v29.h, v33.l, s7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v100, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v30.h, v32.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v30.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v50.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v99, v99
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v97, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v98, v129
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v28.h, v34.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v26.h, v36.l, s19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v67, v100
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v68, v101
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v51.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v66, v99
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v28.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v50.l, v33.l, s20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v49.l, v32.l, s18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v50.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v70, v112
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v11.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v25.h, v37.l, s23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v27.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v69, v103
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v71, v113
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v51.l, v34.l, s22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v10.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s23
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v96, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v51.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v66
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v117, v97
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v81, v115
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v28.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v97, v97
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s42
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v24.h, v38.l, s27
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v83, v117
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v70
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v98, v98
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v69
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v71
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v23.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v96, v119
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v87, v135
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v115, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v100, v130
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s44
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s40
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v102, v132
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v85, v119
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v22.h, v48.l, s45
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v81
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s21, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v23.h, v39.l, s41
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v87, v129
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v97, v131
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v12.l
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s19, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v65.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v83
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s25, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s41
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v25.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s23, s7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v101, v131
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v112, v133
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v34.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v99, v144
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v103, v145
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s16, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v38.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v113, v134
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v48.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v114, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v50.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v51.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v52.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v32.l
+; GFX11-TRUE16-NEXT: s_and_b32 s11, s27, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v98, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v27.h, v35.l, s15
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s18, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v85
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v49.l, v32.l, s2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s46
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v48.l, s44
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v87
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v97
+; GFX11-TRUE16-NEXT: s_and_b32 s13, s29, s13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v65.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s15, s41, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v33.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v98
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, s4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v35.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v50.l, v33.l, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v54.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v55.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v37.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v116, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v49.l
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v39.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v80, v114
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v64.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.l, v35.l, s24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v52.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s13, s28, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v82, v116
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v84, v118
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v86, v128
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v96, v130
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v80
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.l, v36.l, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.l, v37.l, s28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.l, v38.l, s40
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.l, v39.l, s42
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s24, s8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v53.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v52.l, v35.l, s8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v64.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v34.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: s_and_b32 s6, s22, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v36.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v37.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v38.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v39.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v82
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v84
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s40, 0, v86
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v96
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v51.l, v34.l, s6
+; GFX11-TRUE16-NEXT: s_and_b32 s10, s26, s10
+; GFX11-TRUE16-NEXT: s_and_b32 s12, s28, s12
+; GFX11-TRUE16-NEXT: s_and_b32 s14, s40, s14
+; GFX11-TRUE16-NEXT: s_and_b32 s16, s42, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v53.l, v36.l, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v54.l, v37.l, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v55.l, v38.l, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v64.l, v39.l, s16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v15.h, v31.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v67, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v68, v68
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v15.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v31.h, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v31.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v39
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v68, v70
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v69, v71
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v67.l, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v31.l, v15.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v30.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v6.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v29.l, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v102, v102
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v15.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s43, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v5.h, v21.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v22.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v48.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v21.h, v23.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v53, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v54, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v4.h, v20.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v23.l, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v20.h, v25.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v29
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v65.l, v48.l, s4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v29, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v25.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.l, v23.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v26.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v3.h, v19.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v25.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v19.h, v22.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v22.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v26.l, v25.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v2.h, v18.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v18.h, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v27, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v23.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v21.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v24.l, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v1.h, v17.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v17.h, v22.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v24.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v21.l, v23.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v0.h, v16.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v30 :: v_dual_mov_b32 v12, v37
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v16.h, v21.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v29, v28
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v21.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v22.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v23.l, v21.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v32bf16:
@@ -11574,697 +11428,654 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v14
; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v29
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v30
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v29
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v29.h, v33.l, s7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v100, v100
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v30.h, v32.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v14.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v30.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v33.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v50.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v99, v99
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v32.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v28.h, v34.l, s11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v26.h, v36.l, s19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v67, v100
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s20
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s13
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v68, v101
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v34.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v51.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v66, v99
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v13.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v12.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v28.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v97, v128
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v98, v129
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v50.l, v33.l, s20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v49.l, v32.l, s18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v50.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v70, v112
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v24
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v81.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v25.h, v37.l, s23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v27.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v69, v103
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v71, v113
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v117, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v51.l, v34.l, s22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v10.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v26.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s23
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v96, v96
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v51.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v66
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v81, v115
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v28.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v97, v97
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s42
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v24.h, v38.l, s27
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v83, v117
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s29
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v25.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v70
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v98, v98
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s27
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v81.l, v27.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v69
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v71
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v23.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v96, v119
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v87, v135
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v115, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v100, v130
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s44
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v13.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s40
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v102, v132
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v85, v119
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v22.h, v48.l, s45
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v11.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v81
+; GFX12-TRUE16-NEXT: s_and_b32 s5, s21, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v23.h, v39.l, s41
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v87, v129
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v97, v131
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s29
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v12.l
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s19, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v48.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v65.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v83
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s25, s9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v25.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s23, s7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v101, v131
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v112, v133
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v34.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v99, v144
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v103, v145
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s16, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v32.l
+; GFX12-TRUE16-NEXT: s_and_b32 s11, s27, s11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v38.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v113, v134
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v23.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v98, v132
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v27.h, v35.l, s15
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s18, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v85
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v48.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v114, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v50.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v51.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v52.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v49.l, v32.l, s2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s46
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v48.l, s44
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v87
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v97
+; GFX12-TRUE16-NEXT: s_and_b32 s13, s29, s13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v65.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX12-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX12-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v64.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s15, s41, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v33.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v98
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v80.l, v35.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s20, s4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v35.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v50.l, v33.l, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v53.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v37.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v38.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v39.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v80, v114
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v53.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v55.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v64.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.l, v35.l, s24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v80.l, v52.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v55.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v37.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v116, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v49.l
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v82, v116
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v84, v118
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s40, v86, v128
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v96, v130
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v80
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.l, v36.l, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.l, v37.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.l, v38.l, s40
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.l, v39.l, s42
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s24, s8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v53.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX12-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s13, s28, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v52.l, v35.l, s8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v55.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v64.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v34.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: s_and_b32 s6, s22, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v36.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v37.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v38.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v39.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v82
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v84
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s40, 0, v86
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v96
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v51.l, v34.l, s6
+; GFX12-TRUE16-NEXT: s_and_b32 s10, s26, s10
+; GFX12-TRUE16-NEXT: s_and_b32 s12, s28, s12
+; GFX12-TRUE16-NEXT: s_and_b32 s14, s40, s14
+; GFX12-TRUE16-NEXT: s_and_b32 s16, s42, s16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v53.l, v36.l, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v54.l, v37.l, s12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v55.l, v38.l, s14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v64.l, v39.l, s16
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v31
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v15.h, v31.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v67, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v68, v68
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v66.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v15.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v31.h, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v67.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v31.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v39
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v32.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v68, v70
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v69, v71
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v67.l, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v31.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v66.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v15.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v30.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v6.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v29.l, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v102, v102
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v15.l, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s43, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v5.h, v21.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v22.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v48.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v21.h, v23.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX12-TRUE16-NEXT: s_and_b32 s4, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v27, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v53, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v54, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v4.h, v20.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v23.l, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v20.h, v25.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v23.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v29
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v26.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v25.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v65.l, v48.l, s4
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v29, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v25.l, s3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.l, v23.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v26.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v3.h, v19.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v25.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v20.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v4.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v19.h, v22.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v22.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v29
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v26.l, v25.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v24, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v2.h, v18.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v18.h, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v27, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v23.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v25
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v21.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v24.l, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v1.h, v17.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v23.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v17.h, v22.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v24.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v21.l, v23.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v0.h, v16.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v17.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v16.h, v21.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v23.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v29, v28
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v31, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v21.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v22.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v31 :: v_dual_mov_b32 v11, v30
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v22.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v23.l, v21.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v32bf16:
@@ -13317,20 +13128,19 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
@@ -13417,22 +13227,21 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
@@ -13766,51 +13575,51 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16_no_ieee:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -13824,9 +13633,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13895,56 +13704,54 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -13959,9 +13766,9 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -14358,82 +14165,78 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee:
@@ -14525,91 +14328,87 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v8, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee:
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index d5d49a74815fc7..e8c77cb8958279 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -563,20 +563,19 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
@@ -663,22 +662,21 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
@@ -899,16 +897,14 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.h, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.h
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -918,10 +914,10 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16_nnan:
@@ -964,17 +960,15 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.h, v0.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.h
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
@@ -984,11 +978,11 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16_nnan:
@@ -1279,51 +1273,51 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -1337,9 +1331,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1408,56 +1402,54 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -1472,9 +1464,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1728,36 +1720,35 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16_nnan:
@@ -1811,38 +1802,38 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.h
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v6
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v7
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s4, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16_nnan:
@@ -2223,82 +2214,78 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16:
@@ -2390,91 +2377,87 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16:
@@ -2799,48 +2782,45 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v10, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v0.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v9
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.h, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:
@@ -2905,53 +2885,49 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v10, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.h
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v0.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v9
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s5, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.h, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:
@@ -3501,119 +3477,113 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v11, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v18, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v14, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v4.h, v8.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v0.h, v3.h, s5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v3.h, v9.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v9.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v8.l, s7
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v6bf16:
@@ -3742,133 +3712,125 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v10, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v2.h, v5.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v11, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.h, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v18, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v4.h, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v14, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v4.h, v8.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v0.h, v3.h, s5
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v3.h, v9.l, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v9.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v8.l, s7
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v6bf16:
@@ -4650,164 +4612,150 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v16
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v14, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v10.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v5.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v5.h, v8.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v4.h, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.l, v8.l, s8
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v10.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v8bf16:
@@ -4966,185 +4914,172 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v11, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v3.h, v7.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v7.h, v8.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v15
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v2.h, v6.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v7.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v6.h, v10.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v16
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v14, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v7.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v10.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.h, v5.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v6.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v5.h, v8.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v10.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v0.h, v4.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v4.h, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v10.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v11.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v13
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.l, v8.l, s8
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v10.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v8bf16:
@@ -6562,327 +6497,306 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-TRUE16-LABEL: v_minimumnum_v16bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v7.h, v15.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v15.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v16.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v15.h, v16.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v20.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v6.h, v14.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v20, v21
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v16.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v18.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v19.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v13.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v13.h, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s0, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v21, v17
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v21, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v4.h, v12.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.h, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v23, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v22
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v20.l, v17.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v16.l, v15.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v11.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v17.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.h, v14.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v18.l, v17.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v2.h, v10.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v10.h, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v19, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v15.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v1.h, v9.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v15.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v9.h, v14.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v16.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v18, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v8.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.h, v13.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v14.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v15.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v20
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v4, v19
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v14.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v16.l, v14.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v16bf16:
@@ -7208,372 +7122,349 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v7.h, v15.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v16.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v15.h, v16.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v17.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v18
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v6.h, v14.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v20, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v14.h, v18.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v19.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v17.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v20
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v19.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v5.h, v13.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v18.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v15.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v20.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v13.h, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v13
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s0, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v21, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v29
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v21, v20
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v4.h, v12.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v14.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v24.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.h, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v17.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v20.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s4
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v23, v21
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v22
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v20.l, v17.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v4
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v22
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v16.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v16, v16
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v3.h, v11.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v15, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v17.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v4.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v11.h, v14.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v18.l, v17.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v2.h, v10.h, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v13.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v10.h, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v11.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v13.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v19, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v1.h, v9.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v16, v16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v15.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v9.h, v14.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v14.l
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v16.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v20
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v18, v18
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v13, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v0.h, v8.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v9.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v8.h, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v15.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v19, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v20
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v14.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v20 :: v_dual_mov_b32 v3, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v16.l, v14.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.l, v13.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v16bf16:
@@ -10402,633 +10293,596 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v29.h, v33.l, s7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v100, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v30.h, v32.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v14.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v30.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v50.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v99, v99
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s16, v97, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v98, v129
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v28.h, v34.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v26.h, v36.l, s19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v67, v100
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s13
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v68, v101
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v51.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v66, v99
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s19
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s16
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v12.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v28.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v50.l, v33.l, s20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v49.l, v32.l, s18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v50.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v70, v112
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v24
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v11.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v25.h, v37.l, s23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v27.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v69, v103
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v71, v113
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v51.l, v34.l, s22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v10.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s23
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v96, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v51.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v66
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v117, v97
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v36.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v81, v115
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v28.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v97, v97
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s42
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v24.h, v38.l, s27
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v83, v117
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v9.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v70
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v98, v98
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v27.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v69
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v71
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v23.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s15, v96, v119
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v87, v135
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v115, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v100, v130
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s44
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v13.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s40
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v102, v132
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v85, v119
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v22.h, v48.l, s45
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v11.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v81
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s21, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v23.h, v39.l, s41
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v87, v129
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v97, v131
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v12.l
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s19, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v65.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v83
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s25, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s41
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v25.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s23, s7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v101, v131
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v112, v133
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v34.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v99, v144
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v103, v145
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s16, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v38.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v113, v134
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v48.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v114, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v50.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v51.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v52.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v64.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v32.l
+; GFX11-TRUE16-NEXT: s_and_b32 s11, s27, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v98, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v27.h, v35.l, s15
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s18, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v85
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v49.l, v32.l, s2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s46
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v48.l, s44
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v87
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v97
+; GFX11-TRUE16-NEXT: s_and_b32 s13, s29, s13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v65.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s15, s41, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v33.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v98
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, s4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v35.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v50.l, v33.l, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v54.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v55.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v37.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v116, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v49.l
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v39.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v80, v114
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v64.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.l, v35.l, s24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v52.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s13, s28, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v82, v116
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v84, v118
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v86, v128
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v96, v130
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v80
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.l, v36.l, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.l, v37.l, s28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.l, v38.l, s40
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.l, v39.l, s42
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s24, s8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v53.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v52.l, v35.l, s8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v64.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v34.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX11-TRUE16-NEXT: s_and_b32 s6, s22, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v36.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v37.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v38.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v39.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v82
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v84
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s40, 0, v86
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v96
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v51.l, v34.l, s6
+; GFX11-TRUE16-NEXT: s_and_b32 s10, s26, s10
+; GFX11-TRUE16-NEXT: s_and_b32 s12, s28, s12
+; GFX11-TRUE16-NEXT: s_and_b32 s14, s40, s14
+; GFX11-TRUE16-NEXT: s_and_b32 s16, s42, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v53.l, v36.l, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v54.l, v37.l, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v55.l, v38.l, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v64.l, v39.l, s16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v15.h, v31.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v67, v67
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v68, v68
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v15.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v31.h, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v31.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v96, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v39
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v68, v70
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v69, v71
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v67.l, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v31.l, v15.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v29.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v30.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v6.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v29.l, v66.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v102, v102
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v15.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s43, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v5.h, v21.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v22.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v48.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v21.h, v23.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v53, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v54, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v4.h, v20.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v23.l, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v20.h, v25.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v29
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v25.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v65.l, v48.l, s4
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v29, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v25.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.l, v23.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v26.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v3.h, v19.h, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v25.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v20.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v19.h, v22.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v22.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v26.l, v25.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v2.h, v18.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v18.h, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v27, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v23.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v21.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v24.l, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v1.h, v17.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v17.h, v22.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v24.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v21.l, v23.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v0.h, v16.h, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v30 :: v_dual_mov_b32 v12, v37
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v17.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v16.h, v21.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v21.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v0.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v23.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v24.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v29, v28
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v21.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v22.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v22.l, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v23.l, v21.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v32bf16:
@@ -11607,697 +11461,654 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v14
; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v36, v36
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v29
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v38, v38
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v30
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v34
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v37, v37
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v33
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v39, v39
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v13.h, v29.h, s6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v49, 16, v29
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v32
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v35, v35
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v14.h, v30.h, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v50, v50
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v29.h, v33.l, s7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v99, 0xffff0000, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v66, v66
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v67, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v100, v100
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v30.h, v32.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v14.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v30.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v48, v48
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v52, v52
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v68, v68
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v101
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v33.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v50.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v99, v99
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v12.h, v28.h, s10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v10.h, v26.h, s18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v32.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v64, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v53, v53
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v28.h, v34.l, s11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v26.h, v36.l, s19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v67, v100
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v71, 0xffff0000, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v64, v64
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s20
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s13
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v68, v101
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v70, v70
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v34.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v51.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v66, v99
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s19
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v65, v65
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v69, v69
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v71, v71
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s16
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v13.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v12.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v28.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s16, v97, v128
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v98, v129
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v50.l, v33.l, s20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v49.l, v32.l, s18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v30.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v9.h, v25.h, s22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v50.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v70, v112
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v67, 16, v67
; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v83, 0xffff0000, v24
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v54, v54
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v80, v80
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v81
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v81.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v25.h, v37.l, s23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v27.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v69, v103
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v71, v113
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v117, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v36.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v51.l, v34.l, s22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v82
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v83, v83
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v10.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v26.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s23
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v84
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v96, v96
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v51.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v66
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v8.h, v24.h, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v81, v115
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v28.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v85, v85
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v97, v97
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s42
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v55, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v24.h, v38.l, s27
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v83, v117
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v87, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s29
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v25.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v70
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v98, v98
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s27
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v81.l, v27.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v69
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v71
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v86, v86
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v87
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v23.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s15, v96, v119
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v87, v135
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v115, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v100, v130
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v6.h, v22.h, s44
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v13.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v26.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v81
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v7.h, v23.h, s40
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v102, v132
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v85, v119
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v22.h, v48.l, s45
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v11.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v83
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v81
+; GFX12-TRUE16-NEXT: s_and_b32 s5, s21, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v23.h, v39.l, s41
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v87, v129
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v97, v131
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s29
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v12.l
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s19, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v48.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v65.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v83
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s25, s9
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v7.l, s43
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v85.l, v25.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s23, s7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v101, v131
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v112, v133
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v34.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v99, v144
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v103, v145
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s16, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v11.h, v27.h, s14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v32.l
+; GFX12-TRUE16-NEXT: s_and_b32 s11, s27, s11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v38.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v113, v134
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v23.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v85
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v98, v132
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v27.h, v35.l, s15
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s18, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v9.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v85
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v48.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v114, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v50.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v51.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v52.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v49.l, v32.l, s2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, s46
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v48.l, s44
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0x8000, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v87
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v97
+; GFX12-TRUE16-NEXT: s_and_b32 s13, s29, s13
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v65.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX12-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX12-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v64.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s15, s41, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v33.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v98
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v80.l, v35.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v52.l
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s20, s4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v35.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v24
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v50.l, v33.l, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v53.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v37.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v38.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v39.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v80, v114
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v53.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v55.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v64.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.l, v35.l, s24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v80.l, v52.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v55.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v37.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v116, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v49.l
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v80
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v82, v116
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v84, v118
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s40, v86, v128
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v96, v130
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v80
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.l, v36.l, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.l, v37.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.l, v38.l, s40
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.l, v39.l, s42
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s24, s8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v53.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX12-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s13, s28, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v52.l, v35.l, s8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v84.l, v54.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v86.l, v55.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v64.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v34.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: s_and_b32 s6, s22, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v36.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v37.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v38.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v39.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v82
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v84
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s40, 0, v86
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v96
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v51.l, v34.l, s6
+; GFX12-TRUE16-NEXT: s_and_b32 s10, s26, s10
+; GFX12-TRUE16-NEXT: s_and_b32 s12, s28, s12
+; GFX12-TRUE16-NEXT: s_and_b32 s14, s40, s14
+; GFX12-TRUE16-NEXT: s_and_b32 s16, s42, s16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v53.l, v36.l, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v54.l, v37.l, s12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v55.l, v38.l, s14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v64.l, v39.l, s16
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v31
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v15.h, v31.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v67, v67
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v68, v68
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v68.l, v66.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v69.l, v15.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v31.h, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v70.l, v67.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v71.l, v31.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v71, 16, v71
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v96, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v39
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v32.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v68, v70
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v69, v71
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v67.l, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v31.l, v15.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v66.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v15.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v29.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v30.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v6.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v29.l, v66.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v102, v102
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v30.l, v15.l, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s43, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v5.h, v21.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v22.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v48.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v21.h, v23.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v21
+; GFX12-TRUE16-NEXT: s_and_b32 s4, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v29
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v27, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v53, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v54, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v4.h, v20.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v23.l, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v20.h, v25.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v23.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v29
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v26.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v25.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v30
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v28
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v65.l, v48.l, s4
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v29, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v25.l, s3
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v24.l, v23.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v20
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v26.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v24, v24
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v3.h, v19.h, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v25.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v20.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v4.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v19.h, v22.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v3
; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v22.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v29
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v26.l, v25.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v24, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v18
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v19.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v2.h, v18.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v21.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v18.h, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v27, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v23.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s7, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v25
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v21.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v24.l, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v1.h, v17.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v24, v24
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v23.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v17.h, v22.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v22.l
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s0, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v24.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v21.l, v23.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v2.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v26, v26
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v0.h, v16.h, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v17.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v16.h, v21.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v21.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v23.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v18.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v27, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v24.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v29, v28
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v31, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v21.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v17.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v22.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s0, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v0.l
+; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v31 :: v_dual_mov_b32 v11, v30
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v22.l, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s5, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v23.l, v21.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s7
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v32bf16:
@@ -13355,20 +13166,19 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
@@ -13455,22 +13265,21 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v4, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
@@ -13807,51 +13616,51 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16_no_ieee:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -13865,9 +13674,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13936,56 +13745,54 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v2.h, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v2.h, v4.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v8
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -14000,9 +13807,9 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -14402,82 +14209,78 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v12
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee:
@@ -14569,91 +14372,87 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.h, v3.h, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v8, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v10, v10
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v0.h, v2.h, s2
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.h, v6.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v8
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v0.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v12
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v8, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v7.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee:
diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
index 8438b8b089cc4e..3e8c626cbf5e0d 100644
--- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
+++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
@@ -850,10 +850,8 @@ define <4 x half> @v_repeat_divisor_v2f16_x2(<2 x half> %x, <2 x half> %y, <2 x
; GFX11-TRUE16-LABEL: v_repeat_divisor_v2f16_x2:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.h, v2.h
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.l, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v2.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v1, v1, v2
@@ -972,20 +970,18 @@ define <6 x half> @v_repeat_divisor_v3f16_x2(<3 x half> %x, <3 x half> %y, <3 x
; GFX11-TRUE16-LABEL: v_repeat_divisor_v3f16_x2:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v4.h, v4.h
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v4.l, v4.l
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v5.l, v5.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0x7e00
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v4.h, v6.l
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v2, v2, v4
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v3, v3, v5
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v1, v1, v5
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v6, v2, v4
; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/roundeven.ll b/llvm/test/CodeGen/AMDGPU/roundeven.ll
index 92606c5e51da76..bd4879b46e28b6 100644
--- a/llvm/test/CodeGen/AMDGPU/roundeven.ll
+++ b/llvm/test/CodeGen/AMDGPU/roundeven.ll
@@ -556,9 +556,8 @@ define <2 x half> @v_roundeven_v2f16(<2 x half> %x) {
; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v2f16:
; SDAG_GFX11-TRUE16: ; %bb.0:
; SDAG_GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.h, v0.h
; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
-; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.h, v1.l
; SDAG_GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v2f16:
@@ -712,9 +711,8 @@ define <2 x half> @v_roundeven_v2f16_fneg(<2 x half> %x) {
; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v2f16_fneg:
; SDAG_GFX11-TRUE16: ; %bb.0:
; SDAG_GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e64 v0.h, -v0.h
; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e64 v0.l, -v0.l
-; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e64 v0.h, -v1.l
; SDAG_GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v2f16_fneg:
@@ -925,12 +923,10 @@ define <4 x half> @v_roundeven_v4f16(<4 x half> %x) {
; SDAG_GFX11-TRUE16-LABEL: v_roundeven_v4f16:
; SDAG_GFX11-TRUE16: ; %bb.0:
; SDAG_GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SDAG_GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; SDAG_GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v1.l, v1.l
+; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v1.h, v1.h
+; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.h, v0.h
; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l
-; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.h, v2.l
-; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v1.h, v3.l
+; SDAG_GFX11-TRUE16-NEXT: v_rndne_f16_e32 v1.l, v1.l
; SDAG_GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; SDAG_GFX11-FAKE16-LABEL: v_roundeven_v4f16:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
index abea713b453cd2..d5b2a72d5fa129 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
@@ -19,9 +19,7 @@ define amdgpu_kernel void @scalar_to_vector_i32 (ptr addrspace(1) %a, ptr addrsp
; GFX11-REAL16-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2
; GFX11-REAL16-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 killed [[S_MOV_B32_1]], killed [[V_AND_B32_e64_]], implicit $exec
; GFX11-REAL16-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[S_LOAD_DWORDX2_IMM]], killed [[V_LSHLREV_B32_e64_]], 0, 0, implicit $exec :: (load (s32) from %ir.in.gep1, addrspace 1)
- ; GFX11-REAL16-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 16
- ; GFX11-REAL16-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed [[S_MOV_B32_2]], [[GLOBAL_LOAD_DWORD_SADDR]], implicit $exec
- ; GFX11-REAL16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_LSHRREV_B32_e64_]].lo16
+ ; GFX11-REAL16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[GLOBAL_LOAD_DWORD_SADDR]].hi16
; GFX11-REAL16-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
; GFX11-REAL16-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY2]]
; GFX11-REAL16-NEXT: [[S_PACK_HL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HL_B32_B16 [[COPY3]], killed [[COPY4]]
diff --git a/llvm/test/CodeGen/AMDGPU/scmp.ll b/llvm/test/CodeGen/AMDGPU/scmp.ll
index 6ad3fee5344ccc..6d567d5790cafe 100644
--- a/llvm/test/CodeGen/AMDGPU/scmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/scmp.ll
@@ -393,21 +393,19 @@ define <2 x i32> @scmp_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_i16_e32 vcc_lo, v0.h, v1.h
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
-; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_i16_e32 vcc_lo, v0.h, v1.h
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v5, vcc_lo
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, -1, v3 :: v_dual_mov_b32 v0, v2
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: scmp_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
index 2ccfb6219dc419..d9a527bcb9ae42 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
@@ -60,18 +60,15 @@ define <2 x half> @add_select_fabs_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16-LABEL: add_select_fabs_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_fabs_fabs_v2f16:
@@ -172,19 +169,16 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_lhs_fabs_fabs_v2f16(<2 x
; GFX11-TRUE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v1, v4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v5
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_multi_use_lhs_fabs_fabs_v2f16:
@@ -272,19 +266,15 @@ define { <2 x half>, <2 x half> } @add_select_multi_store_use_lhs_fabs_fabs_v2f1
; GFX11-TRUE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_multi_store_use_lhs_fabs_fabs_v2f16:
@@ -388,19 +378,16 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_rhs_fabs_fabs_v2f16(<2 x
; GFX11-TRUE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v3, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_multi_use_rhs_fabs_fabs_v2f16:
@@ -484,15 +471,13 @@ define <2 x half> @add_select_fabs_var_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h
; GFX11-TRUE16-LABEL: add_select_fabs_var_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -573,15 +558,14 @@ define <2 x half> @add_select_fabs_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16-LABEL: add_select_fabs_negk_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0xbc00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0xbc00, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_fabs_negk_v2f16:
@@ -827,14 +811,13 @@ define <2 x half> @add_select_negk_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0xbc00, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0xbc00, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_negk_fabs_v2f16:
@@ -914,14 +897,13 @@ define <2 x half> @add_select_negliteralk_fabs_v2f16(<2 x i32> %c, <2 x half> %x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0xe400, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0xe400, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xe400, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xe400, v2.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_negliteralk_fabs_v2f16:
@@ -1000,15 +982,14 @@ define <2 x half> @add_select_fabs_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16-LABEL: add_select_fabs_posk_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3c00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3c00, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_fabs_posk_v2f16:
@@ -1088,14 +1069,13 @@ define <2 x half> @add_select_posk_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x3c00, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3c00, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_posk_fabs_v2f16:
@@ -1169,13 +1149,10 @@ define <2 x half> @add_select_fneg_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1267,14 +1244,11 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_lhs_fneg_fneg_v2f16(<2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v5, v2 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1357,14 +1331,11 @@ define { <2 x half>, <2 x half> } @add_select_multi_store_use_lhs_fneg_fneg_v2f1
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1459,14 +1430,11 @@ define { <2 x half>, <2 x half> } @add_select_multi_use_rhs_fneg_fneg_v2f16(<2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v5, v3 neg_lo:[0,1] neg_hi:[0,1]
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1548,15 +1516,13 @@ define <2 x half> @add_select_fneg_var_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h
; GFX11-TRUE16-LABEL: add_select_fneg_var_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1635,12 +1601,10 @@ define <2 x half> @add_select_fneg_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1717,12 +1681,10 @@ define <2 x half> @add_select_fneg_inv2pi_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xb118, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xb118, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xb118, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1799,12 +1761,10 @@ define <2 x half> @add_select_fneg_neginv2pi_v2f16(<2 x i32> %c, <2 x half> %x,
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3118, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3118, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3118, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2128,12 +2088,10 @@ define <2 x half> @add_select_negk_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x3c00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3c00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2210,12 +2168,10 @@ define <2 x half> @add_select_fneg_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2292,12 +2248,10 @@ define <2 x half> @add_select_posk_fneg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xbc00, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xbc00, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v3, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2376,18 +2330,15 @@ define <2 x half> @add_select_negfabs_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: add_select_negfabs_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_negfabs_fabs_v2f16:
@@ -2471,18 +2422,15 @@ define <2 x half> @add_select_fabs_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: add_select_fabs_negfabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x80008000, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_fabs_negfabs_v2f16:
@@ -2566,18 +2514,15 @@ define <2 x half> @add_select_neg_fabs_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h
; GFX11-TRUE16-LABEL: add_select_neg_fabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_neg_fabs_v2f16:
@@ -2660,18 +2605,15 @@ define <2 x half> @add_select_fabs_neg_v2f16(<2 x i32> %c, <2 x half> %x, <2 x h
; GFX11-TRUE16-LABEL: add_select_fabs_neg_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80008000, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v2, v4
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v0, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: add_select_fabs_neg_v2f16:
@@ -2751,15 +2693,13 @@ define <2 x half> @add_select_neg_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: add_select_neg_negfabs_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v2.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2839,15 +2779,13 @@ define <2 x half> @add_select_negfabs_neg_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: add_select_negfabs_neg_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v3.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v3.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v3.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, v4, v0 neg_lo:[0,1] neg_hi:[0,1]
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2930,15 +2868,14 @@ define <2 x half> @mul_select_negfabs_posk_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: mul_select_negfabs_posk_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4400, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x4400, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: mul_select_negfabs_posk_v2f16:
@@ -3019,14 +2956,13 @@ define <2 x half> @mul_select_posk_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4400, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x4400, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4400, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4400, v2.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: mul_select_posk_negfabs_v2f16:
@@ -3106,15 +3042,14 @@ define <2 x half> @mul_select_negfabs_negk_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16-LABEL: mul_select_negfabs_negk_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x80008000, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0xc400, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0xc400, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v1.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: mul_select_negfabs_negk_v2f16:
@@ -3195,14 +3130,13 @@ define <2 x half> @mul_select_negk_negfabs_v2f16(<2 x i32> %c, <2 x half> %x, <2
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, 0xc400, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0xc400, v0.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0xc400, v2.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0xc400, v2.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v1, v3
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: mul_select_negk_negfabs_v2f16:
@@ -3293,11 +3227,10 @@ define <2 x half> @select_fneg_posk_src_add_v2f16(<2 x i32> %c, <2 x half> %x, <
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_add_v2f16:
@@ -3371,14 +3304,12 @@ define <2 x half> @select_fneg_posk_src_add_v2f16_nsz(<2 x i32> %c, <2 x half> %
; GFX11-TRUE16-LABEL: select_fneg_posk_src_add_v2f16_nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, -4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_add_v2f16_nsz:
@@ -3463,11 +3394,10 @@ define <2 x half> @select_fneg_posk_src_sub_v2f16(<2 x i32> %c, <2 x half> %x) {
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16:
@@ -3541,14 +3471,12 @@ define <2 x half> @select_fneg_posk_src_sub_v2f16_nsz(<2 x i32> %c, <2 x half> %
; GFX11-TRUE16-LABEL: select_fneg_posk_src_sub_v2f16_nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, v2, 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_sub_v2f16_nsz:
@@ -3621,14 +3549,12 @@ define <2 x half> @select_fneg_posk_src_mul_v2f16(<2 x i32> %c, <2 x half> %x) {
; GFX11-TRUE16-LABEL: select_fneg_posk_src_mul_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_mul_f16 v2, v2, -4.0 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_pk_mul_f16 v1, v2, -4.0 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_mul_v2f16:
@@ -3802,11 +3728,10 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, <
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_fma_v2f16:
@@ -3903,11 +3828,10 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16(<2 x i32> %c, <2 x half> %x,
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x80008000, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16:
@@ -3991,14 +3915,12 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16_nsz(<2 x i32> %c, <2 x half>
; GFX11-TRUE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_pk_fma_f16 v2, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_pk_fma_f16 v1, v2, -4.0, v3 op_sel_hi:[1,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v2.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x4000, v1.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: select_fneg_posk_src_fmad_v2f16_nsz:
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index e3a43047014af8..928a92b88c4c1c 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -1363,13 +1363,11 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
@@ -1392,15 +1390,13 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_safe:
@@ -1462,13 +1458,11 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
@@ -1491,15 +1485,13 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
@@ -1561,13 +1553,11 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
@@ -1590,15 +1580,13 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nsz_flag:
@@ -1704,13 +1692,11 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
@@ -1733,15 +1719,13 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_safe(<2 x half> %a, <2 x half> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_safe:
@@ -1803,13 +1787,11 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
@@ -1832,15 +1814,13 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
@@ -1902,13 +1882,11 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
@@ -1931,15 +1909,13 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nsz_flag(<2 x half> %a, <2 x hal
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3.l, v2.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nsz_flag:
@@ -2065,20 +2041,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
@@ -2109,21 +2081,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_safe:
@@ -2214,20 +2181,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
@@ -2258,21 +2221,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
@@ -2363,20 +2321,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX1170-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
@@ -2407,21 +2361,16 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nsz_flag:
@@ -2571,20 +2520,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
@@ -2615,21 +2560,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_safe(<4 x half> %a, <4 x half> %
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_safe:
@@ -2720,20 +2660,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
@@ -2764,21 +2700,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
@@ -2869,20 +2800,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX1170-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
; GFX1170-TRUE16: ; %bb.0:
; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX1170-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX1170-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1170-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
@@ -2913,21 +2840,16 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nsz_flag(<4 x half> %a, <4 x hal
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v5.l, v4.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v7.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v7.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nsz_flag:
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index d4ff8ed56b7c66..4c335cf31c1c3c 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -1672,17 +1672,13 @@ define <4 x half> @v_vselect_v4f16(<4 x half> %a, <4 x half> %b, <4 x i32> %cond
; GFX11-TRUE16-LABEL: v_vselect_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v5
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v9.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
@@ -1814,28 +1810,20 @@ define <8 x half> @v_vselect_v8f16(<8 x half> %a, <8 x half> %b, <8 x i32> %cond
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 0, v13
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v12
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v11.l, v10.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v13.l, v12.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v16.l, v15.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v7.h, v3.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s5
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v3.l, s6
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2046,56 +2034,40 @@ define <16 x half> @v_vselect_v16f16(<16 x half> %a, <16 x half> %b, <16 x i32>
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 0, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v17
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v18
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v22
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v26
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v30
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 0, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 0, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 0, v21
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 0, v23
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v19
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 0, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v22
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v23
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s7, 0, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s8, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s9, 0, v30
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s10, 0, v29
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s11, 0, v28
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s12, 0, v27
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 0, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v21.l, v20.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v23.l, v22.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v25.l, v24.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v27.l, v26.l, s9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v29.l, v28.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v32.l, v30.l, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s13, 0, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.h, v0.h, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v7.l, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v14.h, v6.h, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v13.h, v5.h, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v13.l, v5.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v12.h, v4.h, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v12.l, v4.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.h, v3.h, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v10.h, v2.h, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v9.h, v1.h, s2
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v10.l, v2.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v11.l, v3.l, s5
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s3, 0, v31
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v31
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v16.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v15.h, v7.h, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_vselect_v16f16:
@@ -2617,75 +2589,44 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_b32 v34, off, s32 offset:28
-; GFX11-TRUE16-NEXT: scratch_load_b32 v35, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_b32 v36, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_b32 v38, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_b32 v39, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_b32 v49, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_b32 v50, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_b32 v51, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_b32 v52, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_b32 v64, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_b32 v65, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_b32 v67, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_b32 v68, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_b32 v34, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_b32 v35, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_b32 v36, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_b32 v38, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v39, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_b32 v49, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_b32 v50, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_b32 v51, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_b32 v52, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_b32 v64, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_b32 v65, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_b32 v67, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_b32 v68, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:108
; GFX11-TRUE16-NEXT: scratch_load_b32 v82, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_b32 v83, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_b32 v83, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_b32 v84, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:96
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v1
+; GFX11-TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_b32 v87, off, s32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(32)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(31)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(30)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s1, 0, v33
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(29)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v34
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(28)
@@ -2737,47 +2678,46 @@ define <32 x half> @v_vselect_v32f16(<32 x half> %a, <32 x half> %b, <32 x i32>
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s26, 0, v82
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v83
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s27, 0, v83
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s27, 0, v84
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s28, 0, v84
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s28, 0, v85
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s29, 0, v85
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s29, 0, v86
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s40, 0, v86
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e64 s40, 0, v87
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v34.l, v96.l, s26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v98.l, v97.l, s27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v100.l, v99.l, s28
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v102.l, v101.l, s29
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v112.l, v103.l, s40
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v114.l, v113.l, s25
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v116.l, v115.l, s24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v118.l, v117.l, s23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v128.l, v119.l, s22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v130.l, v129.l, s21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v132.l, v131.l, s20
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v134.l, v133.l, s19
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v144.l, v135.l, s18
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v146.l, v145.l, s17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v31.l, v147.l, s16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v33.l, v32.l, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v83.l, v15.l, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v87.h, v15.h, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v87.l, v15.l, s27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v30.h, v14.h, s28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v29.h, v13.h, s40
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v28.h, v12.h, s24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v27.h, v11.h, s22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v26.h, v10.h, s20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v25.h, v9.h, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v25.l, v9.l, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v24.h, v8.h, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v24.l, v8.l, s15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v23.h, v7.h, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v23.l, v7.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v22.h, v6.h, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v22.l, v6.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v21.h, v5.h, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v21.l, v5.l, s9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v20.h, v4.h, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v19.h, v3.h, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v18.h, v2.h, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v17.h, v1.h, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v16.h, v0.h, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v17.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v18.l, v2.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v19.l, v3.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v20.l, v4.l, s7
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_vselect_v32f16:
diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
index 62bfc2d7b861c8..2b447a97bd42e1 100644
--- a/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
@@ -12,23 +12,21 @@ define amdgpu_kernel void @v_sext_in_reg_i8_i16_shuffle_vector(ptr addrspace(1)
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v6, 24, v1
-; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v1.l
-; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8
-; GFX11-TRUE16-NEXT: v_bfe_i32 v10, v4, 0, 8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v9, 24, v2
; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8
-; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.h, 8, v2.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.h, 8, v1.l
+; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v1, 0, 8
+; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v1, 24, v1
; GFX11-TRUE16-NEXT: v_bfe_i32 v7, v3, 0, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.l, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v10.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v3.l, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.l, v0.h
-; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.l, v9.l
+; GFX11-TRUE16-NEXT: v_bfe_i32 v6, v2, 0, 8
+; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v3.l, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.l, v9.l
; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.h, v5.l
; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.h, v6.l
; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.h, v7.l
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
index e0ebb7ff1927d0..00c5429269df8a 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
@@ -427,14 +427,10 @@ define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.h, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.h, v6.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.h, v7.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
@@ -466,15 +462,10 @@ define <4 x half> @v_constained_fadd_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: v_add_f16_e32 v1.h, v1.h, v3.h
+; GFX12-SDAG-NEXT: v_add_f16_e32 v0.h, v0.h, v2.h
; GFX12-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_add_f16_e32 v0.h, v6.l, v5.l
-; GFX12-SDAG-NEXT: v_add_f16_e32 v1.h, v7.l, v4.l
+; GFX12-SDAG-NEXT: v_add_f16_e32 v1.l, v1.l, v3.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fadd_v4f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index 88db30099d58ce..2c86ccc5ea4402 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -171,18 +171,10 @@ define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x ha
; GFX11-TRUE16-LABEL: v_constained_fma_v4f16_fpexcept_strict:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
-; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v5.l, v1.l, v3.l
+; GFX11-TRUE16-NEXT: v_fma_f16 v5.h, v1.h, v3.h, v5.h
+; GFX11-TRUE16-NEXT: v_fma_f16 v4.h, v0.h, v2.h, v4.h
; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v8.l, v10.l, v9.l
-; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v6.l, v11.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v5.l, v1.l, v3.l
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
index d8925bf2c9a5fb..9eefa8501ac8c5 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
@@ -499,14 +499,10 @@ define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.h, v6.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.h, v7.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
@@ -538,15 +534,10 @@ define <4 x half> @v_constained_fmul_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v1.h, v1.h, v3.h
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v0.h, v2.h
; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v0.h, v6.l, v5.l
-; GFX12-SDAG-NEXT: v_mul_f16_e32 v1.h, v7.l, v4.l
+; GFX12-SDAG-NEXT: v_mul_f16_e32 v1.l, v1.l, v3.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fmul_v4f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fpext.ll b/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
index 6a4287d3e22e0b..735a21e0dd6fef 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fpext.ll
@@ -70,9 +70,9 @@ define <2 x float> @v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict(<2 x half
; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_fpexcept_strict:
@@ -121,11 +121,10 @@ define <3 x float> @v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict(<3 x half
; GFX11-TRUE16-LABEL: v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_constrained_fpext_v3f16_to_v3f32_fpexcept_strict:
@@ -270,10 +269,9 @@ define <2 x double> @v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict(<2 x hal
; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f64_fpexcept_strict:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -330,13 +328,12 @@ define <3 x double> @v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict(<3 x hal
; GFX11-TRUE16-LABEL: v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[4:5], v3
-; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v3, v0.h
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
+; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
+; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_constrained_fpext_v3f16_to_v2f64_fpexcept_strict:
@@ -558,11 +555,10 @@ define <2 x float> @v_constrained_fpext_v2f16_to_v2f32_noabi(ptr addrspace(1) %p
; GFX11-TRUE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_noabi:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_constrained_fpext_v2f16_to_v2f32_noabi:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
index 3fa3a3c5a98e0c..87068af9d72745 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
@@ -220,10 +220,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
@@ -249,11 +247,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_strict(<2 x half> %x, <2 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_strict:
@@ -321,10 +316,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
@@ -350,11 +343,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_ignore(<2 x half> %x, <2 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_ignore:
@@ -422,10 +412,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
@@ -451,11 +439,8 @@ define <2 x half> @v_constained_fsub_v2f16_fpexcept_maytrap(<2 x half> %x, <2 x
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v1.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v3.l, v2.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v2f16_fpexcept_maytrap:
@@ -533,11 +518,9 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v5.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -574,12 +557,9 @@ define <3 x half> @v_constained_fsub_v3f16_fpexcept_strict(<3 x half> %x, <3 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v5.l, v4.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v3f16_fpexcept_strict:
@@ -665,14 +645,10 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX11-SDAG-TRUE16-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.h, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v0.h, v6.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.h, v7.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
@@ -704,15 +680,10 @@ define <4 x half> @v_constained_fsub_v4f16_fpexcept_strict(<4 x half> %x, <4 x h
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.h, v1.h, v3.h
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v0.h, v2.h
; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v0.h, v6.l, v5.l
-; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.h, v7.l, v4.l
+; GFX12-SDAG-NEXT: v_sub_f16_e32 v1.l, v1.l, v3.l
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: v_constained_fsub_v4f16_fpexcept_strict:
diff --git a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
index 2f3cab4c9ecc39..d8552645fc8c81 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
@@ -128,12 +128,12 @@ define <2 x half> @test_ldexp_v2f16_v2i32(ptr addrspace(1) %out, <2 x half> %a,
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v4, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v3, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v2f16_v2i32:
@@ -241,15 +241,14 @@ define <3 x half> @test_ldexp_v3f16_v3i32(ptr addrspace(1) %out, <3 x half> %a,
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v5, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v5, v6, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v4, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v6, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v3.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v3.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v3f16_v3i32:
@@ -379,18 +378,17 @@ define <4 x half> @test_ldexp_v4f16_v4i32(ptr addrspace(1) %out, <4 x half> %a,
; GFX11-SDAG-TRUE16: ; %bb.0:
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: s_movk_i32 s0, 0x8000
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v0, v7, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v5, v5, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v1, v5, s0, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v4, v4, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v6, v6, s0, 0x7fff
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_med3_i32 v5, v6, s0, 0x7fff
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.h, v3.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v7.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v3.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e32 v1.l, v3.l, v5.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_ldexp_v4f16_v4i32:
diff --git a/llvm/test/CodeGen/AMDGPU/ucmp.ll b/llvm/test/CodeGen/AMDGPU/ucmp.ll
index 2eef0cd806efb0..cbe27b453883a0 100644
--- a/llvm/test/CodeGen/AMDGPU/ucmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/ucmp.ll
@@ -393,21 +393,19 @@ define <2 x i32> @ucmp_v2i16(<2 x i16> %a, <2 x i16> %b) {
; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_gt_u16_e32 vcc_lo, v0.h, v1.h
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.l, v1.l
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v0, -1, v4, vcc_lo
-; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v3.l, v2.l
+; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc_lo
+; GFX12-SDAG-NEXT: v_cmp_ge_u16_e32 vcc_lo, v0.h, v1.h
; GFX12-SDAG-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-NEXT: v_cndmask_b32_e32 v1, -1, v5, vcc_lo
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v1, -1, v3 :: v_dual_mov_b32 v0, v2
; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: ucmp_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 58ccba8b84b56e..305d5a27cc3740 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -1537,9 +1537,8 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; SDAG-GFX11-TRUE16-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_pk_max_i16 v1, v0, 0
-; SDAG-GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1565,9 +1564,8 @@ define i16 @basic_smax_smin_vec_input(<2 x i16> %src) {
; SDAG-GFX12-TRUE16-NEXT: v_pk_min_i16 v0, 0xff, v0 op_sel_hi:[0,1]
; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX12-TRUE16-NEXT: v_pk_max_i16 v1, v0, 0
-; SDAG-GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; SDAG-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1713,9 +1711,8 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; SDAG-GFX11-TRUE16-NEXT: v_pk_max_i16 v0, v0, 0
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_pk_min_i16 v1, 0xff, v0 op_sel_hi:[0,1]
-; SDAG-GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; SDAG-GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1741,9 +1738,8 @@ define i16 @basic_smax_smin_vec_input_rev(<2 x i16> %src) {
; SDAG-GFX12-TRUE16-NEXT: v_pk_max_i16 v0, v0, 0
; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; SDAG-GFX12-TRUE16-NEXT: v_pk_min_i16 v1, 0xff, v0 op_sel_hi:[0,1]
-; SDAG-GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; SDAG-GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; SDAG-GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX12-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; SDAG-GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
index 01b7293dcd7ab4..71b23bb18e58b5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
@@ -1213,9 +1213,7 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i16:
@@ -1249,9 +1247,7 @@ define i16 @test_vector_reduce_add_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v2i16:
@@ -1353,10 +1349,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_add_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v1, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1392,10 +1387,9 @@ define i16 @test_vector_reduce_add_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v1, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v3i16:
@@ -1522,9 +1516,8 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i16:
@@ -1562,9 +1555,8 @@ define i16 @test_vector_reduce_add_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v4i16:
@@ -1725,9 +1717,7 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i16:
@@ -1777,9 +1767,7 @@ define i16 @test_vector_reduce_add_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v8i16:
@@ -2010,9 +1998,7 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i16:
@@ -2082,9 +2068,7 @@ define i16 @test_vector_reduce_add_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_add_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_add_v16i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
index d1c392665c7da8..71baa8abd2886f 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
@@ -70,9 +70,8 @@ define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
@@ -109,9 +108,8 @@ define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v2half:
@@ -221,9 +219,8 @@ define half @test_vector_reduce_fadd_v3half(half %sp, <3 x half> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -264,9 +261,8 @@ define half @test_vector_reduce_fadd_v3half(half %sp, <3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -392,14 +388,12 @@ define half @test_vector_reduce_fadd_v4half(half %sp, <4 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
@@ -446,14 +440,12 @@ define half @test_vector_reduce_fadd_v4half(half %sp, <4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v4half:
@@ -634,22 +626,18 @@ define half @test_vector_reduce_fadd_v8half(half %sp, <8 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v8half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
@@ -718,22 +706,18 @@ define half @test_vector_reduce_fadd_v8half(half %sp, <8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v8half:
@@ -1032,38 +1016,30 @@ define half @test_vector_reduce_fadd_v16half(half %sp, <16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fadd_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v6.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v7.h
; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v8.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v8.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
@@ -1176,38 +1152,30 @@ define half @test_vector_reduce_fadd_v16half(half %sp, <16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v4.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v6.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v6.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v7.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v8.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v8.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fadd_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
index c19c285454a4c0..651b8829574da8 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
@@ -92,10 +92,9 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -131,10 +130,9 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -174,10 +172,9 @@ define half @test_vector_reduce_fmax_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -310,9 +307,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -357,9 +352,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -408,9 +401,7 @@ define half @test_vector_reduce_fmax_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v3half:
@@ -575,9 +566,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -626,9 +615,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -681,9 +668,7 @@ define half @test_vector_reduce_fmax_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v4half:
@@ -932,9 +917,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1010,9 +993,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1092,9 +1073,7 @@ define half @test_vector_reduce_fmax_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v8half:
@@ -1502,29 +1481,20 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v8.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v1.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v2.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v4.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v5.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v6.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v7.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v2.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v3.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v4.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v5.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v7.l, v7.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1632,29 +1602,20 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmax_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX1170-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
@@ -1766,29 +1727,20 @@ define half @test_vector_reduce_fmax_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmax_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
index 3ac13782301dc5..d7461162a37946 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
@@ -55,10 +55,9 @@ define half @test_vector_reduce_fmaximum_v2half(<2 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v2half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -75,9 +74,7 @@ define half @test_vector_reduce_fmaximum_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v2half:
@@ -95,9 +92,7 @@ define half @test_vector_reduce_fmaximum_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v2half:
@@ -177,14 +172,13 @@ define half @test_vector_reduce_fmaximum_v3half(<3 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v3half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -208,9 +202,7 @@ define half @test_vector_reduce_fmaximum_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfc00
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v3half:
@@ -235,9 +227,7 @@ define half @test_vector_reduce_fmaximum_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0xfc00
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v3half:
@@ -341,19 +331,15 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -380,9 +366,8 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v4half:
@@ -402,9 +387,8 @@ define half @test_vector_reduce_fmaximum_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v4half:
@@ -573,34 +557,27 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v8half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v7, v1, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v6.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v7.l, s1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v1.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v1, v0, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v0.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -647,9 +624,7 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v8half:
@@ -675,9 +650,7 @@ define half @test_vector_reduce_fmaximum_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v8half:
@@ -988,63 +961,47 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmaximum_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v11, v0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v5.h
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v8, v1, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v10.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v8.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v9, v0, v4
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v2, v6
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v11.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v0.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v3, v7
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v10, v2, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v9.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v12.l, v11.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v10.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v5.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v1, v5, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.h, v6.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v4.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v4, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v4.h, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v5.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.h, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v9.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.h, v7.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v3, v7
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v4.h, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v4.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v1, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v1.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v2, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1133,9 +1090,7 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
@@ -1171,9 +1126,7 @@ define half @test_vector_reduce_fmaximum_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_maximum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmaximum_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
index b3c0ed6470fa5c..500fbdc208de0d 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
@@ -92,10 +92,9 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -131,10 +130,9 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -174,10 +172,9 @@ define half @test_vector_reduce_fmin_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v1.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -310,9 +307,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -357,9 +352,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -408,9 +401,7 @@ define half @test_vector_reduce_fmin_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v3half:
@@ -575,9 +566,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -626,9 +615,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -681,9 +668,7 @@ define half @test_vector_reduce_fmin_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_num_f16 v0, v0, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v4half:
@@ -932,9 +917,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1010,9 +993,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1092,9 +1073,7 @@ define half @test_vector_reduce_fmin_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_num_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v8half:
@@ -1502,29 +1481,20 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h
; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_max_f16_e32 v0.h, v8.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v1.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v2.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v4.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v5.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v6.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v7.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v1.l, v1.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v2.l, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v3.l, v3.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v4.l, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v5.l, v5.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v6.l, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v7.l, v7.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1632,29 +1602,20 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fmin_v16half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v2.l
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX1170-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
@@ -1766,29 +1727,20 @@ define half @test_vector_reduce_fmin_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v0.h, v0.h
; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_max_num_f16_e32 v0.h, v8.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v8.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v9.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v1.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v2.l, v2.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v3.l, v3.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v4.l, v4.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v5.l, v5.h
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v6.l, v6.h
+; GFX12-SDAG-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v7.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmin_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
index 1ad17d8b89b5a5..e8404a3000c19a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
@@ -59,10 +59,9 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -79,9 +78,7 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX1170-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v2half:
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -115,9 +112,7 @@ define half @test_vector_reduce_fminimum_v2half(<2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v2half:
@@ -221,14 +216,13 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v3half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -252,9 +246,7 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7c00
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
@@ -293,9 +285,7 @@ define half @test_vector_reduce_fminimum_v3half(<3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7c00
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v3half:
@@ -421,19 +411,15 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v3.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v1.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -460,9 +446,8 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX1170-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX1170-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -500,9 +485,8 @@ define half @test_vector_reduce_fminimum_v4half(<4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v4half:
@@ -697,34 +681,27 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v8half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v7, v1, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v6.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v7.l, s1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v1.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v1, v0, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v2.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v4.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v0.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v0.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v1, v0
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.l, v0.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -771,9 +748,7 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -823,9 +798,7 @@ define half @test_vector_reduce_fminimum_v8half(<8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v8half:
@@ -1168,63 +1141,47 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fminimum_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v11, v0, v4
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v5.h
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v8, v1, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v10.l, v9.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v11
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, 0x7e00, v8.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v4.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v9, v0, v4
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.l, v4.l
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v2, v6
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v8.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.l, 0x7e00, v11.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v5.h, 0x7e00, v0.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v0, v3, v7
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v10, v2, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v7
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v9.l, v8.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v10
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v12.l, v11.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v6.l, 0x7e00, v10.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v6.h, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.h, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s3
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v5.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v1, v5, v6
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v5.h, v6.h
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v4.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v4, v0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v4.h, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v1.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v2.l, s1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v5.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v9.h, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v9.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v2.h, v6.h
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v2.l, v6.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v3.h, v7.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v3, v7
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s3, v3.l, v7.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x7e00, v4.h, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x7e00, v4.l, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v8.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.h, 0x7e00, v2.h, s2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, 0x7e00, v2.l, s3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.h, v3.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v1.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s1, v0.h, v2.h
+; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v1, v0, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s2, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v4.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x7e00, v1.h, s1
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_f16 v2, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.h, v1.h
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v3.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e64 s0, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.h, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v2.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.h, v0.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.h, v0.l
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1313,9 +1270,7 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX1170-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX1170-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX1170-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX1170-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
@@ -1385,9 +1340,7 @@ define half @test_vector_reduce_fminimum_v16half(<16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_minimum_f16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fminimum_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
index cd0d7ecb1095b0..dc44dec957332b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
@@ -70,9 +70,8 @@ define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
@@ -109,9 +108,8 @@ define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v2half:
@@ -221,9 +219,8 @@ define half @test_vector_reduce_fmul_v3half(half %sp, <3 x half> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -264,9 +261,8 @@ define half @test_vector_reduce_fmul_v3half(half %sp, <3 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -392,14 +388,12 @@ define half @test_vector_reduce_fmul_v4half(half %sp, <4 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v4half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
@@ -446,14 +440,12 @@ define half @test_vector_reduce_fmul_v4half(half %sp, <4 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v4half:
@@ -634,22 +626,18 @@ define half @test_vector_reduce_fmul_v8half(half %sp, <8 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v8half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
@@ -718,22 +706,18 @@ define half @test_vector_reduce_fmul_v8half(half %sp, <8 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v8half:
@@ -1032,38 +1016,30 @@ define half @test_vector_reduce_fmul_v16half(half %sp, <16 x half> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_fmul_v16half:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v9.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v6.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v6.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v7.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v7.h
; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v8.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v8.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
@@ -1176,38 +1152,30 @@ define half @test_vector_reduce_fmul_v16half(half %sp, <16 x half> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v9.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v3.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v5
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v4.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v5.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v6.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v7
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v6.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v7.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v8
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v7.h
; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v8.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v8.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_fmul_v16half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
index b931b312ff2513..432d4c1b0e8d5e 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
@@ -1297,10 +1297,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_mul_v3i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
@@ -1336,10 +1335,9 @@ define i16 @test_vector_reduce_mul_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v0, v0, v1
+; GFX12-SDAG-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v0, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_mul_v3i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index 219961c35071d6..659882d67d6c83 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -1629,9 +1629,7 @@ define i16 @test_vector_reduce_smax_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i16:
@@ -1657,9 +1655,7 @@ define i16 @test_vector_reduce_smax_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v2i16:
@@ -1759,9 +1755,7 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1794,9 +1788,7 @@ define i16 @test_vector_reduce_smax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x8000
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v3i16:
@@ -1917,9 +1909,8 @@ define i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i16:
@@ -1948,9 +1939,8 @@ define i16 @test_vector_reduce_smax_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v4i16:
@@ -2103,9 +2093,7 @@ define i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i16:
@@ -2143,9 +2131,7 @@ define i16 @test_vector_reduce_smax_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v8i16:
@@ -2368,9 +2354,7 @@ define i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i16:
@@ -2423,9 +2407,7 @@ define i16 @test_vector_reduce_smax_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smax_v16i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 376a64bb862719..09f08d332793e1 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -1629,9 +1629,7 @@ define i16 @test_vector_reduce_smin_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i16:
@@ -1657,9 +1655,7 @@ define i16 @test_vector_reduce_smin_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v2i16:
@@ -1759,9 +1755,7 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1794,9 +1788,7 @@ define i16 @test_vector_reduce_smin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, 0x7fff
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v3i16:
@@ -1917,9 +1909,8 @@ define i16 @test_vector_reduce_smin_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i16:
@@ -1948,9 +1939,8 @@ define i16 @test_vector_reduce_smin_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v4i16:
@@ -2103,9 +2093,7 @@ define i16 @test_vector_reduce_smin_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i16:
@@ -2143,9 +2131,7 @@ define i16 @test_vector_reduce_smin_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v8i16:
@@ -2367,9 +2353,7 @@ define i16 @test_vector_reduce_smin_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i16:
@@ -2422,9 +2406,7 @@ define i16 @test_vector_reduce_smin_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_i16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_smin_v16i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 087832601598a9..7e7da135b05f3a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -1518,9 +1518,7 @@ define i16 @test_vector_reduce_umax_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umax_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i16:
@@ -1546,9 +1544,7 @@ define i16 @test_vector_reduce_umax_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v2i16:
@@ -1644,9 +1640,7 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1678,9 +1672,7 @@ define i16 @test_vector_reduce_umax_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v1, v1.l
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v3i16:
@@ -1797,9 +1789,8 @@ define i16 @test_vector_reduce_umax_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i16:
@@ -1828,9 +1819,8 @@ define i16 @test_vector_reduce_umax_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v4i16:
@@ -1981,9 +1971,7 @@ define i16 @test_vector_reduce_umax_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i16:
@@ -2021,9 +2009,7 @@ define i16 @test_vector_reduce_umax_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v8i16:
@@ -2244,9 +2230,7 @@ define i16 @test_vector_reduce_umax_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i16:
@@ -2299,9 +2283,7 @@ define i16 @test_vector_reduce_umax_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_max_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_max_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umax_v16i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
index 5443cce424a5c0..5527a543f9f5fa 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
@@ -1298,9 +1298,7 @@ define i16 @test_vector_reduce_umin_v2i16(<2 x i16> %v) {
; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_umin_v2i16:
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i16:
@@ -1326,9 +1324,7 @@ define i16 @test_vector_reduce_umin_v2i16(<2 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v2i16:
@@ -1426,9 +1422,7 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1460,9 +1454,7 @@ define i16 @test_vector_reduce_umin_v3i16(<3 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.h, -1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v3i16:
@@ -1576,9 +1568,8 @@ define i16 @test_vector_reduce_umin_v4i16(<4 x i16> %v) {
; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry
; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i16:
@@ -1607,9 +1598,8 @@ define i16 @test_vector_reduce_umin_v4i16(<4 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v4i16:
@@ -1757,9 +1747,7 @@ define i16 @test_vector_reduce_umin_v8i16(<8 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i16:
@@ -1797,9 +1785,7 @@ define i16 @test_vector_reduce_umin_v8i16(<8 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v8i16:
@@ -2017,9 +2003,7 @@ define i16 @test_vector_reduce_umin_v16i16(<16 x i16> %v) {
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i16:
@@ -2072,9 +2056,7 @@ define i16 @test_vector_reduce_umin_v16i16(<16 x i16> %v) {
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v2
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_pk_min_u16 v0, v0, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: test_vector_reduce_umin_v16i16:
diff --git a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
index fca3b5176ce58d..146fe11ae37450 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
@@ -455,10 +455,7 @@ define <2 x i16> @shuffle_v2i16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v2i16_rebroadcast:
@@ -499,10 +496,8 @@ define <4 x i16> @shuffle_v4i16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -550,10 +545,8 @@ define <8 x i16> @shuffle_v8i16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -613,10 +606,8 @@ define <16 x i16> @shuffle_v16i16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -700,10 +691,8 @@ define <32 x i16> @shuffle_v32i16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1079,9 +1068,7 @@ define <2 x bfloat> @shuffle_v2bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v2bf16_rebroadcast:
@@ -1122,10 +1109,8 @@ define <3 x bfloat> @shuffle_v3bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v3bf16_rebroadcast:
@@ -1167,9 +1152,8 @@ define <4 x bfloat> @shuffle_v4bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1215,9 +1199,8 @@ define <6 x bfloat> @shuffle_v6bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1267,9 +1250,8 @@ define <8 x bfloat> @shuffle_v8bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1329,9 +1311,8 @@ define <16 x bfloat> @shuffle_v16bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1415,9 +1396,8 @@ define <32 x bfloat> @shuffle_v32bf16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1487,9 +1467,7 @@ define <2 x half> @shuffle_v2f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v2f16_rebroadcast:
@@ -1530,10 +1508,8 @@ define <3 x half> @shuffle_v3f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v3f16_rebroadcast:
@@ -1575,9 +1551,8 @@ define <4 x half> @shuffle_v4f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1623,9 +1598,8 @@ define <6 x half> @shuffle_v6f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1675,9 +1649,8 @@ define <8 x half> @shuffle_v8f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1737,9 +1710,8 @@ define <16 x half> @shuffle_v16f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
@@ -1823,9 +1795,8 @@ define <32 x half> @shuffle_v32f16_rebroadcast(ptr addrspace(1) %arg0) {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v0
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index a0910fa124f677..ee346785aee2c5 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -212,7 +212,7 @@ define <4 x half> @shuffle_v4f16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -271,7 +271,7 @@ define <4 x half> @shuffle_v4f16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -326,15 +326,12 @@ define <4 x half> @shuffle_v4f16_35u5(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-LABEL: shuffle_v4f16_35u5:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_35u5:
@@ -390,15 +387,11 @@ define <4 x half> @shuffle_v4f16_357u(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-LABEL: shuffle_v4f16_357u:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_357u:
@@ -1005,7 +998,7 @@ define <4 x half> @shuffle_v4f16_2356(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1065,7 +1058,7 @@ define <4 x half> @shuffle_v4f16_5623(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1112,13 +1105,13 @@ define <4 x half> @shuffle_v4f16_3456(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_3456:
@@ -1166,9 +1159,9 @@ define <4 x half> @shuffle_v4f16_5634(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1228,15 +1221,15 @@ define <4 x half> @shuffle_v4f16_5734(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-LABEL: shuffle_v4f16_5734:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_5734:
@@ -1430,7 +1423,7 @@ define <4 x half> @shuffle_v4f16_1010(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
@@ -1486,13 +1479,11 @@ define <4 x half> @shuffle_v4f16_1100(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-LABEL: shuffle_v4f16_1100:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_1100:
@@ -1547,11 +1538,9 @@ define <4 x half> @shuffle_v4f16_6161(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[2:3], off offset:4
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1603,9 +1592,8 @@ define <4 x half> @shuffle_v4f16_2333(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_2333:
@@ -1653,9 +1641,8 @@ define <4 x half> @shuffle_v4f16_6667(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4f16_6667:
@@ -1842,7 +1829,7 @@ define <4 x half> @shuffle_v8f16_13_14_2_3(ptr addrspace(1) %arg0, ptr addrspace
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off offset:8
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -1932,7 +1919,7 @@ define <4 x half> @shuffle_v2f16_0122(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2159,8 +2146,8 @@ define <4 x half> @shuffle_v4f16_0456(ptr addrspace(1) %arg0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2325,14 +2312,10 @@ define <2 x half> @hi16bits_v2f16(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
; GFX11-TRUE16-LABEL: hi16bits_v2f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: hi16bits_v2f16:
@@ -2386,11 +2369,8 @@ define <2 x half> @low16hi16bits_v2f16(ptr addrspace(1) %x0, ptr addrspace(1) %x
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: low16hi16bits_v2f16:
@@ -2434,7 +2414,7 @@ define <2 x half> @hi16low16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1) %
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2545,11 +2525,8 @@ define <2 x i16> @i16_low16hi16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1)
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: i16_low16hi16bits:
@@ -2647,14 +2624,10 @@ define <2 x i16> @i16_hi16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
; GFX11-TRUE16-LABEL: i16_hi16bits:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: i16_hi16bits:
@@ -3529,7 +3502,7 @@ define <4 x bfloat> @shuffle_v4bf16_3u6u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3588,7 +3561,7 @@ define <4 x bfloat> @shuffle_v4bf16_3uu7(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3643,15 +3616,12 @@ define <4 x bfloat> @shuffle_v4bf16_35u5(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-LABEL: shuffle_v4bf16_35u5:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_35u5:
@@ -3707,15 +3677,11 @@ define <4 x bfloat> @shuffle_v4bf16_357u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-LABEL: shuffle_v4bf16_357u:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: global_load_b32 v4, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_357u:
@@ -4322,7 +4288,7 @@ define <4 x bfloat> @shuffle_v4bf16_2356(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -4382,7 +4348,7 @@ define <4 x bfloat> @shuffle_v4bf16_5623(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -4429,13 +4395,13 @@ define <4 x bfloat> @shuffle_v4bf16_3456(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_3456:
@@ -4483,9 +4449,9 @@ define <4 x bfloat> @shuffle_v4bf16_5634(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -4545,15 +4511,15 @@ define <4 x bfloat> @shuffle_v4bf16_5734(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-LABEL: shuffle_v4bf16_5734:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_5734:
@@ -4651,7 +4617,7 @@ define <4 x bfloat> @shuffle_v4bf16_1010(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
@@ -4707,13 +4673,11 @@ define <4 x bfloat> @shuffle_v4bf16_1100(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-LABEL: shuffle_v4bf16_1100:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_1100:
@@ -4768,11 +4732,9 @@ define <4 x bfloat> @shuffle_v4bf16_6161(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[2:3], off offset:4
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.h
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4824,9 +4786,8 @@ define <4 x bfloat> @shuffle_v4bf16_2333(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_2333:
@@ -4874,9 +4835,8 @@ define <4 x bfloat> @shuffle_v4bf16_6667(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: shuffle_v4bf16_6667:
@@ -5063,7 +5023,7 @@ define <4 x bfloat> @shuffle_v8bf16_13_14_2_3(ptr addrspace(1) %arg0, ptr addrsp
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off offset:8
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off offset:4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5153,7 +5113,7 @@ define <4 x bfloat> @shuffle_v2bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5541,46 +5501,40 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v4, v2, v5 :: v_dual_cndmask_b32 v1, v15, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v13, v14, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_dual_fmac_f32 v7, v3, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v2, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v4, 16, 1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v7, 16, 1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v4, 0x7fff
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v7, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v5, v8 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v1, v3, v10
+; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v11, v12, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.h
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.h
; GFX11-TRUE16-NEXT: global_store_b64 v6, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -5752,8 +5706,8 @@ define <4 x bfloat> @shuffle_v4bf16_0456(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-TRUE16-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5860,14 +5814,10 @@ define <2 x bfloat> @hi16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1) %x1)
; GFX11-TRUE16-LABEL: hi16bits_v2bf16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
-; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX11-TRUE16-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: hi16bits_v2bf16:
@@ -5921,11 +5871,8 @@ define <2 x bfloat> @low16hi16bits_v2bf16(ptr addrspace(1) %x0, ptr addrspace(1)
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b32 v2, v[2:3], off
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: low16hi16bits_v2bf16:
@@ -5969,7 +5916,7 @@ define <2 x bfloat> @hi16low16bits(ptr addrspace(1) %x0, ptr addrspace(1) %x1) {
; GFX11-TRUE16-NEXT: global_load_b32 v0, v[0:1], off
; GFX11-TRUE16-NEXT: global_load_b32 v1, v[2:3], off
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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