[llvm] [AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16 (PR #221960)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 8 04:08:24 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Harrison Hao (harrisonGPU)
<details>
<summary>Changes</summary>
Use the high 16 bits of a VGPR directly instead of shifting.
Before:
```
v_lshrrev_b32_e32 v1, 16, v0
v_add_f16_e32 v0.l, v0.l, v1.l
```
After:
```
v_add_f16_e32 v0.l, v0.l, v0.h
```
Example: https://godbolt.org/z/c7bE46hzb
---
Patch is 5.36 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/221960.diff
133 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+6)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+5957-6380)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+672-725)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll (+14-20)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll (+1415-1524)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll (+408-522)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll (+173-170)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll (+60-59)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+2635-2851)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll (+80-1456)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll (+80-1600)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll (+404-436)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll (+80-1744)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll (+80-1888)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll (+80-2032)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll (+80-2176)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll (+80-2320)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+377-403)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll (+33-44)
- (modified) llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/bf16-math.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+4587-4391)
- (modified) llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll (-5)
- (modified) llvm/test/CodeGen/AMDGPU/bitreverse.ll (+2-3)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+54-78)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+36-54)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+36-54)
- (modified) llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll (+16-39)
- (modified) llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll (+1-3)
- (modified) llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (+4-10)
- (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll (+12-20)
- (modified) llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll (+12-20)
- (modified) llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (+10-13)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+21-35)
- (modified) llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll (+5-6)
- (added) llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll (+238)
- (modified) llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll (+66-88)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll (+27-39)
- (modified) llvm/test/CodeGen/AMDGPU/fabs.bf16.ll (+22-32)
- (modified) llvm/test/CodeGen/AMDGPU/fabs.f16.ll (+1-3)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll (+230-304)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+56-95)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll (+5-9)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+3-7)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll (+79-140)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll (+109-174)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll (+109-174)
- (modified) llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll (+109-174)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+6-18)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll (+107-109)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll (+24-26)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll (+1464-1493)
- (modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll (+56-60)
- (modified) llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll (+29-46)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll (+10-11)
- (modified) llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll (+56-60)
- (modified) llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll (+29-46)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll (+23-35)
- (modified) llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll (+21-31)
- (modified) llvm/test/CodeGen/AMDGPU/fpow.ll (+24-36)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll (+230-292)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll (+206-268)
- (modified) llvm/test/CodeGen/AMDGPU/fract-match.ll (+230-55)
- (modified) llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll (+7-9)
- (modified) llvm/test/CodeGen/AMDGPU/fshr.ll (+54-72)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+91-161)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll (+108-172)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll (+108-172)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll (+108-172)
- (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+45-22)
- (modified) llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll (+350-314)
- (modified) llvm/test/CodeGen/AMDGPU/idot4s.ll (+29-31)
- (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+36-43)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll (+60-80)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll (+76-115)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll (+1-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll (+30-25)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll (+42-186)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll (+60-78)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll (+94-122)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.frexp.ll (+16-28)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll (+12-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+12-13)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll (+13-26)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+52-79)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+52-79)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll (+5-15)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+13-33)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll (+102-162)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll (+102-162)
- (modified) llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll (+231-126)
- (modified) llvm/test/CodeGen/AMDGPU/load-atomic-global.ll (+566-304)
- (modified) llvm/test/CodeGen/AMDGPU/load-atomic-local.ll (+558-300)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll (+20-40)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll (+38-70)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll (+38-70)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll (+38-70)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll (+5-6)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll (+2698-2899)
- (modified) llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll (+2698-2899)
- (modified) llvm/test/CodeGen/AMDGPU/repeated-divisor.ll (+6-10)
- (modified) llvm/test/CodeGen/AMDGPU/roundeven.ll (+5-9)
- (modified) llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll (+1-3)
- (modified) llvm/test/CodeGen/AMDGPU/scmp.ll (+7-9)
- (modified) llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll (+180-258)
- (modified) llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll (+144-222)
- (modified) llvm/test/CodeGen/AMDGPU/select.f16.ll (+110-170)
- (modified) llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll (+11-13)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll (+6-15)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll (+3-11)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll (+6-15)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fpext.ll (+18-22)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll (+14-43)
- (modified) llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll (+17-19)
- (modified) llvm/test/CodeGen/AMDGPU/ucmp.ll (+7-9)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+8-12)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll (+14-30)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll (+54-86)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll (+51-99)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll (+86-133)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll (+51-99)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll (+86-133)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll (+54-86)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll (+4-6)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll (+12-30)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll (+12-30)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll (+12-30)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll (+12-30)
- (modified) llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll (+30-59)
- (modified) llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll (+108-161)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index eb23b6fea26b3..5df81c0a8c58f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3554,6 +3554,12 @@ def : GCNPat <
(EXTRACT_SUBREG $a, sub0)
>;
+let True16Predicate = UseRealTrue16Insts in
+def : GCNPat <
+ (i16 (DivergentUnaryFrag<trunc> (i32 (srl_oneuse VGPR_32:$src, (i32 16))))),
+ (EXTRACT_SUBREG VGPR_32:$src, hi16)
+>;
+
def : GCNPat <
(v2i32 (UniformUnaryFrag<trunc> v2i64:$a)),
(v2i32 (REG_SEQUENCE SReg_64,
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 7be6ad4575d69..aaa177348b323 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -7037,145 +7037,73 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-LABEL: bitcast_v32i32_to_v128i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x13 ; 80-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:88
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:84
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:80
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:76
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:72
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:68
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:64
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:60
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:56
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:52
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:48
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:44
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:40
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:36
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:32
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:28
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:24
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:20
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:16
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:12
; GFX11-TRUE16-NEXT: s_clause 0x2
; GFX11-TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v33
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
@@ -7184,103 +7112,71 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[48:49], 24, v[19:20]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[29:30]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[49:50], 24, v[17:18]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[27:28]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[25:26]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[52:53], 24, v[11:12]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[64:65], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[53:54], 24, v[9:10]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[65:66], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 24, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 8, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 8, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 8, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 24, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 8, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 24, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 24, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 16, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 16, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[21:22]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v32
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 24, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 8, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 24, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 8, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 8, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 8, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 8, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 8, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v1
; GFX11-TRUE16-NEXT: .LBB12_2: ; %Flow
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_4
@@ -7336,188 +7232,188 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[54:55], 24, v[7:8]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[66:67], 24, v[1:2]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 24, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v32
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v31
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 24, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 8, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v25
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 8, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 24, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 8, v2...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/221960
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