[llvm] [RISCV] Add ZVBB RUN lines to vpgather-sdnode.ll and vpscatter-sdnode.ll. NFC (PR #220400)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 1 14:57:15 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
This shows that we are able to use vwsll.vi and that the VL optimizer is able to optimize it.
We've had these RUN lines in our downstream since the early days of VL optimizer development internally and we'd like to reduce our diff with upstream.
---
Patch is 91.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/220400.diff
2 Files Affected:
- (modified) llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll (+574-290)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll (+618-312)
``````````diff
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 0856b9a42f826..7da35085dc8a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64ZVBB
define <vscale x 1 x i8> @vpgather_nxv1i8(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_nxv1i8:
@@ -556,21 +560,37 @@ define <vscale x 8 x i16> @vpgather_baseidx_sext_nxv8i8_nxv8i16(ptr %base, <vsca
}
define <vscale x 8 x i16> @vpgather_baseidx_zext_nxv8i8_nxv8i16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -771,23 +791,39 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i8_nxv8i32(ptr %base, <vsca
}
define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i8_nxv8i32(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x i32> @llvm.vp.gather.nxv8i32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -842,23 +878,39 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i16_nxv8i32(ptr %base, <vsc
}
define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i16_nxv8i32(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x i32> @llvm.vp.gather.nxv8i32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1020,23 +1072,39 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(ptr %base, <vsca
}
define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i8_nxv8i64(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1089,23 +1157,39 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(ptr %base, <vsc
}
define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i16_nxv8i64(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1166,14 +1250,22 @@ define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(ptr %base, <vsc
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1339,21 +1431,37 @@ define <vscale x 8 x bfloat> @vpgather_baseidx_sext_nxv8i8_nxv8bf16(ptr %base, <
}
define <vscale x 8 x bfloat> @vpgather_baseidx_zext_nxv8i8_nxv8bf16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds bfloat, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x bfloat> @llvm.vp.gather.nxv8bf16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1519,21 +1627,37 @@ define <vscale x 8 x half> @vpgather_baseidx_sext_nxv8i8_nxv8f16(ptr %base, <vsc
}
define <vscale x 8 x half> @vpgather_baseidx_zext_nxv8i8_nxv8f16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x half> @llvm.vp.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1692,23 +1816,39 @@ define <vscale x 8 x float> @vpgather_baseidx_sext_nxv8i8_nxv8f32(ptr %ba...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/220400
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