[llvm] [RISCV] Add ZVBB RUN lines to vpgather-sdnode.ll and vpscatter-sdnode.ll. NFC (PR #220400)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 1 14:56:39 PDT 2026
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/220400
This shows that we are able to use vwsll.vi and that the VL optimizer is able to optimize it.
We've had these RUN lines in our downstream since the early days of VL optimizer development internally and we'd like to reduce our diff with upstream.
>From ab9b3cafb81954a76c7c80fcd22f71303c5decbb Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 1 Sep 2026 14:51:17 -0700
Subject: [PATCH] [RISCV] Add ZVBB RUN lines to vpgather-sdnode.ll and
vpscatter-sdnode.ll. NFC
This shows that we are able to use vwsll.vi and that the VL optimizer
is able to optimize it.
We've had these RUN lines in our downstream since the early days
of VL optimizer development internally and we'd like to reduce our
diff with upstream.
---
.../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 864 ++++++++++------
.../CodeGen/RISCV/rvv/vpscatter-sdnode.ll | 930 ++++++++++++------
2 files changed, 1192 insertions(+), 602 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 0856b9a42f826..7da35085dc8a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64ZVBB
define <vscale x 1 x i8> @vpgather_nxv1i8(<vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_nxv1i8:
@@ -556,21 +560,37 @@ define <vscale x 8 x i16> @vpgather_baseidx_sext_nxv8i8_nxv8i16(ptr %base, <vsca
}
define <vscale x 8 x i16> @vpgather_baseidx_zext_nxv8i8_nxv8i16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x i16> @llvm.vp.gather.nxv8i16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -771,23 +791,39 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i8_nxv8i32(ptr %base, <vsca
}
define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i8_nxv8i32(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x i32> @llvm.vp.gather.nxv8i32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -842,23 +878,39 @@ define <vscale x 8 x i32> @vpgather_baseidx_sext_nxv8i16_nxv8i32(ptr %base, <vsc
}
define <vscale x 8 x i32> @vpgather_baseidx_zext_nxv8i16_nxv8i32(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x i32> @llvm.vp.gather.nxv8i32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1020,23 +1072,39 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i8_nxv8i64(ptr %base, <vsca
}
define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i8_nxv8i64(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1089,23 +1157,39 @@ define <vscale x 8 x i64> @vpgather_baseidx_sext_nxv8i16_nxv8i64(ptr %base, <vsc
}
define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i16_nxv8i64(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1166,14 +1250,22 @@ define <vscale x 8 x i64> @vpgather_baseidx_zext_nxv8i32_nxv8i64(ptr %base, <vsc
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x i64> @llvm.vp.gather.nxv8i64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1339,21 +1431,37 @@ define <vscale x 8 x bfloat> @vpgather_baseidx_sext_nxv8i8_nxv8bf16(ptr %base, <
}
define <vscale x 8 x bfloat> @vpgather_baseidx_zext_nxv8i8_nxv8bf16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds bfloat, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x bfloat> @llvm.vp.gather.nxv8bf16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1519,21 +1627,37 @@ define <vscale x 8 x half> @vpgather_baseidx_sext_nxv8i8_nxv8f16(ptr %base, <vsc
}
define <vscale x 8 x half> @vpgather_baseidx_zext_nxv8i8_nxv8f16(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v10, v8, v8
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v10, v8, v8
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v10, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v10, v8, v8
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v10, v8, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v10, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
%v = call <vscale x 8 x half> @llvm.vp.gather.nxv8f16.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1692,23 +1816,39 @@ define <vscale x 8 x float> @vpgather_baseidx_sext_nxv8i8_nxv8f32(ptr %base, <vs
}
define <vscale x 8 x float> @vpgather_baseidx_zext_nxv8i8_nxv8f32(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x float> @llvm.vp.gather.nxv8f32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1763,23 +1903,39 @@ define <vscale x 8 x float> @vpgather_baseidx_sext_nxv8i16_nxv8f32(ptr %base, <v
}
define <vscale x 8 x float> @vpgather_baseidx_zext_nxv8i16_nxv8f32(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v12, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v12, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v12, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v8, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <vscale x 8 x i32> %eidxs
%v = call <vscale x 8 x float> @llvm.vp.gather.nxv8f32.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1941,23 +2097,39 @@ define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i8_nxv6f64(ptr %base, <v
}
define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i8_nxv6f64(ptr %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv6i8_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i8> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
%v = call <vscale x 6 x double> @llvm.vp.gather.nxv6f64.nxv6p0(<vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -2010,23 +2182,39 @@ define <vscale x 6 x double> @vpgather_baseidx_sext_nxv6i16_nxv6f64(ptr %base, <
}
define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i16_nxv6f64(ptr %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv6i16_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i16> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
%v = call <vscale x 6 x double> @llvm.vp.gather.nxv6f64.nxv6p0(<vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -2087,14 +2275,22 @@ define <vscale x 6 x double> @vpgather_baseidx_zext_nxv6i32_nxv6f64(ptr %base, <
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv6i32_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
%v = call <vscale x 6 x double> @llvm.vp.gather.nxv6f64.nxv6p0(<vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -2186,23 +2382,39 @@ define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i8_nxv8f64(ptr %base, <v
}
define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i8_nxv8f64(ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei16.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i8_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei16.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2255,23 +2467,39 @@ define <vscale x 8 x double> @vpgather_baseidx_sext_nxv8i16_nxv8f64(ptr %base, <
}
define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i16_nxv8f64(ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v8, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i16_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2332,14 +2560,22 @@ define <vscale x 8 x double> @vpgather_baseidx_zext_nxv8i32_nxv8f64(ptr %base, <
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v8, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v8, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv8i32_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v8, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei64.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
%v = call <vscale x 8 x double> @llvm.vp.gather.nxv8f64.nxv8p0(<vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2534,53 +2770,101 @@ define <vscale x 16 x double> @vpgather_baseidx_sext_nxv16i16_nxv16f64(ptr %base
}
define <vscale x 16 x double> @vpgather_baseidx_zext_nxv16i16_nxv16f64(ptr %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli a3, zero, e16, m4, ta, ma
-; RV32-NEXT: vwmulu.vx v24, v8, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: mv a3, a1
-; RV32-NEXT: bltu a1, a2, .LBB114_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: mv a3, a2
-; RV32-NEXT: .LBB114_2:
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
-; RV32-NEXT: srli a3, a2, 3
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sub a2, a1, a2
-; RV32-NEXT: sltu a1, a1, a2
-; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli a3, zero, e16, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v24, v8, a2
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: bltu a1, a2, .LBB114_2
-; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a3, a2
-; RV64-NEXT: .LBB114_2:
-; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v8, (a0), v24, v0.t
-; RV64-NEXT: srli a3, a2, 3
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a3
-; RV64-NEXT: sub a2, a1, a2
-; RV64-NEXT: sltu a1, a1, a2
-; RV64-NEXT: addi a1, a1, -1
-; RV64-NEXT: and a1, a1, a2
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vluxei32.v v16, (a0), v28, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v24, v8, a2
+; RV32NOZVBB-NEXT: csrr a2, vlenb
+; RV32NOZVBB-NEXT: mv a3, a1
+; RV32NOZVBB-NEXT: bltu a1, a2, .LBB114_2
+; RV32NOZVBB-NEXT: # %bb.1:
+; RV32NOZVBB-NEXT: mv a3, a2
+; RV32NOZVBB-NEXT: .LBB114_2:
+; RV32NOZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v8, (a0), v24, v0.t
+; RV32NOZVBB-NEXT: srli a3, a2, 3
+; RV32NOZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32NOZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV32NOZVBB-NEXT: sub a2, a1, a2
+; RV32NOZVBB-NEXT: sltu a1, a1, a2
+; RV32NOZVBB-NEXT: addi a1, a1, -1
+; RV32NOZVBB-NEXT: and a1, a1, a2
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v24, v8, a2
+; RV64NOZVBB-NEXT: csrr a2, vlenb
+; RV64NOZVBB-NEXT: mv a3, a1
+; RV64NOZVBB-NEXT: bltu a1, a2, .LBB114_2
+; RV64NOZVBB-NEXT: # %bb.1:
+; RV64NOZVBB-NEXT: mv a3, a2
+; RV64NOZVBB-NEXT: .LBB114_2:
+; RV64NOZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v8, (a0), v24, v0.t
+; RV64NOZVBB-NEXT: srli a3, a2, 3
+; RV64NOZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64NOZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV64NOZVBB-NEXT: sub a2, a1, a2
+; RV64NOZVBB-NEXT: sltu a1, a1, a2
+; RV64NOZVBB-NEXT: addi a1, a1, -1
+; RV64NOZVBB-NEXT: and a1, a1, a2
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV32ZVBB-NEXT: vmv1r.v v12, v0
+; RV32ZVBB-NEXT: csrr a2, vlenb
+; RV32ZVBB-NEXT: srli a3, a2, 3
+; RV32ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV32ZVBB-NEXT: sub a3, a1, a2
+; RV32ZVBB-NEXT: sltu a4, a1, a3
+; RV32ZVBB-NEXT: addi a4, a4, -1
+; RV32ZVBB-NEXT: vsetvli a5, zero, e16, m4, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v24, v8, 3
+; RV32ZVBB-NEXT: and a3, a4, a3
+; RV32ZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV32ZVBB-NEXT: bltu a1, a2, .LBB114_2
+; RV32ZVBB-NEXT: # %bb.1:
+; RV32ZVBB-NEXT: mv a1, a2
+; RV32ZVBB-NEXT: .LBB114_2:
+; RV32ZVBB-NEXT: vmv1r.v v0, v12
+; RV32ZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vluxei32.v v8, (a0), v24, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpgather_baseidx_zext_nxv16i16_nxv16f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV64ZVBB-NEXT: vmv1r.v v12, v0
+; RV64ZVBB-NEXT: csrr a2, vlenb
+; RV64ZVBB-NEXT: srli a3, a2, 3
+; RV64ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV64ZVBB-NEXT: sub a3, a1, a2
+; RV64ZVBB-NEXT: sltu a4, a1, a3
+; RV64ZVBB-NEXT: addi a4, a4, -1
+; RV64ZVBB-NEXT: vsetvli a5, zero, e16, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v24, v8, 3
+; RV64ZVBB-NEXT: and a3, a4, a3
+; RV64ZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v16, (a0), v28, v0.t
+; RV64ZVBB-NEXT: bltu a1, a2, .LBB114_2
+; RV64ZVBB-NEXT: # %bb.1:
+; RV64ZVBB-NEXT: mv a1, a2
+; RV64ZVBB-NEXT: .LBB114_2:
+; RV64ZVBB-NEXT: vmv1r.v v0, v12
+; RV64ZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vluxei32.v v8, (a0), v24, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 16 x i16> %idxs to <vscale x 16 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 16 x i64> %eidxs
%v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0(<vscale x 16 x ptr> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
index 7daf16e963027..d441d2ca46830 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v,+m \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v,+m \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v,+m \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32NOZVBB
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v,+m \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64NOZVBB
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+m,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32ZVBB
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+m,+zvbb \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64,RV64ZVBB
define void @vpscatter_nxv1i8(<vscale x 1 x i8> %val, <vscale x 1 x ptr> %ptrs, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpscatter_nxv1i8:
@@ -348,21 +352,37 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v12, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v12, v10, v10
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -413,19 +433,33 @@ define void @vpscatter_baseidx_vpsext_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, p
}
define void @vpscatter_baseidx_vpzext_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwaddu.vv v12, v10, v10
-; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwaddu.vv v12, v10, v10
-; RV64-NEXT: vsoxei32.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i16_nxv8i16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = call <vscale x 8 x i32> @llvm.vp.zext.nxv8i16.nxv8i32(<vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 %evl)
%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i32> %eidxs
call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -463,13 +497,21 @@ define void @vpscatter_baseidx_vpzext_nxv8i32_nxv8i16(<vscale x 8 x i16> %val, p
; RV32-NEXT: vsoxei32.v v8, (a0), v12, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpscatter_baseidx_vpzext_nxv8i32_nxv8i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwaddu.vv v16, v12, v12
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i32_nxv8i16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v16, v12, v12
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vsoxei64.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_vpzext_nxv8i32_nxv8i16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v12, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vsoxei64.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = call <vscale x 8 x i64> @llvm.vp.zext.nxv8i32.nxv8i64(<vscale x 8 x i32> %idxs, <vscale x 8 x i1> %m, i32 %evl)
%ptrs = getelementptr inbounds i16, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8i16.nxv8p0(<vscale x 8 x i16> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -621,23 +663,39 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8i32(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v14, v12, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v14, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v14, v12, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v14, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v14, v12, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v14, v12, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v14, v12, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v14, v12, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
call void @llvm.vp.scatter.nxv8i32.nxv8p0(<vscale x 8 x i32> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -692,23 +750,39 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i16_nxv8i32(<vscale x 8 x i32> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v12, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v12, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v12, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v12, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v12, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v12, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <vscale x 8 x i32> %eidxs
call void @llvm.vp.scatter.nxv8i32.nxv8p0(<vscale x 8 x i32> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -861,23 +935,39 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8i64(<vscale x 8 x i64> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v18, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v18, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8i64.nxv8p0(<vscale x 8 x i64> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -930,23 +1020,39 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i16_nxv8i64(<vscale x 8 x i64> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v20, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v20, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8i64.nxv8p0(<vscale x 8 x i64> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1007,14 +1113,22 @@ define void @vpscatter_baseidx_zext_nxv8i32_nxv8i64(<vscale x 8 x i64> %val, ptr
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v24, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v24, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8i64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v24, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds i64, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8i64.nxv8p0(<vscale x 8 x i64> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1170,21 +1284,37 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8bf16(<vscale x 8 x bfloat> %val,
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v12, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v12, v10, v10
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8bf16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds bfloat, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.vp.scatter.nxv8bf16.nxv8p0(<vscale x 8 x bfloat> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1340,21 +1470,37 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, ptr
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwaddu.vv v12, v10, v10
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwaddu.vv v12, v10, v10
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v12, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwaddu.vv v12, v10, v10
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV32ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f16:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v12, v10, 1
+; RV64ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v12, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
%ptrs = getelementptr inbounds half, ptr %base, <vscale x 8 x i16> %eidxs
call void @llvm.vp.scatter.nxv8f16.nxv8p0(<vscale x 8 x half> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1508,23 +1654,39 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, pt
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8f32(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v14, v12, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v14, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v14, v12, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v14, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v14, v12, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v14, v12, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v14, v12, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v14, v12, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v14, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <vscale x 8 x i32> %eidxs
call void @llvm.vp.scatter.nxv8f32.nxv8p0(<vscale x 8 x float> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1579,23 +1741,39 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, p
}
define void @vpscatter_baseidx_zext_nxv8i16_nxv8f32(<vscale x 8 x float> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 4
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v16, v12, a2
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 4
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v16, v12, a2
-; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v16, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 4
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v16, v12, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 4
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v16, v12, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v16, v12, 2
+; RV32ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f32:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v16, v12, 2
+; RV64ZVBB-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v16, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <vscale x 8 x i32> %eidxs
call void @llvm.vp.scatter.nxv8f32.nxv8p0(<vscale x 8 x float> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -1748,23 +1926,39 @@ define void @vpscatter_baseidx_sext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, p
}
define void @vpscatter_baseidx_zext_nxv6i8_nxv6f64(<vscale x 6 x double> %val, ptr %base, <vscale x 6 x i8> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v18, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v18, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv6i8_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i8> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
call void @llvm.vp.scatter.nxv6f64.nxv6p0(<vscale x 6 x double> %val, <vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -1817,23 +2011,39 @@ define void @vpscatter_baseidx_sext_nxv6i16_nxv6f64(<vscale x 6 x double> %val,
}
define void @vpscatter_baseidx_zext_nxv6i16_nxv6f64(<vscale x 6 x double> %val, ptr %base, <vscale x 6 x i16> %idxs, <vscale x 6 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v20, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v20, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv6i16_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i16> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
call void @llvm.vp.scatter.nxv6f64.nxv6p0(<vscale x 6 x double> %val, <vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -1894,14 +2104,22 @@ define void @vpscatter_baseidx_zext_nxv6i32_nxv6f64(<vscale x 6 x double> %val,
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v24, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v24, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv6i32_nxv6f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v24, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 6 x i32> %idxs to <vscale x 6 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 6 x i64> %eidxs
call void @llvm.vp.scatter.nxv6f64.nxv6p0(<vscale x 6 x double> %val, <vscale x 6 x ptr> %ptrs, <vscale x 6 x i1> %m, i32 %evl)
@@ -1991,23 +2209,39 @@ define void @vpscatter_baseidx_sext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, p
}
define void @vpscatter_baseidx_zext_nxv8i8_nxv8f64(<vscale x 8 x double> %val, ptr %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV32-NEXT: vwmulu.vx v18, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; RV64-NEXT: vwmulu.vx v18, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei16.v v8, (a0), v18, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v18, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i8_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v18, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei16.v v8, (a0), v18, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8f64.nxv8p0(<vscale x 8 x double> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2060,23 +2294,39 @@ define void @vpscatter_baseidx_sext_nxv8i16_nxv8f64(<vscale x 8 x double> %val,
}
define void @vpscatter_baseidx_zext_nxv8i16_nxv8f64(<vscale x 8 x double> %val, ptr %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 8
-; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV32-NEXT: vwmulu.vx v20, v16, a2
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
-; RV64-NEXT: vwmulu.vx v20, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v20, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: li a2, 8
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV32NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v20, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV32ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i16_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v20, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v20, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i16> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8f64.nxv8p0(<vscale x 8 x double> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2137,14 +2387,22 @@ define void @vpscatter_baseidx_zext_nxv8i32_nxv8f64(<vscale x 8 x double> %val,
; RV32-NEXT: vsoxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret
;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64:
-; RV64: # %bb.0:
-; RV64-NEXT: li a2, 8
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v24, v16, a2
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
-; RV64-NEXT: ret
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: li a2, 8
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v24, v16, a2
+; RV64NOZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv8i32_nxv8f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v24, v16, 3
+; RV64ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei64.v v8, (a0), v24, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 8 x i32> %idxs to <vscale x 8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 8 x i64> %eidxs
call void @llvm.vp.scatter.nxv8f64.nxv8p0(<vscale x 8 x double> %val, <vscale x 8 x ptr> %ptrs, <vscale x 8 x i1> %m, i32 %evl)
@@ -2387,55 +2645,103 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
}
define void @vpscatter_baseidx_zext_nxv16i16_nxv16f64(<vscale x 16 x double> %val, ptr %base, <vscale x 16 x i16> %idxs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
-; RV32: # %bb.0:
-; RV32-NEXT: vl4re16.v v4, (a1)
-; RV32-NEXT: li a1, 8
-; RV32-NEXT: vsetvli a3, zero, e16, m4, ta, ma
-; RV32-NEXT: vwmulu.vx v24, v4, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: mv a3, a2
-; RV32-NEXT: bltu a2, a1, .LBB111_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: mv a3, a1
-; RV32-NEXT: .LBB111_2:
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
-; RV32-NEXT: srli a3, a1, 3
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sub a1, a2, a1
-; RV32-NEXT: sltu a2, a2, a1
-; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: and a1, a2, a1
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsoxei32.v v16, (a0), v28, v0.t
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
-; RV64: # %bb.0:
-; RV64-NEXT: vl4re16.v v4, (a1)
-; RV64-NEXT: li a1, 8
-; RV64-NEXT: vsetvli a3, zero, e16, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v24, v4, a1
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: mv a3, a2
-; RV64-NEXT: bltu a2, a1, .LBB111_2
-; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a3, a1
-; RV64-NEXT: .LBB111_2:
-; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; RV64-NEXT: vsoxei32.v v8, (a0), v24, v0.t
-; RV64-NEXT: srli a3, a1, 3
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a3
-; RV64-NEXT: sub a1, a2, a1
-; RV64-NEXT: sltu a2, a2, a1
-; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: and a1, a2, a1
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei32.v v16, (a0), v28, v0.t
-; RV64-NEXT: ret
+; RV32NOZVBB-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
+; RV32NOZVBB: # %bb.0:
+; RV32NOZVBB-NEXT: vl4re16.v v4, (a1)
+; RV32NOZVBB-NEXT: li a1, 8
+; RV32NOZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV32NOZVBB-NEXT: vwmulu.vx v24, v4, a1
+; RV32NOZVBB-NEXT: csrr a1, vlenb
+; RV32NOZVBB-NEXT: mv a3, a2
+; RV32NOZVBB-NEXT: bltu a2, a1, .LBB111_2
+; RV32NOZVBB-NEXT: # %bb.1:
+; RV32NOZVBB-NEXT: mv a3, a1
+; RV32NOZVBB-NEXT: .LBB111_2:
+; RV32NOZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v8, (a0), v24, v0.t
+; RV32NOZVBB-NEXT: srli a3, a1, 3
+; RV32NOZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32NOZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV32NOZVBB-NEXT: sub a1, a2, a1
+; RV32NOZVBB-NEXT: sltu a2, a2, a1
+; RV32NOZVBB-NEXT: addi a2, a2, -1
+; RV32NOZVBB-NEXT: and a1, a2, a1
+; RV32NOZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32NOZVBB-NEXT: vsoxei32.v v16, (a0), v28, v0.t
+; RV32NOZVBB-NEXT: ret
+;
+; RV64NOZVBB-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
+; RV64NOZVBB: # %bb.0:
+; RV64NOZVBB-NEXT: vl4re16.v v4, (a1)
+; RV64NOZVBB-NEXT: li a1, 8
+; RV64NOZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV64NOZVBB-NEXT: vwmulu.vx v24, v4, a1
+; RV64NOZVBB-NEXT: csrr a1, vlenb
+; RV64NOZVBB-NEXT: mv a3, a2
+; RV64NOZVBB-NEXT: bltu a2, a1, .LBB111_2
+; RV64NOZVBB-NEXT: # %bb.1:
+; RV64NOZVBB-NEXT: mv a3, a1
+; RV64NOZVBB-NEXT: .LBB111_2:
+; RV64NOZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v8, (a0), v24, v0.t
+; RV64NOZVBB-NEXT: srli a3, a1, 3
+; RV64NOZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64NOZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV64NOZVBB-NEXT: sub a1, a2, a1
+; RV64NOZVBB-NEXT: sltu a2, a2, a1
+; RV64NOZVBB-NEXT: addi a2, a2, -1
+; RV64NOZVBB-NEXT: and a1, a2, a1
+; RV64NOZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64NOZVBB-NEXT: vsoxei32.v v16, (a0), v28, v0.t
+; RV64NOZVBB-NEXT: ret
+;
+; RV32ZVBB-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
+; RV32ZVBB: # %bb.0:
+; RV32ZVBB-NEXT: vl4re16.v v4, (a1)
+; RV32ZVBB-NEXT: csrr a1, vlenb
+; RV32ZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV32ZVBB-NEXT: vwsll.vi v24, v4, 3
+; RV32ZVBB-NEXT: mv a3, a2
+; RV32ZVBB-NEXT: bltu a2, a1, .LBB111_2
+; RV32ZVBB-NEXT: # %bb.1:
+; RV32ZVBB-NEXT: mv a3, a1
+; RV32ZVBB-NEXT: .LBB111_2:
+; RV32ZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v8, (a0), v24, v0.t
+; RV32ZVBB-NEXT: srli a3, a1, 3
+; RV32ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV32ZVBB-NEXT: sub a1, a2, a1
+; RV32ZVBB-NEXT: sltu a2, a2, a1
+; RV32ZVBB-NEXT: addi a2, a2, -1
+; RV32ZVBB-NEXT: and a1, a2, a1
+; RV32ZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32ZVBB-NEXT: vsoxei32.v v16, (a0), v28, v0.t
+; RV32ZVBB-NEXT: ret
+;
+; RV64ZVBB-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
+; RV64ZVBB: # %bb.0:
+; RV64ZVBB-NEXT: vl4re16.v v4, (a1)
+; RV64ZVBB-NEXT: csrr a1, vlenb
+; RV64ZVBB-NEXT: vsetvli a3, zero, e16, m4, ta, ma
+; RV64ZVBB-NEXT: vwsll.vi v24, v4, 3
+; RV64ZVBB-NEXT: mv a3, a2
+; RV64ZVBB-NEXT: bltu a2, a1, .LBB111_2
+; RV64ZVBB-NEXT: # %bb.1:
+; RV64ZVBB-NEXT: mv a3, a1
+; RV64ZVBB-NEXT: .LBB111_2:
+; RV64ZVBB-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v8, (a0), v24, v0.t
+; RV64ZVBB-NEXT: srli a3, a1, 3
+; RV64ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; RV64ZVBB-NEXT: sub a1, a2, a1
+; RV64ZVBB-NEXT: sltu a2, a2, a1
+; RV64ZVBB-NEXT: addi a2, a2, -1
+; RV64ZVBB-NEXT: and a1, a2, a1
+; RV64ZVBB-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64ZVBB-NEXT: vsoxei32.v v16, (a0), v28, v0.t
+; RV64ZVBB-NEXT: ret
%eidxs = zext <vscale x 16 x i16> %idxs to <vscale x 16 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 16 x i64> %eidxs
call void @llvm.vp.scatter.nxv16f64.nxv16p0(<vscale x 16 x double> %val, <vscale x 16 x ptr> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
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