[llvm] [AMDGPU] Fix uniform fcopysign pattern (PR #218644)

[Jay Foad via llvm-commits]

jayfoad wrote:

> From the macro, the lo16 is actually corresponding to bit 2 in 32bit reg, and hi16 is 0x1:

I'm not sure this is right. These subreg index values should go through TRI->getSubRegIndexLaneMask which will convert them into a more sensible bit mask format. lo16 should be 0b01, hi16 should be 0b10, sub0 should be 0b11, sub1 should be 0b1100, etc.

https://github.com/llvm/llvm-project/pull/218644