[llvm] [AMDGPU] Fix uniform fcopysign pattern (PR #218644)

[Jay Foad via llvm-commits]

jayfoad wrote:

It sounds like DetectDeadLanes is making (reasonable) assumptions that the def and use of a register will have the same width. But instructions like this:

  %37:vgpr_32 = REG_SEQUENCE %53:vgpr_32, %subreg.lo16, %38:sreg_32, %subreg.hi16

are weird because they use "%53:vgpr_32" and "%38:sreg_32" (both 32-bit vregs) as 16-bit inputs. Is this even legal? What does it mean?

https://github.com/llvm/llvm-project/pull/218644