[llvm] [AMDGPU] Fix uniform fcopysign pattern (PR #218644)

Tue Aug 25 23:37:22 PDT 2026

================
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -stop-after=amdgpu-isel -o - %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -verify-machineinstrs -o - %s | FileCheck --check-prefix=ASM %s
+
+define void @uniform_fcopysign(ptr addrspace(1) inreg %out, ptr addrspace(1) inreg %in) {
+; ASM-LABEL: uniform_fcopysign:
+; ASM:       ; %bb.0: ; %entry
+; ASM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; ASM-NEXT:    v_mov_b32_e32 v0, 0
+; ASM-NEXT:    global_load_d16_b16 v0, v0, s[2:3]
+; ASM-NEXT:    s_waitcnt vmcnt(0)
+; ASM-NEXT:    v_cmp_ge_f16_e32 vcc_lo, 0, v0.l
+; ASM-NEXT:    s_cbranch_vccz .LBB0_2
+; ASM-NEXT:  ; %bb.1: ; %negative
+; ASM-NEXT:    v_mul_f16_e32 v1.l, 0x4200, v0.l
+; ASM-NEXT:    s_mov_b32 s2, 0
+; ASM-NEXT:    s_branch .LBB0_3
+; ASM-NEXT:  .LBB0_2:
+; ASM-NEXT:    s_mov_b32 s2, -1
+; ASM-NEXT:    ; implicit-def: $vgpr1
+; ASM-NEXT:  .LBB0_3: ; %Flow
+; ASM-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; ASM-NEXT:    s_and_b32 s2, s2, exec_lo
+; ASM-NEXT:    s_cselect_b32 s2, 1, 0
+; ASM-NEXT:    s_cmp_lg_u32 s2, 1
+; ASM-NEXT:    s_cbranch_scc1 .LBB0_5
+; ASM-NEXT:  ; %bb.4: ; %positive
+; ASM-NEXT:    v_add_f16_e32 v1.l, v0.l, v0.l
+; ASM-NEXT:  .LBB0_5: ; %exit
+; ASM-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; ASM-NEXT:    v_bfi_b32 v0, 0x7fff, v1, v0
+; ASM-NEXT:    v_mov_b32_e32 v1, 0
+; ASM-NEXT:    global_store_b16 v1, v0, s[0:1]
+; ASM-NEXT:    s_setpc_b64 s[30:31]
+; CHECK-LABEL: name: uniform_fcopysign
+; CHECK: bb.0.entry:
+; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
+; CHECK-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr3
+; CHECK-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr2
+; CHECK-NEXT:   [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
+; CHECK-NEXT:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
+; CHECK-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
+; CHECK-NEXT:   [[COPY4:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[REG_SEQUENCE]]
+; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT:   [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 killed [[REG_SEQUENCE1]], killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s16) from %ir.in, addrspace 1)
+; CHECK-NEXT:   [[COPY5:%[0-9]+]]:sreg_32 = COPY [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]]
+; CHECK-NEXT:   [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 0, 0, implicit $exec
+; CHECK-NEXT:   [[V_CMP_LE_F16_t16_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_LE_F16_t16_e64 0, [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], 0, killed [[V_MOV_B16_t16_e64_]], 0, 0, implicit $mode, implicit $exec
+; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
+; CHECK-NEXT:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+; CHECK-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_F16_t16_e64_]], implicit-def dead $scc
+; CHECK-NEXT:   $vcc_lo = COPY [[S_AND_B32_]]
+; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit $vcc
+; CHECK-NEXT:   S_BRANCH %bb.1
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT: bb.1.Flow:
+; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[DEF]], %bb.0, %4, %bb.3
+; CHECK-NEXT:   [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %28, %bb.3
+; CHECK-NEXT:   $scc = COPY [[PHI1]]
+; CHECK-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 1, 0, implicit $scc
+; CHECK-NEXT:   [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+; CHECK-NEXT:   S_CMP_LG_U32 killed [[S_CSELECT_B32_]], killed [[S_MOV_B32_1]], implicit-def $scc
+; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.4, implicit $scc
+; CHECK-NEXT:   S_BRANCH %bb.2
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT: bb.2.positive:
+; CHECK-NEXT:   successors: %bb.4(0x80000000)
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT:   [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY5]], 0, [[COPY5]], 0, 0, 0, implicit $mode, implicit $exec
+; CHECK-NEXT:   [[COPY6:%[0-9]+]]:sreg_32 = COPY [[V_ADD_F16_t16_e64_]]
+; CHECK-NEXT:   S_BRANCH %bb.4
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT: bb.3.negative:
+; CHECK-NEXT:   successors: %bb.1(0x80000000)
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT:   [[V_MOV_B16_t16_e64_1:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 16896, 0, implicit $exec
+; CHECK-NEXT:   [[V_MUL_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MUL_F16_t16_e64 0, [[COPY5]], 0, killed [[V_MOV_B16_t16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec
+; CHECK-NEXT:   [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+; CHECK-NEXT:   [[COPY7:%[0-9]+]]:sreg_32 = COPY [[V_MUL_F16_t16_e64_]]
+; CHECK-NEXT:   S_BRANCH %bb.1
+; CHECK-NEXT: {{  $}}
+; CHECK-NEXT: bb.4.exit:
+; CHECK-NEXT:   [[PHI2:%[0-9]+]]:sreg_32 = PHI [[PHI]], %bb.1, [[COPY6]], %bb.2
+; CHECK-NEXT:   [[COPY8:%[0-9]+]]:vgpr_16 = COPY [[COPY5]]
+; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+; CHECK-NEXT:   [[REG_SEQUENCE2:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[COPY8]], %subreg.lo16, [[DEF1]], %subreg.hi16
+; CHECK-NEXT:   [[COPY9:%[0-9]+]]:vgpr_16 = COPY [[PHI2]]
+; CHECK-NEXT:   [[DEF3:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+; CHECK-NEXT:   [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+; CHECK-NEXT:   [[REG_SEQUENCE3:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[COPY9]], %subreg.lo16, [[DEF3]], %subreg.hi16
+; CHECK-NEXT:   [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
+; CHECK-NEXT:   [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 killed [[S_MOV_B32_3]], killed [[REG_SEQUENCE3]], killed [[REG_SEQUENCE2]], implicit $exec
+; CHECK-NEXT:   [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_BFI_B32_e64_]].lo16
+; CHECK-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+; CHECK-NEXT:   [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
+; CHECK-NEXT:   GLOBAL_STORE_SHORT_SADDR_t16 killed [[V_MOV_B32_e32_1]], killed [[COPY11]], [[COPY4]], 0, 0, implicit $exec :: (store (s16) into %ir.out, addrspace 1)
+; CHECK-NEXT:   SI_RETURN
+entry:
----------------
Shoreshen wrote:

Hi @jayfoad , the case seems has to be like this, I tried multiple versions but most of them will be effected by other optimization......

https://github.com/llvm/llvm-project/pull/218644
