[llvm] [Reassociate] Improve handling of fadd/fmul pairs (PR #218675)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 25 05:43:10 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Hari Limaye (hazzlim)
<details>
<summary>Changes</summary>
Currently fadd/fmul pairs are treated as leaf nodes in order to preserve pairs of instructions likely to result in FMA generation. However, doing this unconditionally can prevent reassociation of deeper expression trees. This commit fixes that by preserving an fadd/fmul pair as a leaf only when the other operand of the fadd is not itself a reassociable fadd expression.
---
Patch is 25.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218675.diff
4 Files Affected:
- (modified) llvm/lib/Transforms/Scalar/Reassociate.cpp (+8-3)
- (modified) llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll (+31-32)
- (modified) llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll (+70-70)
- (modified) llvm/test/Transforms/Reassociate/fma-pairs.ll (+10-14)
``````````diff
diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index bd040df55007e..59c29ebeb21ee 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -182,6 +182,10 @@ static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1,
/// operand, both allowing contraction. Such pairs can be fused into a single
/// fma, so they are kept together as leaves of the enclosing expression tree
/// instead of being linearized into it.
+///
+/// Do not keep the pair together if the other operand is itself a reassociable
+/// fadd. Treating the outer fadd as a leaf would hide the nested addition from
+/// reassociation and prevent the complete expression from being optimized.
static BinaryOperator *isFMulAddCandidate(Value *V) {
BinaryOperator *FAdd = isReassociableOp(V, Instruction::FAdd);
if (!FAdd || !FAdd->hasAllowContract())
@@ -192,10 +196,11 @@ static BinaryOperator *isFMulAddCandidate(Value *V) {
};
BinaryOperator *Mul = nullptr, *OtherMul = nullptr;
Value *OtherOp = nullptr;
- // Keep constants visible to the enclosing expression so they still can be
- // folded there.
+ // Keep constants and nested additions visible to the enclosing expression so
+ // they can participate in folding and reassociation.
if (!match(FAdd, m_c_FAdd(ContractableFMul(Mul), m_Value(OtherOp))) ||
- isa<Constant>(OtherOp) || match(OtherOp, ContractableFMul(OtherMul)))
+ isa<Constant>(OtherOp) || isReassociableOp(OtherOp, Instruction::FAdd) ||
+ match(OtherOp, ContractableFMul(OtherMul)))
return nullptr;
return Mul;
}
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll
index 63478d24837b0..33df34fd80713 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll
@@ -11,60 +11,59 @@ define double @md_vdw_energy(ptr nocapture readonly %coeffs, double %energy, dou
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = fmul fast double [[TABLE_DELTA]], [[TABLE_DELTA]]
; CHECK-NEXT: [[FACTOR_OP_FMUL:%.*]] = fmul fast double [[TMP0]], f0x3FC5555555555555
-; CHECK-NEXT: [[FACTOR_OP_FMUL5:%.*]] = fmul fast double [[TABLE_DELTA]], -5.000000e-01
-; CHECK-NEXT: [[TMP1:%.*]] = fneg fast double [[TABLE_DELTA]]
-; CHECK-NEXT: [[FACTOR_OP_FMUL6:%.*]] = fmul fast double [[FACTOR_OP_FMUL]], [[TMP1]]
-; CHECK-NEXT: [[FACTOR_OP_FMUL7:%.*]] = fmul fast double [[TMP0]], -2.500000e-01
+; CHECK-NEXT: [[FACTOR_OP_FMUL2:%.*]] = fmul fast double [[TABLE_DELTA]], 5.000000e-01
+; CHECK-NEXT: [[FACTOR_OP_FMUL3:%.*]] = fmul fast double [[FACTOR_OP_FMUL]], [[TABLE_DELTA]]
+; CHECK-NEXT: [[FACTOR_OP_FMUL4:%.*]] = fmul fast double [[TMP0]], 2.500000e-01
+; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[SCALE]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[ACC:%.*]] = phi double [ [[ENERGY]], %[[ENTRY]] ], [ [[RESULT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[ACC1:%.*]] = phi double [ [[ENERGY]], %[[ENTRY]] ], [ [[RESULT1:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[BASE:%.*]] = getelementptr inbounds [8 x i8], ptr [[COEFFS]], i64 [[I]]
-; CHECK-NEXT: [[A:%.*]] = load double, ptr [[BASE]], align 8
-; CHECK-NEXT: [[B_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 8
-; CHECK-NEXT: [[B:%.*]] = load double, ptr [[B_PTR]], align 8
-; CHECK-NEXT: [[AB:%.*]] = fmul fast double [[A]], [[SCALE]]
-; CHECK-NEXT: [[BB:%.*]] = fmul fast double [[B]], [[SCALE]]
; CHECK-NEXT: [[C0_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 16
; CHECK-NEXT: [[C0:%.*]] = load double, ptr [[C0_PTR]], align 8
; CHECK-NEXT: [[C1_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 24
; CHECK-NEXT: [[C1:%.*]] = load double, ptr [[C1_PTR]], align 8
-; CHECK-NEXT: [[P0:%.*]] = fmul fast double [[C0]], [[AB]]
-; CHECK-NEXT: [[Q0:%.*]] = fmul fast double [[C1]], [[BB]]
-; CHECK-NEXT: [[D0:%.*]] = fsub fast double [[P0]], [[Q0]]
; CHECK-NEXT: [[C2_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 32
; CHECK-NEXT: [[C2:%.*]] = load double, ptr [[C2_PTR]], align 8
; CHECK-NEXT: [[C3_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 40
; CHECK-NEXT: [[C3:%.*]] = load double, ptr [[C3_PTR]], align 8
-; CHECK-NEXT: [[P1:%.*]] = fmul fast double [[C2]], [[AB]]
-; CHECK-NEXT: [[Q1:%.*]] = fmul fast double [[C3]], [[BB]]
-; CHECK-NEXT: [[D1:%.*]] = fsub fast double [[P1]], [[Q1]]
; CHECK-NEXT: [[C4_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 48
; CHECK-NEXT: [[C4:%.*]] = load double, ptr [[C4_PTR]], align 8
; CHECK-NEXT: [[C5_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 56
; CHECK-NEXT: [[C5:%.*]] = load double, ptr [[C5_PTR]], align 8
-; CHECK-NEXT: [[P2:%.*]] = fmul fast double [[C4]], [[AB]]
-; CHECK-NEXT: [[Q2:%.*]] = fmul fast double [[C5]], [[BB]]
-; CHECK-NEXT: [[D2:%.*]] = fsub fast double [[P2]], [[Q2]]
; CHECK-NEXT: [[C6_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 64
-; CHECK-NEXT: [[C6:%.*]] = load double, ptr [[C6_PTR]], align 8
-; CHECK-NEXT: [[C7_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 72
-; CHECK-NEXT: [[C7:%.*]] = load double, ptr [[C7_PTR]], align 8
-; CHECK-NEXT: [[T1_REASS_REASS_REASS:%.*]] = fmul fast double [[FACTOR_OP_FMUL6]], [[D0]]
-; CHECK-NEXT: [[T2_REASS_REASS_REASS:%.*]] = fmul fast double [[D1]], [[FACTOR_OP_FMUL7]]
-; CHECK-NEXT: [[S0:%.*]] = fadd fast double [[T2_REASS_REASS_REASS]], [[T1_REASS_REASS_REASS]]
-; CHECK-NEXT: [[T4_REASS_REASS:%.*]] = fmul fast double [[D2]], [[FACTOR_OP_FMUL5]]
-; CHECK-NEXT: [[S1:%.*]] = fadd fast double [[S0]], [[T4_REASS_REASS]]
-; CHECK-NEXT: [[Q3_NEG_NEG:%.*]] = fmul fast double [[C7]], [[BB]]
-; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[AB]], [[C6]]
+; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[BASE]], align 8
+; CHECK-NEXT: [[TMP4:%.*]] = fmul fast <2 x double> [[TMP3]], [[TMP11]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
+; CHECK-NEXT: [[P2:%.*]] = fmul fast double [[C0]], [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP4]], i64 1
+; CHECK-NEXT: [[Q2:%.*]] = fmul fast double [[C1]], [[TMP6]]
+; CHECK-NEXT: [[D2:%.*]] = fsub fast double [[P2]], [[Q2]]
+; CHECK-NEXT: [[P1:%.*]] = fmul fast double [[C2]], [[TMP5]]
+; CHECK-NEXT: [[Q1:%.*]] = fmul fast double [[C3]], [[TMP6]]
+; CHECK-NEXT: [[D1:%.*]] = fsub fast double [[P1]], [[Q1]]
+; CHECK-NEXT: [[ACC:%.*]] = fmul fast double [[C4]], [[TMP5]]
+; CHECK-NEXT: [[TMP2:%.*]] = fmul fast double [[C5]], [[TMP6]]
; CHECK-NEXT: [[D3_NEG:%.*]] = fsub fast double [[ACC]], [[TMP2]]
-; CHECK-NEXT: [[S2_NEG:%.*]] = fadd fast double [[Q3_NEG_NEG]], [[D3_NEG]]
-; CHECK-NEXT: [[RESULT]] = fadd fast double [[S1]], [[S2_NEG]]
+; CHECK-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr [[C6_PTR]], align 8
+; CHECK-NEXT: [[T1_REASS_REASS:%.*]] = fmul fast double [[FACTOR_OP_FMUL3]], [[D2]]
+; CHECK-NEXT: [[T2_REASS_REASS:%.*]] = fmul fast double [[D1]], [[FACTOR_OP_FMUL4]]
+; CHECK-NEXT: [[S1:%.*]] = fadd fast double [[T2_REASS_REASS]], [[T1_REASS_REASS]]
+; CHECK-NEXT: [[S2_NEG:%.*]] = fmul fast double [[D3_NEG]], [[FACTOR_OP_FMUL2]]
+; CHECK-NEXT: [[RESULT:%.*]] = fadd fast double [[S1]], [[S2_NEG]]
+; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <2 x double> [[TMP7]], [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x double> [[TMP8]], i64 0
+; CHECK-NEXT: [[REASS_ADD:%.*]] = fadd fast double [[RESULT]], [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP8]], i64 1
+; CHECK-NEXT: [[S2_NEG1:%.*]] = fadd fast double [[ACC1]], [[TMP10]]
+; CHECK-NEXT: [[RESULT1]] = fsub fast double [[S2_NEG1]], [[REASS_ADD]]
; CHECK-NEXT: [[NEXT]] = add nuw i64 [[I]], 10
; CHECK-NEXT: [[DONE_NOT:%.*]] = icmp ult i64 [[NEXT]], [[N]]
; CHECK-NEXT: br i1 [[DONE_NOT]], label %[[LOOP]], label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
-; CHECK-NEXT: ret double [[RESULT]]
+; CHECK-NEXT: ret double [[RESULT1]]
;
entry:
br label %loop
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
index b3acb80c5fdb0..86d6a445ca43e 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
@@ -22,9 +22,9 @@ define dso_local noundef nofpclass(nan inf) float @_Z4testPKfS0_ii(ptr noundef %
; CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[TMP12]], align 4, !tbaa [[TBAA4]]
; CHECK-NEXT: [[TMP14:%.*]] = fsub fast float [[TMP11]], [[TMP13]]
; CHECK-NEXT: [[TMP15:%.*]] = fmul fast float [[TMP14]], [[TMP14]]
-; CHECK-NEXT: [[OP_RDX:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP15]], <20 x float> [[TMP9]])
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP0]], i64 [[TMP5]]
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP1]], i64 [[TMP4]]
+; CHECK-NEXT: [[OP_RDX:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP15]], <20 x float> [[TMP9]])
; CHECK-NEXT: [[TMP18:%.*]] = load <20 x float>, ptr [[TMP16]], align 4, !tbaa [[TBAA4]]
; CHECK-NEXT: [[TMP19:%.*]] = load <20 x float>, ptr [[TMP17]], align 4, !tbaa [[TBAA4]]
; CHECK-NEXT: [[TMP20:%.*]] = fsub fast <20 x float> [[TMP18]], [[TMP19]]
@@ -35,79 +35,79 @@ define dso_local noundef nofpclass(nan inf) float @_Z4testPKfS0_ii(ptr noundef %
; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[TMP24]], align 4, !tbaa [[TBAA4]]
; CHECK-NEXT: [[TMP26:%.*]] = fsub fast float [[TMP23]], [[TMP25]]
; CHECK-NEXT: [[TMP27:%.*]] = fmul fast float [[TMP26]], [[TMP26]]
-; CHECK-NEXT: [[OP_RDX_1:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP27]], <20 x float> [[TMP21]])
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP16]], i64 [[TMP5]]
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP17]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP30:%.*]] = fadd fast float [[OP_RDX_1]], [[OP_RDX]]
-; CHECK-NEXT: [[TMP31:%.*]] = load <20 x float>, ptr [[TMP28]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP32:%.*]] = load <20 x float>, ptr [[TMP29]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP33:%.*]] = fsub fast <20 x float> [[TMP31]], [[TMP32]]
-; CHECK-NEXT: [[TMP34:%.*]] = fmul fast <20 x float> [[TMP33]], [[TMP33]]
-; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP28]], i64 80
-; CHECK-NEXT: [[TMP36:%.*]] = load float, ptr [[TMP35]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP29]], i64 80
-; CHECK-NEXT: [[TMP38:%.*]] = load float, ptr [[TMP37]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP39:%.*]] = fsub fast float [[TMP36]], [[TMP38]]
-; CHECK-NEXT: [[TMP40:%.*]] = fmul fast float [[TMP39]], [[TMP39]]
-; CHECK-NEXT: [[OP_RDX_2:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP40]], <20 x float> [[TMP34]])
-; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP28]], i64 [[TMP5]]
-; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP29]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP43:%.*]] = fadd fast float [[OP_RDX_2]], [[TMP30]]
-; CHECK-NEXT: [[TMP44:%.*]] = load <20 x float>, ptr [[TMP41]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP45:%.*]] = load <20 x float>, ptr [[TMP42]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP46:%.*]] = fsub fast <20 x float> [[TMP44]], [[TMP45]]
-; CHECK-NEXT: [[TMP47:%.*]] = fmul fast <20 x float> [[TMP46]], [[TMP46]]
+; CHECK-NEXT: [[OP_RDX_1:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP27]], <20 x float> [[TMP21]])
+; CHECK-NEXT: [[OP_RDX3_1:%.*]] = fadd fast float [[OP_RDX_1]], [[OP_RDX]]
+; CHECK-NEXT: [[TMP30:%.*]] = load <20 x float>, ptr [[TMP28]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP31:%.*]] = load <20 x float>, ptr [[TMP29]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP32:%.*]] = fsub fast <20 x float> [[TMP30]], [[TMP31]]
+; CHECK-NEXT: [[TMP33:%.*]] = fmul fast <20 x float> [[TMP32]], [[TMP32]]
+; CHECK-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP28]], i64 80
+; CHECK-NEXT: [[TMP35:%.*]] = load float, ptr [[TMP34]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP29]], i64 80
+; CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP36]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP38:%.*]] = fsub fast float [[TMP35]], [[TMP37]]
+; CHECK-NEXT: [[TMP39:%.*]] = fmul fast float [[TMP38]], [[TMP38]]
+; CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP28]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP41:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP29]], i64 [[TMP4]]
+; CHECK-NEXT: [[OP_RDX_2:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP39]], <20 x float> [[TMP33]])
+; CHECK-NEXT: [[OP_RDX3_2:%.*]] = fadd fast float [[OP_RDX_2]], [[OP_RDX3_1]]
+; CHECK-NEXT: [[TMP42:%.*]] = load <20 x float>, ptr [[TMP40]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP43:%.*]] = load <20 x float>, ptr [[TMP41]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP44:%.*]] = fsub fast <20 x float> [[TMP42]], [[TMP43]]
+; CHECK-NEXT: [[TMP45:%.*]] = fmul fast <20 x float> [[TMP44]], [[TMP44]]
+; CHECK-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP40]], i64 80
+; CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[TMP46]], align 4, !tbaa [[TBAA4]]
; CHECK-NEXT: [[TMP48:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP41]], i64 80
; CHECK-NEXT: [[TMP49:%.*]] = load float, ptr [[TMP48]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP42]], i64 80
-; CHECK-NEXT: [[TMP51:%.*]] = load float, ptr [[TMP50]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP52:%.*]] = fsub fast float [[TMP49]], [[TMP51]]
-; CHECK-NEXT: [[TMP53:%.*]] = fmul fast float [[TMP52]], [[TMP52]]
-; CHECK-NEXT: [[OP_RDX_3:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP53]], <20 x float> [[TMP47]])
-; CHECK-NEXT: [[TMP54:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP41]], i64 [[TMP5]]
-; CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP42]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP56:%.*]] = fadd fast float [[OP_RDX_3]], [[TMP43]]
-; CHECK-NEXT: [[TMP57:%.*]] = load <20 x float>, ptr [[TMP54]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP58:%.*]] = load <20 x float>, ptr [[TMP55]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP59:%.*]] = fsub fast <20 x float> [[TMP57]], [[TMP58]]
-; CHECK-NEXT: [[TMP60:%.*]] = fmul fast <20 x float> [[TMP59]], [[TMP59]]
-; CHECK-NEXT: [[TMP61:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP54]], i64 80
-; CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[TMP61]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP63:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP55]], i64 80
-; CHECK-NEXT: [[TMP64:%.*]] = load float, ptr [[TMP63]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP65:%.*]] = fsub fast float [[TMP62]], [[TMP64]]
-; CHECK-NEXT: [[TMP66:%.*]] = fmul fast float [[TMP65]], [[TMP65]]
-; CHECK-NEXT: [[OP_RDX_4:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP66]], <20 x float> [[TMP60]])
-; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP54]], i64 [[TMP5]]
-; CHECK-NEXT: [[TMP68:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP55]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP69:%.*]] = fadd fast float [[OP_RDX_4]], [[TMP56]]
-; CHECK-NEXT: [[TMP70:%.*]] = load <20 x float>, ptr [[TMP67]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP71:%.*]] = load <20 x float>, ptr [[TMP68]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP72:%.*]] = fsub fast <20 x float> [[TMP70]], [[TMP71]]
-; CHECK-NEXT: [[TMP73:%.*]] = fmul fast <20 x float> [[TMP72]], [[TMP72]]
-; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP67]], i64 80
-; CHECK-NEXT: [[TMP75:%.*]] = load float, ptr [[TMP74]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP68]], i64 80
-; CHECK-NEXT: [[TMP77:%.*]] = load float, ptr [[TMP76]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP78:%.*]] = fsub fast float [[TMP75]], [[TMP77]]
-; CHECK-NEXT: [[TMP79:%.*]] = fmul fast float [[TMP78]], [[TMP78]]
-; CHECK-NEXT: [[OP_RDX_5:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP79]], <20 x float> [[TMP73]])
-; CHECK-NEXT: [[TMP80:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP67]], i64 [[TMP5]]
-; CHECK-NEXT: [[TMP81:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP68]], i64 [[TMP4]]
-; CHECK-NEXT: [[TMP82:%.*]] = fadd fast float [[OP_RDX_5]], [[TMP69]]
-; CHECK-NEXT: [[TMP83:%.*]] = load <20 x float>, ptr [[TMP80]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP84:%.*]] = load <20 x float>, ptr [[TMP81]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP85:%.*]] = fsub fast <20 x float> [[TMP83]], [[TMP84]]
-; CHECK-NEXT: [[TMP86:%.*]] = fmul fast <20 x float> [[TMP85]], [[TMP85]]
-; CHECK-NEXT: [[TMP87:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP80]], i64 80
-; CHECK-NEXT: [[TMP88:%.*]] = load float, ptr [[TMP87]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP89:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP81]], i64 80
-; CHECK-NEXT: [[TMP90:%.*]] = load float, ptr [[TMP89]], align 4, !tbaa [[TBAA4]]
-; CHECK-NEXT: [[TMP91:%.*]] = fsub fast float [[TMP88]], [[TMP90]]
-; CHECK-NEXT: [[TMP92:%.*]] = fmul fast float [[TMP91]], [[TMP91]]
-; CHECK-NEXT: [[OP_RDX_6:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP92]], <20 x float> [[TMP86]])
-; CHECK-NEXT: [[TMP93:%.*]] = fadd fast float [[OP_RDX_6]], [[TMP82]]
-; CHECK-NEXT: ret float [[TMP93]]
+; CHECK-NEXT: [[TMP50:%.*]] = fsub fast float [[TMP47]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = fmul fast float [[TMP50]], [[TMP50]]
+; CHECK-NEXT: [[TMP52:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP40]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP41]], i64 [[TMP4]]
+; CHECK-NEXT: [[OP_RDX_3:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP51]], <20 x float> [[TMP45]])
+; CHECK-NEXT: [[OP_RDX3_3:%.*]] = fadd fast float [[OP_RDX_3]], [[OP_RDX3_2]]
+; CHECK-NEXT: [[TMP54:%.*]] = load <20 x float>, ptr [[TMP52]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP55:%.*]] = load <20 x float>, ptr [[TMP53]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP56:%.*]] = fsub fast <20 x float> [[TMP54]], [[TMP55]]
+; CHECK-NEXT: [[TMP57:%.*]] = fmul fast <20 x float> [[TMP56]], [[TMP56]]
+; CHECK-NEXT: [[TMP58:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP52]], i64 80
+; CHECK-NEXT: [[TMP59:%.*]] = load float, ptr [[TMP58]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP60:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP53]], i64 80
+; CHECK-NEXT: [[TMP61:%.*]] = load float, ptr [[TMP60]], align 4, !tbaa [[TBAA4]]
+; CHECK-NEXT: [[TMP62:%.*]] = fsub fast float [[TMP59]], [[TMP61]]
+; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP62]], [[TMP62]]
+; CHECK-NEXT: [[TMP64:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP52]], i64 [[TMP5]]
+; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP53]], i64 [[TMP4]]
+; CHECK-NEXT: [[OP_RDX_4:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v20f32(float [[TMP63]], <20 x float> [[TMP57]])
+; CHECK-NEXT: [[OP_RDX3_4:%.*]] = fadd fast float [[OP_RDX_4]], [[OP_RDX3_3]]
+; CHECK-NEXT: [[TMP66:%.*]] = load <20 x float>, ptr [[TMP64]],...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/218675
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