[llvm] [AArch64] C1-Premium SME definitions (PR #212482)

[Nashe Mncube via llvm-commits]

================
@@ -2348,4 +2781,191 @@ def : InstRW<[C1PWrite_2c_1V], (instregex "^(BCAX|EOR3)_ZZZZ$",
 // Crypto SM4 ops
 def : InstRW<[C1PWrite_4c_1V0], (instregex "^SM4E(KEY)?_ZZZ_S$")>;
 
+// SME predicates
+// -----------------------------------------------------------------------------
+
+// Signed/unsigned pair-producing while compare
+def : InstRW<[C1PWrite_2c_1M_StreamingCMEVX0ALU],
+             (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_2PXX")>;
+
+// SVE instructions added by SME but not sent to CME when in Streaming SVE mode
+// -----------------------------------------------------------------------------
+
+// Add/Read multiple of streaming SVE predicate/vector register size to scalar register
+def : InstRW<[C1PWrite_1c_1I], (instrs ADDSPL_XXI, ADDSVL_XXI, RDSVLI_XI)>;
+
+// Predicate counting scalar to count from predicate-as-counter
+def : InstRW<[C1PWrite_2c_1M], (instregex "^CNTP_XCI_[BHSD]$")>;
+
+// Set predicates from predicate-as-counter
+def : InstRW<[C1PWrite_2c_1M], (instregex "^PEXT_PCI_[BHSD]$")>;
+
+// Set pair of predicates from predicate-as-counter
+def : InstRW<[C1PWrite_3c_1M], (instregex "^PEXT_2PCI_[BHSD]$")>;
+
+// Predicate as counter set
+def : InstRW<[C1PWrite_1c_1M], (instregex "^PTRUE_C_[BHSD]$")>;
+
+// Loop control, based on GPR generating predicate as counter
+def : InstRW<[C1PWrite_1c_1M], (instregex "^WHILE(GE|GT|HI|HS|LE|LO|LS|LT)_CXX_[BHSD]$")>;
+
+// SME-added SVE instructions that stay on-core when Streaming SVE mode is modelled
+def : InstRW<[C1PWrite_4c_1V_StreamingCMEMML0], (instregex "^BFMLSLB_Z", "^BFMLSLT_Z")>;
+def : InstRW<[C1PWrite_2c_1V_StreamingCMEVXALU_5c], (instregex "^FCLAMP_ZZZ")>;
+def : InstRW<[C1PWrite_4c_1V_StreamingCMEVXALU], (instregex "^FDOT_(ZZZ|ZZZI)?(_S|_BtoS|_BtoH|HtoS)$")>;
+def : InstRW<[C1PWrite_2c_2M_StreamingCMEPERM], (instregex "^PSEL_PPPRI")>;
+def : InstRW<[C1PWrite_2c_1V_StreamingCMEPERM], (instregex "^REVD_ZPmZ")>;
+def : InstRW<[C1PWrite_2c_1V_StreamingCMEVXALU], (instregex "^(S|U)CLAMP_ZZZ")>;
+def : InstRW<[C1PWrite_2c_1V_StreamingCMEVXALU_1CMEPERMS],
+             (instregex "^SQCVTUN_Z2Z_StoH")>;
+def : InstRW<[C1PWrite_3c_1V01_StreamingCMEVXALU], (instregex "^SQRSHRUN_Z2ZI_StoH")>;
+
+// SVE instructions added by SME and only available in Streaming SVE mode
+// -----------------------------------------------------------------------------
+
+// Horizontal and vertical ZA reductions.
+def : InstRW<[C1PWrite_4c_1CMEVXALU_4rc],
+             (instregex "^ADDHA_MPPZ_(S(_PSEUDO_S)?|D(_PSEUDO_D)?)$",
+                        "^ADDVA_MPPZ_(S(_PSEUDO_S)?|D(_PSEUDO_D)?)$")>;
+
+// Outer-product ZA updates.
+def : InstRW<[C1PWrite_2c_1CMEMML0_2rc],
+             (instregex "^BMOPA_MPPZZ_S(_PSEUDO)?$", "^BMOPS_MPPZZ_S(_PSEUDO)?$",
+                        "^(SMOPA|UMOPA|SMOPS|UMOPS)_MPPZZ_(S|D|HtoS)(_PSEUDO)?$",
+                        "^(SUMOPA|USMOPA|SUMOPS|USMOPS)_MPPZZ_(S|D)(_PSEUDO)?$")>;
+def : InstRW<[C1PWrite_4c_1CMEMML0_2rc],
+             (instregex "^(F?MOPA|F?MOPS)_MPPZZ_(S|D|H)(_PSEUDO)?$",
+                        "^F?MOP(AL|SL)_MPPZZ(_PSEUDO)?$",
+                        "^(BFMOPA|BFMOPS)_MPPZZ(_H)?(_PSEUDO)?$")>;
+
+// ZA accumulators updated through multi-vector add/subtract operations.
+def : InstRW<[C1PWrite_2c_1CMEMML0_1rc],
+             (instregex "^(ADD|SUB)_VG2_M2(Z|ZZ|Z2Z)_[SD](_PSEUDO)?$")>;
+def : InstRW<[C1PWrite_2c_1CMEMML0_2rc],
+             (instregex "^(ADD|SUB)_VG4_M4(Z|ZZ|Z4Z)_[SD](_PSEUDO)?$")>;
+def : InstRW<[C1PWrite_4c_1CMEMML0_1rc],
+             (instregex "^(FADD|FSUB|BFADD|BFSUB)_VG2_M2Z_[HSD](_PSEUDO)?$")>;
+def : InstRW<[C1PWrite_4c_1CMEMML0_2rc],
+             (instregex "^(FADD|FSUB|BFADD|BFSUB)_VG4_M4Z_[HSD](_PSEUDO)?$")>;
+def : InstRW<[C1PWrite_5c_1CMEVXALU_1rc], (instregex "^ADD_VG2_2ZZ_")>;
+def : InstRW<[C1PWrite_6c_1CMEVXALU_4rc], (instregex "^ADD_VG4_4ZZ_")>;
+
+// Streaming-only clamp, convert and shift families.
+def : InstRW<[C1PWrite_5c_1CMEVXALU_1rc],
+             (instregex "^FCLAMP_VG2_2Z2Z_", "^BFCLAMP_VG2_2ZZZ",
+                        "^(S|U)CLAMP_VG2_2Z2Z_", "^(FMAX|FMIN)_VG2_2(ZZ|Z2Z)_",
+                        "^FA(MAX|MIN)_2Z2Z_", "^SQDMULH_VG2_2ZZ_",
+                        "^(S|U)RSHL_VG2_2ZZ_")>;
+def : InstRW<[C1PWrite_7c_1CMEVXALU_4rc],
+             (instregex "^FCLAMP_VG4_4Z4Z_", "^BFCLAMP_VG4_4ZZZ",
+                        "^(S|U)CLAMP_VG4_4Z4Z_")>;
+def : InstRW<[C1PWrite_4c_1CMEVXALU_2rc],
+             (instregex "^(S|U)(MAX|MIN)_VG2_2(ZZ|Z2Z)_",
+                        "^(FMAXNM|FMINNM)_VG2_2(ZZ|Z2Z)_",
+                        "^SQDMULH_VG2_2Z2Z_", "^(S|U)RSHL_VG2_2Z2Z_",
+                        "^(SQRSHR|UQRSHR)_VG2_Z2ZI_",
+                        "^(FRINT(A|M|N|P))_2Z2Z_")>;
+def : InstRW<[C1PWrite_4c_1CMEVXALU_4rc],
+             (instregex "^(S|U)(MAX|MIN)_VG4_4Z4Z_",
+                        "^(S|U)RSHL_VG4_4Z4Z_")>;
+def : InstRW<[C1PWrite_5c_1CMEVXALU_4rc],
+             (instregex "^(S|U)(MAX|MIN)_VG4_4ZZ_",
+                        "^(FMAX|FMIN|FMAXNM|FMINNM)_VG4_4(ZZ|Z4Z)_",
+        "^(BFMAX|BFMIN|BFMAXNM|BFMINNM)_VG4_4(Z2Z|ZZ)_",
+                        "^SQDMULH_VG4_4(ZZ|Z4Z)_", "^(FRINT(A|M|N|P))_4Z4Z_",
+                        "^FSCALE_4(ZZ|Z4Z)_")>;
+def : InstRW<[C1PWrite_4c_1CMEVXALU_2rc],
+             (instregex "^(BFMAX|BFMIN|BFMAXNM|BFMINNM)_VG2_2(ZZ|Z2Z)_",
+                        "^FSCALE_2(ZZ|Z2Z)_", "^FCVTZS_2Z2Z_StoS$",
+                        "^FCVTZU_2Z2Z_StoS$", "^F[12]CVT_2?ZZ_BtoH$",
+                        "^F[12]CVTL(T_ZZ|_2ZZ)_BtoH$",
+                        "^FCVT_Z2Z_(HtoB|StoH)$", "^FCVT_2ZZ_H_S$",
----------------
nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/212482