[llvm] [AArch64] C1-Premium SME definitions (PR #212482)

[Nashe Mncube via llvm-commits]

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@@ -1146,18 +1584,18 @@ def : InstRW<[C1PWrite_11c_V1_4rc], (instrs FDIVv4f32)>;
 def : InstRW<[C1PWrite_13c_V1_2rc], (instrs FDIVv2f64)>;
 
 // ASIMD FP max/min, reduce, F32 and D-form F16
-def : InstRW<[C1PWrite_4c_2V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
+def : InstRW<[C1PWrite_4c_2V_CMEFPReduceD], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
 
 // ASIMD FP max/min, reduce, Q-form F16
-def : InstRW<[C1PWrite_6c_3V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
+def : InstRW<[C1PWrite_6c_3V_CMEFPReduceMaxMin], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
 
 // ASIMD FP multiply
 def : InstRW<[C1PWrite_3c_1V], (instregex "^FMULv", "^FMULXv", "^FMULX(16|32|64)")>;
 
 // ASIMD FP multiply accumulate
 // ASIMD FP multiply accumulate long
-def : InstRW<[C1PWr_VFMA, C1PRd_VFMA, C1PRd_VFMA], (instregex "^FMLAv", "^FMLSv", 
-                                                  "^FML[AS]L2?(lane)?v")>;
+def : InstRW<[C1PWr_VFMA_CME, C1PRd_VFMA, C1PRd_VFMA],
+             (instregex "^FMLAv", "^FMLSv", "^FML[AS]L2?(lane)?v")>;
 
 // ASIMD FP round, D-form F32 and Q-form F64
 def : InstRW<[C1PWrite_3c_1V],
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nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/212482