[llvm] [M68k] Implement `CLR` instruction encoding and logic (PR #216636)

[Dan Salvato via llvm-commits]

================
@@ -609,6 +637,29 @@ bool M68kInstrInfo::ExpandMOVEM(MachineInstrBuilder &MIB,
   return true;
 }
 
+void M68kInstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator Iter,
+                                       DebugLoc &DL,
+                                       bool AllowSideEffects) const {
+  // Clear an address register by subtracting it from itself.
+  if (M68k::AR32RegClass.contains(Reg)) {
----------------
dansalvato wrote:

The issue with AR16 is that word-sized operations on address registers (move, add, sub) sign-extend the operand to 32 bits before performing the operation. So it's actually a symptom of a more complicated modeling problem, where we can expect subreg operations on data registers to preserve the upper bits, but we can't expect that on address registers.

IMO, the immediate fix needed here is to change `MOVI16ri` to `MOVI16di`, because the side effects are different depending on the type of register, so they shouldn't be bundled into a single pseudo. The pseudo expansion logic already optimizes `MOVI32ri` to use a sign-extended 16-bit immediate value for address registers when possible, so nothing is lost in doing this—it would just more strongly guarantee that codegen never attempts to clear an AR16. If that sounds reasonable, I can add that change to this patch.

https://github.com/llvm/llvm-project/pull/216636