[llvm] [M68k] Implement `CLR` instruction encoding and logic (PR #216636)

[Dan Salvato via llvm-commits]

================
@@ -333,6 +335,16 @@ void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator I, DebugLoc DL,
                             unsigned Reg, MVT From, MVT To) const {
 
+  // On 68000, SWAP -> CLR -> SWAP is faster than AND with mask.
----------------
dansalvato wrote:

The optimization applies to all pre-020 CPUs, because the 32-bit immediate takes two extra bus reads (8 cycles), plus 8 cycles for the AND operation. `SWAP -> CLR -> SWAP` is also 3 bus reads, but 4 cycles each. Same code size, but 4 cycles faster.

My main source for cycle and bus information is the YACHT document, which is the most comprehensive and thoroughly-researched source I'm aware of: https://github.com/danorf69/YACHT/blob/main/Yacht.txt

https://github.com/llvm/llvm-project/pull/216636