[llvm] [AArch64][SelectionDAG] Reduce redundant loads for constant <2 x i64> values (PR #214864)

[Eli Friedman via llvm-commits]

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@@ -90,21 +90,22 @@ define void @build_vector_0_dec3_v8i32(ptr %a) {
 define void @build_vector_minus2_dec32_v4i64(ptr %a) {
 ; CHECK-LABEL: build_vector_minus2_dec32_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-32 // =0xffffffffffffffe0
-; CHECK-NEXT:    index z0.d, #0, x8
-; CHECK-NEXT:    movprfx z1, z0
-; CHECK-NEXT:    sub z1.d, z1.d, #66 // =0x42
-; CHECK-NEXT:    sub z0.d, z0.d, #2 // =0x2
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    mov x8, #-98 // =0xffffffffffffff9e
+; CHECK-NEXT:    mov x9, #-66 // =0xffffffffffffffbe
+; CHECK-NEXT:    mov x10, #-34 // =0xffffffffffffffde
+; CHECK-NEXT:    mov x11, #-2 // =0xfffffffffffffffe
+; CHECK-NEXT:    stp x9, x8, [x0, #16]
+; CHECK-NEXT:    stp x11, x10, [x0]
 ; CHECK-NEXT:    ret
 ;
 ; NONEON-NOSVE-LABEL: build_vector_minus2_dec32_v4i64:
 ; NONEON-NOSVE:       // %bb.0:
-; NONEON-NOSVE-NEXT:    adrp x8, .LCPI4_0
-; NONEON-NOSVE-NEXT:    adrp x9, .LCPI4_1
-; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI4_0]
-; NONEON-NOSVE-NEXT:    ldr q1, [x9, :lo12:.LCPI4_1]
-; NONEON-NOSVE-NEXT:    stp q1, q0, [x0]
+; NONEON-NOSVE-NEXT:    mov x8, #-98 // =0xffffffffffffff9e
+; NONEON-NOSVE-NEXT:    mov x9, #-66 // =0xffffffffffffffbe
+; NONEON-NOSVE-NEXT:    mov x10, #-34 // =0xffffffffffffffde
+; NONEON-NOSVE-NEXT:    mov x11, #-2 // =0xfffffffffffffffe
+; NONEON-NOSVE-NEXT:    stp x9, x8, [x0, #16]
+; NONEON-NOSVE-NEXT:    stp x11, x10, [x0]
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efriedma-quic wrote:

> Would you say that in this instance its worth adding an extra store in exchange for removing two loads

In most cases this tradeoff probably makes sense.  There are maybe some edge cases involving loops, but I don't think that's a big issue.

https://github.com/llvm/llvm-project/pull/214864