[llvm] [AArch64][SelectionDAG] Reduce redundant loads for constant <2 x i64> values (PR #214864)

[Eli Friedman via llvm-commits]

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@@ -90,21 +90,22 @@ define void @build_vector_0_dec3_v8i32(ptr %a) {
 define void @build_vector_minus2_dec32_v4i64(ptr %a) {
 ; CHECK-LABEL: build_vector_minus2_dec32_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-32 // =0xffffffffffffffe0
-; CHECK-NEXT:    index z0.d, #0, x8
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efriedma-quic wrote:

Oh, I see, pre-isel it's add(step_vector(), splat_vector()).  Then the isel patterns check for step_vector_oneuse, which fails here because it has two uses.  (The one-use check here is probably wrong, since the sharing isn't actually helpful here, but not really relevant to this patch.)

Doing splitConst128VectorStore after we've already created a constant pool load is tricky; I don't think that's worth pursuing.

https://github.com/llvm/llvm-project/pull/214864