[llvm] [AMDGPU] Restrict DPP combine from performing bad transformations when handling certain REV subtraction insts that use Src1 as the DPP operand (PR #216835)

[Domenic Nutile via llvm-commits]

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@@ -117,6 +117,51 @@ FunctionPass *llvm::createGCNDPPCombinePass() {
   return new GCNDPPCombineLegacy();
 }
 
+// Some opcodes use Src1 for DPP instead of Src0, because the sequencer
+// transforms them and reverse the order of their operands at runtime.
+//
+// Documentation is incomplete on which instructions are effected, so
+// much is derived from experimentation.
+//
+// Listed as target-independent pseudos; the per-subtarget MC opcodes
+// (V_SUBREV_NC_U32_e32_gfx11 and friends) are all reached through these.
+static bool isSrc1DPPRevOpcode(unsigned Opc, const GCNSubtarget *ST) {
+  switch (Opc) {
+  // v_subrev_u16 (gfx9)
+  case AMDGPU::V_SUBREV_U16_e32:
+  case AMDGPU::V_SUBREV_U16_e64:
+  // v_subrev_u32 (gfx9) / v_subrev_nc_u32 (gfx10+)
+  case AMDGPU::V_SUBREV_U32_e32:
+  case AMDGPU::V_SUBREV_U32_e64:
+  // v_subrev_co_u32
+  case AMDGPU::V_SUBREV_CO_U32_e32:
+  case AMDGPU::V_SUBREV_CO_U32_e64:
+  // v_subbrev_u32 (gfx9) / v_subrev_co_ci_u32 (gfx10+)
+  case AMDGPU::V_SUBBREV_U32_e32:
+  case AMDGPU::V_SUBBREV_U32_e64:
+    return true;
+  // REV shift opcodes worked this way before GFX10.3
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saxlungs wrote:

I will verify empirically

https://github.com/llvm/llvm-project/pull/216835