[llvm] [AMDGPU] Restrict DPP combine from performing bad transformations when handling certain REV subtraction insts that use Src1 as the DPP operand (PR #216835)

[Matt Arsenault via llvm-commits]

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@@ -117,6 +117,51 @@ FunctionPass *llvm::createGCNDPPCombinePass() {
   return new GCNDPPCombineLegacy();
 }
 
+// Some opcodes use Src1 for DPP instead of Src0, because the sequencer
+// transforms them and reverse the order of their operands at runtime.
+//
+// Documentation is incomplete on which instructions are effected, so
+// much is derived from experimentation.
+//
+// Listed as target-independent pseudos; the per-subtarget MC opcodes
+// (V_SUBREV_NC_U32_e32_gfx11 and friends) are all reached through these.
+static bool isSrc1DPPRevOpcode(unsigned Opc, const GCNSubtarget *ST) {
----------------
arsenm wrote:

```suggestion
static bool isSrc1DPPRevOpcode(const GCNSubtarget &ST, unsigned Opc) {
```
Though maybe this should just directly be a method in SIInstrInfo

https://github.com/llvm/llvm-project/pull/216835