[llvm] 58d7047 - [NFC][AMDGPU] Use target features to guard WMMA intrinsics (#217681)
via llvm-commits
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Thu Aug 20 10:16:00 PDT 2026
Author: Shilei Tian
Date: 2026-08-20T17:15:56Z
New Revision: 58d704752799aec42c9bf2ce3c03f812cf09a0c5
URL: https://github.com/llvm/llvm-project/commit/58d704752799aec42c9bf2ce3c03f812cf09a0c5
DIFF: https://github.com/llvm/llvm-project/commit/58d704752799aec42c9bf2ce3c03f812cf09a0c5.diff
LOG: [NFC][AMDGPU] Use target features to guard WMMA intrinsics (#217681)
Added:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.target-features.ll
Modified:
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index b07c9657753ec..b321b9155a199 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -3093,21 +3093,25 @@ class AMDGPUWmmaIntrinsicIU<LLVMType AB, LLVMType CD> :
// The content of the other 16-bit half is preserved from the input.
defset list<Intrinsic> AMDGPUWMMAIntrinsicsGFX11 = {
-def int_amdgcn_wmma_f16_16x16x16_f16_tied : AMDGPUWmmaIntrinsicOPSEL<llvm_anyfloat_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_bf16_16x16x16_bf16_tied : AMDGPUWmmaIntrinsicOPSEL<llvm_anyint_ty, llvm_anyint_ty>;
+let TargetFeatures = "wmma-256b-insts" in {
+ def int_amdgcn_wmma_f16_16x16x16_f16_tied : AMDGPUWmmaIntrinsicOPSEL<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_bf16_16x16x16_bf16_tied : AMDGPUWmmaIntrinsicOPSEL<llvm_anyint_ty, llvm_anyint_ty>;
+} // End TargetFeatures = "wmma-256b-insts"
// WMMA GFX11Plus
-def int_amdgcn_wmma_f32_16x16x16_f16 : AMDGPUWmmaIntrinsic<llvm_anyfloat_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_f32_16x16x16_bf16 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_i32_16x16x16_iu8 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
-def int_amdgcn_wmma_i32_16x16x16_iu4 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
-
-// GFX11: The OPSEL intrinsics read from and write to one half of the registers, selected by the op_sel bit.
-// The content of the other 16-bit half is undefined.
-// GFX12: The op_sel bit must be 0.
-def int_amdgcn_wmma_f16_16x16x16_f16 : AMDGPUWmmaIntrinsicOPSEL<llvm_anyfloat_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_bf16_16x16x16_bf16 : AMDGPUWmmaIntrinsicOPSEL<llvm_anyint_ty, llvm_anyint_ty>;
+let TargetFeatures = "wmma-256b-insts|wmma-128b-insts" in {
+ def int_amdgcn_wmma_f32_16x16x16_f16 : AMDGPUWmmaIntrinsic<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_f32_16x16x16_bf16 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_i32_16x16x16_iu8 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
+ def int_amdgcn_wmma_i32_16x16x16_iu4 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
+
+ // GFX11: The OPSEL intrinsics read from and write to one half of the registers, selected by the op_sel bit.
+ // The content of the other 16-bit half is undefined.
+ // GFX12: The op_sel bit must be 0.
+ def int_amdgcn_wmma_f16_16x16x16_f16 : AMDGPUWmmaIntrinsicOPSEL<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_bf16_16x16x16_bf16 : AMDGPUWmmaIntrinsicOPSEL<llvm_anyint_ty, llvm_anyint_ty>;
+} // End TargetFeatures = "wmma-256b-insts|wmma-128b-insts"
}
//===----------------------------------------------------------------------===//
@@ -3215,13 +3219,15 @@ defset list<Intrinsic> AMDGPUWMMAIntrinsicsGFX12 = {
// These operations perform a matrix multiplication and accumulation of
// the form: D = A * B + C .
-// A and B are <8 x fp8> or <8 x bf8>, but since fp8 and bf8 are not supported by llvm we use <2 x i32>.
-def int_amdgcn_wmma_f32_16x16x16_fp8_fp8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_f32_16x16x16_fp8_bf8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_f32_16x16x16_bf8_fp8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_f32_16x16x16_bf8_bf8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
-// A and B are <16 x iu4>.
-def int_amdgcn_wmma_i32_16x16x32_iu4 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
+let TargetFeatures = "wmma-128b-insts" in {
+ // A and B are <8 x fp8> or <8 x bf8>, but since fp8 and bf8 are not supported by llvm we use <2 x i32>.
+ def int_amdgcn_wmma_f32_16x16x16_fp8_fp8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_f32_16x16x16_fp8_bf8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_f32_16x16x16_bf8_fp8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
+ def int_amdgcn_wmma_f32_16x16x16_bf8_bf8 : AMDGPUWmmaIntrinsic<llvm_anyint_ty, llvm_anyfloat_ty>;
+ // A and B are <16 x iu4>.
+ def int_amdgcn_wmma_i32_16x16x32_iu4 : AMDGPUWmmaIntrinsicIU<llvm_anyint_ty, llvm_anyint_ty>;
+} // End TargetFeatures = "wmma-128b-insts"
def int_amdgcn_swmmac_f32_16x16x32_f16 : AMDGPUSWmmacIntrinsicIdx<llvm_anyfloat_ty, llvm_anyfloat_ty, llvm_anyfloat_ty, llvm_anyint_ty>;
def int_amdgcn_swmmac_f32_16x16x32_bf16 : AMDGPUSWmmacIntrinsicIdx<llvm_anyint_ty, llvm_anyint_ty, llvm_anyfloat_ty, llvm_anyint_ty>;
@@ -4213,8 +4219,14 @@ class AMDGPUWmmaScaleF4IntrinsicModsC<LLVMType scale_ty> :
>;
defset list<Intrinsic> AMDGPUWMMAIntrinsicsGFX1250 = {
-def int_amdgcn_wmma_f64_16x16x4_f64 : AMDGPUWmmaIntrinsicModsAll<llvm_anyfloat_ty, llvm_anyfloat_ty>;
-def int_amdgcn_wmma_f32_16x16x4_f32 : AMDGPUWmmaIntrinsicModsC<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+let TargetFeatures = "gfx1251-gemm-insts" in {
+ def int_amdgcn_wmma_f64_16x16x4_f64 : AMDGPUWmmaIntrinsicModsAll<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+} // End TargetFeatures = "gfx1251-gemm-insts"
+
+let TargetFeatures = "gfx1250-insts" in {
+ def int_amdgcn_wmma_f32_16x16x4_f32 : AMDGPUWmmaIntrinsicModsC<llvm_anyfloat_ty, llvm_anyfloat_ty>;
+} // End TargetFeatures = "gfx1250-insts"
+
let TargetFeatures = "wmma-n16-insts" in {
def int_amdgcn_wmma_f32_16x16x32_bf16 : AMDGPUWmmaIntrinsicModsC<llvm_anyfloat_ty, llvm_anyfloat_ty>;
def int_amdgcn_wmma_f32_16x16x32_f16 : AMDGPUWmmaIntrinsicModsC<llvm_anyfloat_ty, llvm_anyfloat_ty>;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.target-features.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.target-features.ll
new file mode 100644
index 0000000000000..3fc00787d1781
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.target-features.ll
@@ -0,0 +1,39 @@
+; RUN: not llc -global-isel=0 -mtriple=amdgpu9.50 -filetype=null < %s 2>&1 | FileCheck %s
+; RUN: not llc -global-isel=1 -global-isel-abort=0 -mtriple=amdgpu9.50 -filetype=null < %s 2>&1 | FileCheck %s
+;
+; CHECK: llvm.amdgcn.wmma.f16.16x16x16.f16.tied requires target feature 'wmma-256b-insts'
+; CHECK: llvm.amdgcn.wmma.f32.16x16x16.f16 requires target feature 'wmma-256b-insts|wmma-128b-insts'
+; CHECK: llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8 requires target feature 'wmma-128b-insts'
+; CHECK: llvm.amdgcn.wmma.f32.16x16x4.f32 requires target feature 'gfx1250-insts'
+; CHECK: llvm.amdgcn.wmma.f64.16x16x4.f64 requires target feature 'gfx1251-gemm-insts'
+; CHECK: llvm.amdgcn.wmma.f32.16x16x32.bf16 requires target feature 'wmma-n16-insts'
+
+define <16 x half> @wmma_256b(<16 x half> %a, <16 x half> %b, <16 x half> %c) {
+ %result = call <16 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.tied(<16 x half> %a, <16 x half> %b, <16 x half> %c, i1 false)
+ ret <16 x half> %result
+}
+
+define <8 x float> @wmma_256b_or_128b(<16 x half> %a, <16 x half> %b, <8 x float> %c) {
+ %result = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16(<16 x half> %a, <16 x half> %b, <8 x float> %c)
+ ret <8 x float> %result
+}
+
+define <8 x float> @wmma_128b(<2 x i32> %a, <2 x i32> %b, <8 x float> %c) {
+ %result = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8(<2 x i32> %a, <2 x i32> %b, <8 x float> %c)
+ ret <8 x float> %result
+}
+
+define <8 x float> @gfx1250(<2 x float> %a, <2 x float> %b, <8 x float> %c) {
+ %result = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x4.f32.v8f32.v2f32(<2 x float> %a, <2 x float> %b, i16 0, <8 x float> %c, i1 false, i1 false)
+ ret <8 x float> %result
+}
+
+define <8 x double> @gfx1251_gemm(<2 x double> %a, <2 x double> %b, <8 x double> %c) {
+ %result = call <8 x double> @llvm.amdgcn.wmma.f64.16x16x4.f64.v8f64.v2f64(i1 false, <2 x double> %a, i1 false, <2 x double> %b, i16 0, <8 x double> %c, i1 false, i1 false)
+ ret <8 x double> %result
+}
+
+define <8 x float> @wmma_n16(<16 x bfloat> %a, <16 x bfloat> %b, <8 x float> %c) {
+ %result = call <8 x float> @llvm.amdgcn.wmma.f32.16x16x32.bf16.v8f32.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b, i16 0, <8 x float> %c, i1 false, i1 false)
+ ret <8 x float> %result
+}
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