[llvm] [AMDGPU] Remove redundant register alignment check for _Align1 operands (PR #217645)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,45 @@
+# RUN: llc -mtriple=amdgpu9.50 -run-pass=machineverifier -filetype=null %s
+# RUN: llc -mtriple=amdgpu9.50 --passes='machine-function(verify)' -filetype=null %s
+
+# Instructions which declare an _Align1 operand register class can accept
+# unaligned tuples. ds_read_b96_tr_b6 declares AVLdSt_96_Align1, which resolves
+# to an unaligned register class in every HwMode, so these functions should pass
+# verification. The other two _Align1 instructions are covered by
+# verify-align1-operands-gfx1250.mir.
+
+---
+name: ds_read_b96_tr_b6_unaligned_vgpr
+body:             |
+  bb.0:
+    $vgpr0 = IMPLICIT_DEF
+    $vgpr1_vgpr2_vgpr3 = DS_READ_B96_TR_B6 $vgpr0, 32, 0, implicit $exec
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arsenm wrote:

We probably should fix this, we don't need both. the operand change can be handled with RegClassByHwMode 

https://github.com/llvm/llvm-project/pull/217645