[llvm] [CodeGen] Do not retype an already typed vreg in constrainRegAttrs (PR #217410)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 20 04:20:40 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/217410
>From d1ee138736e29ae834f5371cbb9e9b881b0fe092 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 19 Aug 2026 19:44:35 +0200
Subject: [PATCH 1/2] [CodeGen] Do not retype an already typed vreg in
constrainRegAttrs
With extended LLTs s32 and i32 compare equal, so the unconditional setType could silently retype a register behind the CSE map
This fixes the failing test introduced in https://github.com/llvm/llvm-project/pull/207419
---
llvm/lib/CodeGen/MachineRegisterInfo.cpp | 2 +-
.../GlobalISel/combine-binop-s64-with-s32-mask.mir | 9 ++++-----
.../test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll | 4 ++--
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index dbba413548018..98deb84176c02 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,7 +111,7 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
} else if (RegCB != ConstrainingRegCB)
return false;
}
- if (ConstrainingRegTy.isValid())
+ if (ConstrainingRegTy.isValid() && !RegTy.isValid())
setType(Reg, ConstrainingRegTy);
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
index 1c42ae83694d1..329149ed6907f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
@@ -1,5 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# UNSUPPORTED: true
# RUN: llc -mtriple=amdgpu6.00 -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s
---
@@ -158,8 +157,8 @@ body: |
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr1
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-NEXT: $sgpr0 = COPY [[C]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $sgpr0 = COPY [[C]](i32)
; CHECK-NEXT: $sgpr1 = COPY [[COPY]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%0:_(s32) = COPY $sgpr0
@@ -286,9 +285,9 @@ body: |
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
; CHECK-NEXT: $sgpr0 = COPY [[COPY]](s32)
- ; CHECK-NEXT: $sgpr1 = COPY [[C]](s32)
+ ; CHECK-NEXT: $sgpr1 = COPY [[C]](i32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index b9afd0dbdb7d7..c250d492f04ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
@@ -149,7 +149,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK-NEXT: $sgpr13 = COPY [[COPY12]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY13]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](i32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](s32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[LOAD]](p0), 0, csr_amdgpu_gfx90ainsts, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
>From 540b5c53e7ca264f0a48f65a4b668537d404e53f Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 20 Aug 2026 13:20:08 +0200
Subject: [PATCH 2/2] Address comment
---
llvm/lib/CodeGen/MachineRegisterInfo.cpp | 2 +-
.../combine-binop-s64-with-s32-mask.mir | 32 +++++++++----------
.../AMDGPU/GlobalISel/regbankselect-call.ll | 4 +--
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index 98deb84176c02..dbba413548018 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,7 +111,7 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
} else if (RegCB != ConstrainingRegCB)
return false;
}
- if (ConstrainingRegTy.isValid() && !RegTy.isValid())
+ if (ConstrainingRegTy.isValid())
setType(Reg, ConstrainingRegTy);
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
index 329149ed6907f..fb3bf9db3881b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
@@ -156,19 +156,19 @@ body: |
; CHECK-LABEL: name: test_and_mask_hi_with_merge_unmerge
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; CHECK-NEXT: $sgpr0 = COPY [[C]](i32)
- ; CHECK-NEXT: $sgpr1 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: $sgpr1 = COPY [[COPY]](i32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %0:_(i32) = COPY $sgpr0
+ %1:_(i32) = COPY $sgpr1
+ %2:_(s64) = G_MERGE_VALUES %0(i32), %1(i32)
%3:_(s64) = G_CONSTANT i64 -4294967296
%4:_(s64) = G_AND %2, %3
- %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4(s64)
- $sgpr0 = COPY %5(s32)
- $sgpr1 = COPY %6(s32)
+ %5:_(i32), %6:_(i32) = G_UNMERGE_VALUES %4(s64)
+ $sgpr0 = COPY %5(i32)
+ $sgpr1 = COPY %6(i32)
SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
...
---
@@ -284,19 +284,19 @@ body: |
; CHECK-LABEL: name: test_or_mask_hi_with_merge_unmerge
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1
- ; CHECK-NEXT: $sgpr0 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: $sgpr0 = COPY [[COPY]](i32)
; CHECK-NEXT: $sgpr1 = COPY [[C]](i32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %0:_(i32) = COPY $sgpr0
+ %1:_(i32) = COPY $sgpr1
+ %2:_(s64) = G_MERGE_VALUES %0(i32), %1(i32)
%3:_(s64) = G_CONSTANT i64 -4294967296
%4:_(s64) = G_OR %2, %3
- %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4(s64)
- $sgpr0 = COPY %5(s32)
- $sgpr1 = COPY %6(s32)
+ %5:_(i32), %6:_(i32) = G_UNMERGE_VALUES %4(s64)
+ $sgpr0 = COPY %5(i32)
+ $sgpr1 = COPY %6(i32)
SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
index c250d492f04ac..b9afd0dbdb7d7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(i32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
@@ -149,7 +149,7 @@ define amdgpu_kernel void @test_uniform_indirect_call_from_kernel(ptr %fptr) {
; CHECK-NEXT: $sgpr13 = COPY [[COPY12]](s32)
; CHECK-NEXT: $sgpr14 = COPY [[COPY13]](s32)
; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)
- ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](s32)
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY]](i32)
; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[LOAD]](p0), 0, csr_amdgpu_gfx90ainsts, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; CHECK-NEXT: S_ENDPGM 0
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