[llvm] [AMDGPU] Enable CSE in the GlobalISel post-legalizer combiner (PR #217258)

[Matt Arsenault via llvm-commits]

================
@@ -3265,11 +3270,10 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
       MIB.addGlobalAddress(GV, Offset, GAFlags + 1);
   }
 
-  if (!B.getMRI()->getRegClassOrNull(PCReg))
-    B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
-
   if (PtrTy.getSizeInBits() == 32)
     B.buildExtract(DstReg, PCReg, 0);
+  else
+    B.buildCast(DstReg, PCReg);
----------------
arsenm wrote:

This should be restricted to a specific cast 

https://github.com/llvm/llvm-project/pull/217258