[llvm] [AMDGPU] Enable CSE in the GlobalISel post-legalizer combiner (PR #217258)

[Matt Arsenault via llvm-commits]

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@@ -3280,24 +3284,17 @@ void AMDGPULegalizerInfo::buildAbsGlobalAddress(
   bool RequiresHighHalf = PtrTy.getSizeInBits() != 32;
 
   if (RequiresHighHalf && ST.has64BitLiterals()) {
-    if (!MRI.getRegClassOrNull(DstReg))
-      MRI.setRegClass(DstReg, &AMDGPU::SReg_64RegClass);
+    Register Addr =
+        MRI.createVirtualRegister({&AMDGPU::SReg_64RegClass, PtrTy});
     B.buildInstr(AMDGPU::S_MOV_B64)
-        .addDef(DstReg)
+        .addDef(Addr)
         .addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS64);
+    B.buildCast(DstReg, Addr);
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arsenm wrote:

Not sure why this needs a cast like above, the type isn't changing?

https://github.com/llvm/llvm-project/pull/217258