[llvm] [CodeGen] Do not retype an already typed vreg in constrainRegAttrs (PR #217410)

[Matt Arsenault via llvm-commits]

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@@ -111,7 +111,7 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
     } else if (RegCB != ConstrainingRegCB)
       return false;
   }
-  if (ConstrainingRegTy.isValid())
+  if (ConstrainingRegTy.isValid() && !RegTy.isValid())
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arsenm wrote:

I'd kind of expect this to refuse to constrain? 

https://github.com/llvm/llvm-project/pull/217410